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Fri, 13 Jun 2025 02:29:26 -0700 (PDT) From: James Clark Date: Fri, 13 Jun 2025 10:29:00 +0100 Subject: [PATCH v2 5/5] spi: spi-fsl-dspi: Report FIFO overflows as errors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250613-james-nxp-spi-dma-v2-5-017eecf24aab@linaro.org> References: <20250613-james-nxp-spi-dma-v2-0-017eecf24aab@linaro.org> In-Reply-To: <20250613-james-nxp-spi-dma-v2-0-017eecf24aab@linaro.org> To: Vladimir Oltean , Mark Brown Cc: Vladimir Oltean , Arnd Bergmann , Larisa Grigore , Frank Li , linux-spi@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 In target mode, the host sending more data than can be consumed would be a common problem for any message exceeding the FIFO or DMA buffer size. Cancel the whole message as soon as this condition is hit as the message will be corrupted. Only do this for target mode in a DMA transfer because we need to add a register read. In IRQ and polling modes always do it because SPI_SR was already read and it might catch some host mode programming/buffer management errors too. Signed-off-by: James Clark --- drivers/spi/spi-fsl-dspi.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 31432d533dea..f62f99f272b2 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -556,12 +556,24 @@ static void dspi_rx_dma_callback(void *arg) complete(&dma->cmd_rx_complete); } =20 +static int dspi_fifo_error(struct fsl_dspi *dspi, u32 spi_sr) +{ + if (spi_sr & (SPI_SR_TFUF | SPI_SR_RFOF)) { + dev_err_ratelimited(&dspi->pdev->dev, "FIFO errors:%s%s\n", + spi_sr & SPI_SR_TFUF ? " TX underflow," : "", + spi_sr & SPI_SR_RFOF ? " RX overflow," : ""); + return -EIO; + } + return 0; +} + static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) { size_t size =3D dspi_dma_transfer_size(dspi); struct device *dev =3D &dspi->pdev->dev; struct fsl_dspi_dma *dma =3D dspi->dma; int time_left; + u32 spi_sr; int i; =20 for (i =3D 0; i < dspi->words_in_flight; i++) @@ -610,7 +622,8 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *d= spi) =20 if (spi_controller_is_target(dspi->ctlr)) { wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); - return 0; + regmap_read(dspi->regmap, SPI_SR, &spi_sr); + return dspi_fifo_error(dspi, spi_sr); } =20 time_left =3D wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, @@ -1055,6 +1068,10 @@ static void dspi_poll(struct fsl_dspi *dspi) =20 if (spi_sr & SPI_SR_CMDTCF) break; + + dspi->cur_msg->status =3D dspi_fifo_error(dspi, spi_sr); + if (dspi->cur_msg->status) + return; } while (--tries); =20 if (!tries) { @@ -1071,6 +1088,7 @@ static void dspi_poll(struct fsl_dspi *dspi) static irqreturn_t dspi_interrupt(int irq, void *dev_id) { struct fsl_dspi *dspi =3D (struct fsl_dspi *)dev_id; + int status; u32 spi_sr; =20 regmap_read(dspi->regmap, SPI_SR, &spi_sr); @@ -1079,6 +1097,14 @@ static irqreturn_t dspi_interrupt(int irq, void *dev= _id) if (!(spi_sr & SPI_SR_CMDTCF)) return IRQ_NONE; =20 + status =3D dspi_fifo_error(dspi, spi_sr); + if (status) { + if (dspi->cur_msg) + WRITE_ONCE(dspi->cur_msg->status, status); + complete(&dspi->xfer_done); + return IRQ_HANDLED; + } + dspi_rxtx(dspi); =20 if (!dspi->len) { --=20 2.34.1