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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v3 35/44] x86/cacheinfo: Use parsed CPUID(0x4) Date: Fri, 13 Jun 2025 01:40:01 +0200 Message-ID: <20250612234010.572636-36-darwi@linutronix.de> In-Reply-To: <20250612234010.572636-1-darwi@linutronix.de> References: <20250612234010.572636-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the Intel CPUID(0x4) cacheinfo logic to use parsed CPUID access instead of issuing direct CPUID queries. Use the parsed CPUID access macro: cpuid_subleaf_count(c, 0x4) to determine the number of Intel CPUID(0x4) cache leaves instead of calling find_num_cache_leaves(), which internally issues direct CPUID queries. Since find_num_cache_leaves() is no longer needed for Intel code paths, make it AMD-specific. Rename it to amd_find_num_cache_leaves() and remove its Intel CPUID(0x4) logic. Adjust the AMD paths accordingly. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 0ed5dd6d29ef..07f0883f9fbe 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,16 +252,14 @@ static int amd_fill_cpuid4_info(int index, struct _cp= uid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; - u32 ignored; - - cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored); + const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x4, index); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, + (union _cpuid4_leaf_eax)(regs->eax), + (union _cpuid4_leaf_ebx)(regs->ebx), + (union _cpuid4_leaf_ecx)(regs->ecx)); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -273,17 +271,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf intel_fill_cpuid4_info(c, index, id4); } =20 -static int find_num_cache_leaves(struct cpuinfo_x86 *c) +static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; union _cpuid4_leaf_eax cache_eax; + unsigned int eax, ebx, ecx, edx; int i =3D -1; =20 - /* Do a CPUID(op) loop to calculate num_cache_leaves */ - op =3D (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_V= ENDOR_HYGON) ? 0x8000001d : 4; + /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ do { ++i; - cpuid_count(op, i, &eax, &ebx, &ecx, &edx); + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); return i; @@ -313,7 +310,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) * of threads sharing the L3 cache. */ u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; - u32 llc_index =3D find_num_cache_leaves(c) - 1; + u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; =20 cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); if (eax) @@ -344,7 +341,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -353,7 +350,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, @@ -425,7 +422,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) * that the number of leaves has been previously initialized. */ if (!ci->num_leaves) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x4); =20 if (!ci->num_leaves) return false; --=20 2.49.0