From nobody Tue Feb 10 10:58:51 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 673DB29B22D; Thu, 12 Jun 2025 16:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749744581; cv=none; b=f3oZ64lkUUEbE2DBpThzSqKGbZkdyeSbRIlCJ9SoZeNMhhOMoIxcX5s/ChOpDcFgi1cTYHb6WtBaQzvUuWsbZGcq77yavmbY1xyd5391vTf9zKPjgkRiwXUmPs/WOWrOqi9EKw2/F3PP4qtjb5Ev1jQjadk/rAzozTGgSH/cwd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749744581; c=relaxed/simple; bh=hE24lPXX0nLCS23tDnnAm3/lb8HkNfW+nj9tLhcpDQ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y6UKszTt3uwgtQBKlnTHGYT7i5kzQEuozggBTrPVeipW415vfVhK/n4/UEafBr6C0odixFm73t7RT/q1qgz86mTYHP+Fv8MuiODd1xlhGwe6mfHA6MR6rXpNKI5vDMfEjLtu82mSWLM1ZyZCIC/pfK1YjE4jn4DCkuc4AQpbNQU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YJLl5GUI; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YJLl5GUI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1749744580; x=1781280580; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hE24lPXX0nLCS23tDnnAm3/lb8HkNfW+nj9tLhcpDQ8=; b=YJLl5GUIKRluZsUCOZxG8snoFaR1FICEY1x4uBN8jEjeH8uV9e8neOsz xE4IdUojTouo14awxUAusYL82sIydDu1OwhIlrt/9tF12+KNbv1SgoLOu ycJSBgF9Nl7BGb+00UnN/BcxhZkaru4yUyBG37qk8y/s+rgjFzUUN9y9z MMp4o0TRk0YE2DXnx5nJIN2Ba7kuguWA49zX5ioMnxs9nApYQA7+C3CPi 1w5ronskYxjr8OVfrmGxjJagmx5CRhW3hjM+OuPXkQE7JLleGKCm99NCC 83zQzyo6cE6IlAs3QJJz8D8fKii0OHNe7x6OLkFhotkWwJvxnNhVD7Wt1 w==; X-CSE-ConnectionGUID: IAfxlPGXTYOtklZY8vzE9w== X-CSE-MsgGUID: jveXD5LkS/6WBL6Ln868VA== X-IronPort-AV: E=McAfee;i="6800,10657,11462"; a="55738857" X-IronPort-AV: E=Sophos;i="6.16,231,1744095600"; d="scan'208";a="55738857" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2025 09:09:39 -0700 X-CSE-ConnectionGUID: UCXwr6pLR36J3S2hwxKKIQ== X-CSE-MsgGUID: 4B6LOa0JSlKVNLtMNubofQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,231,1744095600"; d="scan'208";a="148468564" Received: from newjersey.igk.intel.com ([10.102.20.203]) by orviesa008.jf.intel.com with ESMTP; 12 Jun 2025 09:09:35 -0700 From: Alexander Lobakin To: intel-wired-lan@lists.osuosl.org Cc: Alexander Lobakin , Michal Kubiak , Maciej Fijalkowski , Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Simon Horman , nex.sw.ncis.osdt.itp.upstreaming@intel.com, bpf@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH iwl-next v2 03/17] libeth: support native XDP and register memory model Date: Thu, 12 Jun 2025 18:02:20 +0200 Message-ID: <20250612160234.68682-4-aleksander.lobakin@intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250612160234.68682-1-aleksander.lobakin@intel.com> References: <20250612160234.68682-1-aleksander.lobakin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expand libeth's Page Pool functionality by adding native XDP support. This means picking the appropriate headroom and DMA direction. Also, register all the created &page_pools as XDP memory models. A driver then can call xdp_rxq_info_attach_page_pool() when registering its RxQ info. Signed-off-by: Alexander Lobakin --- include/net/libeth/rx.h | 6 +++++- drivers/net/ethernet/intel/libeth/rx.c | 20 +++++++++++++++----- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/include/net/libeth/rx.h b/include/net/libeth/rx.h index 7d5dc58984b1..5d991404845e 100644 --- a/include/net/libeth/rx.h +++ b/include/net/libeth/rx.h @@ -13,8 +13,10 @@ =20 /* Space reserved in front of each frame */ #define LIBETH_SKB_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) +#define LIBETH_XDP_HEADROOM (ALIGN(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ + NET_IP_ALIGN) /* Maximum headroom for worst-case calculations */ -#define LIBETH_MAX_HEADROOM LIBETH_SKB_HEADROOM +#define LIBETH_MAX_HEADROOM LIBETH_XDP_HEADROOM /* Link layer / L2 overhead: Ethernet, 2 VLAN tags (C + S), FCS */ #define LIBETH_RX_LL_LEN (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN) /* Maximum supported L2-L4 header length */ @@ -66,6 +68,7 @@ enum libeth_fqe_type { * @count: number of descriptors/buffers the queue has * @type: type of the buffers this queue has * @hsplit: flag whether header split is enabled + * @xdp: flag indicating whether XDP is enabled * @buf_len: HW-writeable length per each buffer * @nid: ID of the closest NUMA node with memory */ @@ -81,6 +84,7 @@ struct libeth_fq { /* Cold fields */ enum libeth_fqe_type type:2; bool hsplit:1; + bool xdp:1; =20 u32 buf_len; int nid; diff --git a/drivers/net/ethernet/intel/libeth/rx.c b/drivers/net/ethernet/= intel/libeth/rx.c index 2afa6e33f160..62521a1f4ec9 100644 --- a/drivers/net/ethernet/intel/libeth/rx.c +++ b/drivers/net/ethernet/intel/libeth/rx.c @@ -72,7 +72,7 @@ static u32 libeth_rx_hw_len_truesize(const struct page_po= ol_params *pp, static bool libeth_rx_page_pool_params(struct libeth_fq *fq, struct page_pool_params *pp) { - pp->offset =3D LIBETH_SKB_HEADROOM; + pp->offset =3D fq->xdp ? LIBETH_XDP_HEADROOM : LIBETH_SKB_HEADROOM; /* HW-writeable / syncable length per one page */ pp->max_len =3D LIBETH_RX_PAGE_LEN(pp->offset); =20 @@ -159,11 +159,12 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct = napi_struct *napi) .dev =3D napi->dev->dev.parent, .netdev =3D napi->dev, .napi =3D napi, - .dma_dir =3D DMA_FROM_DEVICE, }; struct libeth_fqe *fqes; struct page_pool *pool; - bool ret; + int ret; + + pp.dma_dir =3D fq->xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; =20 if (!fq->hsplit) ret =3D libeth_rx_page_pool_params(fq, &pp); @@ -177,18 +178,26 @@ int libeth_rx_fq_create(struct libeth_fq *fq, struct = napi_struct *napi) return PTR_ERR(pool); =20 fqes =3D kvcalloc_node(fq->count, sizeof(*fqes), GFP_KERNEL, fq->nid); - if (!fqes) + if (!fqes) { + ret =3D -ENOMEM; goto err_buf; + } + + ret =3D xdp_reg_page_pool(pool); + if (ret) + goto err_mem; =20 fq->fqes =3D fqes; fq->pp =3D pool; =20 return 0; =20 +err_mem: + kvfree(fqes); err_buf: page_pool_destroy(pool); =20 - return -ENOMEM; + return ret; } EXPORT_SYMBOL_GPL(libeth_rx_fq_create); =20 @@ -198,6 +207,7 @@ EXPORT_SYMBOL_GPL(libeth_rx_fq_create); */ void libeth_rx_fq_destroy(struct libeth_fq *fq) { + xdp_unreg_page_pool(fq->pp); kvfree(fq->fqes); page_pool_destroy(fq->pp); } --=20 2.49.0