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Thu, 12 Jun 2025 08:47:16 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , "Jesper Dangaard Brouer" , Ilias Apalodimas , Richard Cochran , Alexei Starovoitov , Daniel Borkmann , John Fastabend , , , , , Dragos Tatulea , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v5 04/12] net/mlx5e: SHAMPO: Reorganize mlx5_rq_shampo_alloc Date: Thu, 12 Jun 2025 18:46:40 +0300 Message-ID: <20250612154648.1161201-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612154648.1161201-1-mbloch@nvidia.com> References: <20250612154648.1161201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F64:EE_|DM6PR12MB4252:EE_ X-MS-Office365-Filtering-Correlation-Id: d8ba1ffa-15f4-4abd-cc77-08dda9c876d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?sKy0kdpaR1zAZEWO65tkbLjZbAutDjJOKQAlznjU9b43WrJmRUJp3j5bfNJt?= =?us-ascii?Q?sGuEDFI2EhSuEc7Yx/Wfpj/wae2H0nmG2t/yX3+ETVkD6wy3Fa+CHcIWXTI6?= =?us-ascii?Q?d1AI3TFNsXy6k1HIvUNFTdPv5TTTs8hJu560DCcllGA49wCbZjVmwEtCXkp9?= =?us-ascii?Q?yl635oC6364h2Lk2/tZOrhgcuBR28MjO8K0BdgAdH5e5tOiE9R9c3ZYex0nL?= =?us-ascii?Q?ExC1JImU55ITKnohe9xsOZ7BqdDTXvh88HEbM/lgt9VsifEavyFgw+lv4Znt?= =?us-ascii?Q?JIGQbS3Z6pndzvGOPaK61cvWz0iuRuvATkkoetCnVOFdS4q2e24ENTQLSUR6?= =?us-ascii?Q?RufWTAjN0c4VKD7G4fN6Aeql8vlY5K21ZIigWg37Zc8nZW1xnOtayVmq1z3j?= =?us-ascii?Q?sgWZV1tdeegOBMfqeb0Dxxm7b86W4KwIMd8pVaLuSdhg83bpoVYfarbnpLsq?= =?us-ascii?Q?v1+rXGpokAa1Zq5x1PcyJpBof42Oa16NtErA8MMzq0OwU1game51NMRXsDh2?= =?us-ascii?Q?W0HiEG3BSLe73gC9OCH+XTBFmKU15E/0jpxwe5DdbQzRp2YSgy9K/b3D+KL+?= =?us-ascii?Q?Fz//vwzCZ8HswmgYVc2GenrHJEKSzMi30I6b62ZVtfMDVaLBGLWeT1GmJYe0?= =?us-ascii?Q?3NtWV3ds7jePEOp+vnf4yqwqLEXQsx0C7DrSq/2uYXlKuvretvRTvf93I+z9?= =?us-ascii?Q?JecT4gmX5rpMYh/J76f1ZRjO4Hb0E8SM++GHSeVtf1lSmSPaGNIIpOW1qcZT?= =?us-ascii?Q?G9Y8+eb0mKN0Xb/38RNJPZjwClIEF81oNhlFbn2+XUIZJB/3UyU1ydXUPtQV?= =?us-ascii?Q?rrRmlPRPrDEUhznkpvgMsz9UROccenoQzR1+ylI70gcaBQL+u0vGDhW5z7xY?= =?us-ascii?Q?wY37olYCVC8DMsLEBFERsct68UHuoLv5+3j1WPrMuLL/ym2Nnq33YBrHf5EX?= =?us-ascii?Q?edRVoErxB6I1BgOOpyTX20vA6yIzBZHh/yaxo1u0Uq9PSEINVn+gGisotwBf?= =?us-ascii?Q?aklMVIateQIvDUZQkF3G6Mav2bp4+cH155c9JZmzwFP8txxQTWvnRksFXgox?= =?us-ascii?Q?WLVCIdpz6PZE3V8BDUzq4Q+uCW2Gob++vWEhS1Kc27/BpjZ0gXJe1lr02xeY?= =?us-ascii?Q?Et3hlPjIPULlQpFU+zkCt0Y9GTeI8TPrnTeUSFDxU0K1iBzKr0xPH58f3Kaw?= =?us-ascii?Q?p6fMuGxZTC/5DwPp+w8kN2M/6GUlcIcae87n9PZq41oyvSto/4F4AWPxGnb9?= =?us-ascii?Q?ztNq5hL+BImvhNWQprzvPkH8pw4QB92vWOZrfrDdIT0w/ozAFCt9O5qhfBiH?= =?us-ascii?Q?Rm5HU9f5WvFIpahxW7pyxL0oKix7bbL+Ep5t/EzvgdHMbAYh38f1/M0Twtm6?= =?us-ascii?Q?q0J63r9/UDr0XkJkbEYHzSbHLv+E6Owp6skkyojU0ADJrHnP7WdzQ0HfPGDe?= =?us-ascii?Q?EJz08C8GmQw7nFKf3OxECo//1zMCIADx/kX83t/VeRLhUFc2HEJByh/CS5bm?= =?us-ascii?Q?pFoov+1G7RMv7/z70LCrX/r1v1PzOJc+7kPo?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2025 15:47:40.7351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8ba1ffa-15f4-4abd-cc77-08dda9c876d7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4252 Content-Type: text/plain; charset="utf-8" From: Saeed Mahameed Drop redundant SHAMPO structure alloc/free functions. Gather together function calls pertaining to header split info, pass header per WQE (hd_per_wqe) as parameter to those function to avoid use before initialization future mistakes. Allocate HW GRO related info outside of the header related info scope. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 - .../net/ethernet/mellanox/mlx5/core/en_main.c | 135 +++++++++--------- 2 files changed, 66 insertions(+), 70 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 5b0d03b3efe8..211ea429ea89 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -638,7 +638,6 @@ struct mlx5e_shampo_hd { struct mlx5e_frag_page *pages; u32 hd_per_wq; u16 hd_per_wqe; - u16 pages_per_wq; unsigned long *bitmap; u16 pi; u16 ci; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index ea822c69d137..3d11c9f87171 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -331,47 +331,6 @@ static inline void mlx5e_build_umr_wqe(struct mlx5e_rq= *rq, ucseg->mkey_mask =3D cpu_to_be64(MLX5_MKEY_MASK_FREE); } =20 -static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) -{ - rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), - GFP_KERNEL, node); - if (!rq->mpwqe.shampo) - return -ENOMEM; - return 0; -} - -static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) -{ - kvfree(rq->mpwqe.shampo); -} - -static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) -{ - struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; - - shampo->bitmap =3D bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, - node); - shampo->pages =3D kvzalloc_node(array_size(shampo->hd_per_wq, - sizeof(*shampo->pages)), - GFP_KERNEL, node); - if (!shampo->bitmap || !shampo->pages) - goto err_nomem; - - return 0; - -err_nomem: - bitmap_free(shampo->bitmap); - kvfree(shampo->pages); - - return -ENOMEM; -} - -static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) -{ - bitmap_free(rq->mpwqe.shampo->bitmap); - kvfree(rq->mpwqe.shampo->pages); -} - static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) { int wq_sz =3D mlx5_wq_ll_get_size(&rq->mpwqe.wq); @@ -584,19 +543,18 @@ static int mlx5e_create_rq_umr_mkey(struct mlx5_core_= dev *mdev, struct mlx5e_rq } =20 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, - struct mlx5e_rq *rq) + u16 hd_per_wq, u32 *umr_mkey) { u32 max_ksm_size =3D BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); =20 - if (max_ksm_size < rq->mpwqe.shampo->hd_per_wq) { + if (max_ksm_size < hd_per_wq) { mlx5_core_err(mdev, "max ksm list size 0x%x is smaller than shampo heade= r buffer list size 0x%x\n", - max_ksm_size, rq->mpwqe.shampo->hd_per_wq); + max_ksm_size, hd_per_wq); return -EINVAL; } - - return mlx5e_create_umr_ksm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, + return mlx5e_create_umr_ksm_mkey(mdev, hd_per_wq, MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE, - &rq->mpwqe.shampo->mkey); + umr_mkey); } =20 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) @@ -758,6 +716,35 @@ static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, = struct mlx5e_params *param xdp_frag_size); } =20 +static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, u16 hd_per_w= q, + int node) +{ + struct mlx5e_shampo_hd *shampo =3D rq->mpwqe.shampo; + + shampo->hd_per_wq =3D hd_per_wq; + + shampo->bitmap =3D bitmap_zalloc_node(hd_per_wq, GFP_KERNEL, node); + shampo->pages =3D kvzalloc_node(array_size(hd_per_wq, + sizeof(*shampo->pages)), + GFP_KERNEL, node); + if (!shampo->bitmap || !shampo->pages) + goto err_nomem; + + return 0; + +err_nomem: + kvfree(shampo->pages); + bitmap_free(shampo->bitmap); + + return -ENOMEM; +} + +static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) +{ + kvfree(rq->mpwqe.shampo->pages); + bitmap_free(rq->mpwqe.shampo->bitmap); +} + static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rqp, @@ -765,42 +752,52 @@ static int mlx5_rq_shampo_alloc(struct mlx5_core_dev = *mdev, u32 *pool_size, int node) { + void *wqc =3D MLX5_ADDR_OF(rqc, rqp->rqc, wq); + u16 hd_per_wq; + int wq_size; int err; =20 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) return 0; - err =3D mlx5e_rq_shampo_hd_alloc(rq, node); - if (err) - goto out; - rq->mpwqe.shampo->hd_per_wq =3D - mlx5e_shampo_hd_per_wq(mdev, params, rqp); - err =3D mlx5e_create_rq_hd_umr_mkey(mdev, rq); + + rq->mpwqe.shampo =3D kvzalloc_node(sizeof(*rq->mpwqe.shampo), + GFP_KERNEL, node); + if (!rq->mpwqe.shampo) + return -ENOMEM; + + /* split headers data structures */ + hd_per_wq =3D mlx5e_shampo_hd_per_wq(mdev, params, rqp); + err =3D mlx5e_rq_shampo_hd_info_alloc(rq, hd_per_wq, node); if (err) - goto err_shampo_hd; - err =3D mlx5e_rq_shampo_hd_info_alloc(rq, node); + goto err_shampo_hd_info_alloc; + + err =3D mlx5e_create_rq_hd_umr_mkey(mdev, hd_per_wq, + &rq->mpwqe.shampo->mkey); if (err) - goto err_shampo_info; + goto err_umr_mkey; + + rq->mpwqe.shampo->key =3D cpu_to_be32(rq->mpwqe.shampo->mkey); + rq->mpwqe.shampo->hd_per_wqe =3D + mlx5e_shampo_hd_per_wqe(mdev, params, rqp); + wq_size =3D BIT(MLX5_GET(wq, wqc, log_wq_sz)); + *pool_size +=3D (rq->mpwqe.shampo->hd_per_wqe * wq_size) / + MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; + + /* gro only data structures */ rq->hw_gro_data =3D kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, n= ode); if (!rq->hw_gro_data) { err =3D -ENOMEM; goto err_hw_gro_data; } - rq->mpwqe.shampo->key =3D - cpu_to_be32(rq->mpwqe.shampo->mkey); - rq->mpwqe.shampo->hd_per_wqe =3D - mlx5e_shampo_hd_per_wqe(mdev, params, rqp); - rq->mpwqe.shampo->pages_per_wq =3D - rq->mpwqe.shampo->hd_per_wq / MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; - *pool_size +=3D rq->mpwqe.shampo->pages_per_wq; + return 0; =20 err_hw_gro_data: - mlx5e_rq_shampo_hd_info_free(rq); -err_shampo_info: mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); -err_shampo_hd: - mlx5e_rq_shampo_hd_free(rq); -out: +err_umr_mkey: + mlx5e_rq_shampo_hd_info_free(rq); +err_shampo_hd_info_alloc: + kvfree(rq->mpwqe.shampo); return err; } =20 @@ -812,7 +809,7 @@ static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) kvfree(rq->hw_gro_data); mlx5e_rq_shampo_hd_info_free(rq); mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); - mlx5e_rq_shampo_hd_free(rq); + kvfree(rq->mpwqe.shampo); } =20 static int mlx5e_alloc_rq(struct mlx5e_params *params, --=20 2.34.1