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([2a02:1210:8608:9200:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a561b653d5sm1982809f8f.86.2025.06.12.06.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 06:28:35 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Catalin Marinas , Will Deacon , Arnd Bergmann , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 2/6] arm64: dts: sophgo: Add initial SG2000 SoC device tree Date: Thu, 12 Jun 2025 15:28:10 +0200 Message-ID: <20250612132844.767216-3-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250612132844.767216-1-alexander.sverdlin@gmail.com> References: <20250612132844.767216-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). Reviewed-by: Inochi Amaoto Signed-off-by: Alexander Sverdlin --- arch/arm64/boot/dts/sophgo/sg2000.dtsi | 86 ++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/s= ophgo/sg2000.dtsi new file mode 100644 index 000000000000..51177dfe9ed2 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) + +#include +#include +#include + +/ { + compatible =3D "sophgo,sg2000"; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0>; + enable-method =3D "psci"; + i-cache-size =3D <32768>; + d-cache-size =3D <32768>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x20000>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x20000000>; /* 512MiB */ + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + cpu_on =3D <0xc4000003>; + cpu_off =3D <0x84000002>; + }; + + soc { + gic: interrupt-controller@1f01000 { + compatible =3D "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x01f01000 0x1000>, + <0x01f02000 0x2000>; + }; + + pinctrl: pinctrl@3001000 { + compatible =3D "sophgo,sg2000-pinctrl"; + reg =3D <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names =3D "sys", "rtc"; + }; + + clk: clock-controller@3002000 { + compatible =3D "sophgo,sg2000-clk"; + reg =3D <0x03002000 0x1000>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + always-on; + clock-frequency =3D <25000000>; + }; +}; --=20 2.49.0