From nobody Fri Oct 10 20:52:43 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C492309B2 for ; Thu, 12 Jun 2025 10:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724935; cv=none; b=TKx4KYpTWw6euf8vI0/Emq84KTnw3s/CODcWW9K0stbxNgBhNj0A/hWM/v3um9vW4YxW5w44TPEkdae9Dpwb/bPr+w3oG13FBl1cVrDQyT2TSi2HU6Qno+WJuEMivqq6Q9FCEKmKEPiT98II7cmgLxJ1PTez6u2IzBWrF18adII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724935; c=relaxed/simple; bh=dccEvE8z4YXo6tWQOzZnVtCqb27+4nTiKtzvpzK8h3o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jZMIA6Ssbiqf7BMYhATc+L1YpkCZnWEzIiYtkZSKDZpHV6ZpXsIoeD34+6J2Bs1EC00g98iQZnQ8ztaMVej7BNltt8a010fU9IPT2dihgs2chAhfh0p6ceoL4sW4v7Al7vG1lLqRZVcXo9OgSG8VEJ2b1xP4NAYPgh27/A3TWwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uPfNg-00069H-GV; Thu, 12 Jun 2025 12:42:00 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uPfNf-0036k0-0S; Thu, 12 Jun 2025 12:41:59 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1uPfNf-009UTm-0E; Thu, 12 Jun 2025 12:41:59 +0200 From: Oleksij Rempel To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: David Jander , Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v2 1/3] net: phy: dp83tg720: implement soft reset with asymmetric delay Date: Thu, 12 Jun 2025 12:41:55 +0200 Message-Id: <20250612104157.2262058-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250612104157.2262058-1-o.rempel@pengutronix.de> References: <20250612104157.2262058-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Add a .soft_reset callback for the DP83TG720 PHY that issues a hardware reset followed by an asymmetric post-reset delay. The delay differs based on the PHY's master/slave role to avoid synchronized reset deadlocks, which are known to occur when both link partners use identical reset intervals. The delay includes: - a fixed 1ms wait to satisfy MDC access timing per datasheet, and - an empirically chosen extra delay (97ms for master, 149ms for slave). Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- changes v2: - move by Sob to the end of commit message - add documentation references to the comment --- drivers/net/phy/dp83tg720.c | 81 ++++++++++++++++++++++++++++++++----- 1 file changed, 71 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index 7e76323409c4..a53ea6d6130b 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -12,6 +12,48 @@ =20 #include "open_alliance_helpers.h" =20 +/* + * DP83TG720 PHY Limitations and Workarounds + * + * The DP83TG720 1000BASE-T1 PHY has several limitations that require + * software-side mitigations. These workarounds are implemented throughout + * this driver. This section documents the known issues and their correspo= nding + * mitigation strategies. + * + * 1. Unreliable Link Detection and Synchronized Reset Deadlock + * ------------------------------------------------------------ + * After a link loss or during link establishment, the DP83TG720 PHY may f= ail + * to detect or report link status correctly. As of June 2025, no public + * errata sheet for the DP83TG720 PHY documents this behavior. + * The "DP83TC81x, DP83TG72x Software Implementation Guide" application no= te + * (SNLA404, available at https://www.ti.com/lit/an/snla404/snla404.pdf) + * recommends performing a soft restart if polling for a link fails to est= ablish + * a connection after 100ms. This procedure is adopted as the workaround f= or the + * observed link detection issue. + * + * However, in point-to-point setups where both link partners use the same + * driver (e.g. Linux on both sides), a synchronized reset pattern may eme= rge. + * This leads to a deadlock, where both PHYs reset at the same time and + * continuously miss each other during auto-negotiation. + * + * To address this, the reset procedure includes two components: + * + * - A **fixed minimum delay of 1ms** after a hardware reset. The datasheet + * "DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY with SGMII and RGM= II" + * specifies this as the "Post reset stabilization-time prior to MDC pre= amble + * for register access" (T6.2), ensuring the PHY is ready for MDIO + * operations. + * + * - An **additional asymmetric delay**, empirically chosen based on + * master/slave role. This reduces the risk of synchronized resets on bo= th + * link partners. Values are selected to avoid periodic overlap and ensu= re + * the link is re-established within a few cycles. + * + * The functions that implement this logic are: + * - dp83tg720_soft_reset() + * - dp83tg720_get_next_update_time() + */ + /* * DP83TG720S_POLL_ACTIVE_LINK - Polling interval in milliseconds when the= link * is active. @@ -19,6 +61,10 @@ * the link is down. * DP83TG720S_POLL_NO_LINK_MAX - Maximum polling interval in milliseconds = when * the link is down. + * DP83TG720S_RESET_DELAY_MS_MASTER - Delay after a reset before attempting + * to establish a link again for master phy. + * DP83TG720S_RESET_DELAY_MS_SLAVE - Delay after a reset before attempting + * to establish a link again for slave phy. * * These values are not documented or officially recommended by the vendor= but * were determined through empirical testing. They achieve a good balance = in @@ -28,6 +74,8 @@ #define DP83TG720S_POLL_ACTIVE_LINK 1000 #define DP83TG720S_POLL_NO_LINK_MIN 100 #define DP83TG720S_POLL_NO_LINK_MAX 1000 +#define DP83TG720S_RESET_DELAY_MS_MASTER 97 +#define DP83TG720S_RESET_DELAY_MS_SLAVE 149 =20 #define DP83TG720S_PHY_ID 0x2000a284 =20 @@ -201,6 +249,26 @@ static int dp83tg720_update_stats(struct phy_device *p= hydev) return 0; } =20 +static int dp83tg720_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret =3D phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET); + if (ret) + return ret; + + /* Include mandatory MDC-access delay (1ms) + extra asymmetric delay to + * avoid synchronized reset deadlock. See section 1 in the top-of-file + * comment block. + */ + if (phydev->master_slave_state =3D=3D MASTER_SLAVE_STATE_SLAVE) + msleep(DP83TG720S_RESET_DELAY_MS_SLAVE); + else + msleep(DP83TG720S_RESET_DELAY_MS_MASTER); + + return ret; +} + static void dp83tg720_get_link_stats(struct phy_device *phydev, struct ethtool_link_ext_stats *link_stats) { @@ -477,19 +545,11 @@ static int dp83tg720_config_init(struct phy_device *p= hydev) { int ret; =20 - /* Software Restart is not enough to recover from a link failure. - * Using Hardware Reset instead. - */ - ret =3D phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET); + /* Reset the PHY to recover from a link failure */ + ret =3D dp83tg720_soft_reset(phydev); if (ret) return ret; =20 - /* Wait until MDC can be used again. - * The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1 - * Automotive Ethernet PHY with SGMII and RGMII" datasheet. - */ - usleep_range(1000, 2000); - if (phy_interface_is_rgmii(phydev)) { ret =3D dp83tg720_config_rgmii_delay(phydev); if (ret) @@ -582,6 +642,7 @@ static struct phy_driver dp83tg720_driver[] =3D { =20 .flags =3D PHY_POLL_CABLE_TEST, .probe =3D dp83tg720_probe, + .soft_reset =3D dp83tg720_soft_reset, .config_aneg =3D dp83tg720_config_aneg, .read_status =3D dp83tg720_read_status, .get_features =3D genphy_c45_pma_read_ext_abilities, --=20 2.39.5 From nobody Fri Oct 10 20:52:43 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1A12233D9E for ; Thu, 12 Jun 2025 10:42:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724936; cv=none; b=uZNReSNXaxHwKrQPqTlqzyJRcY+k/gGWStdU/S2mzX6ujDcnS3gF4gzShLldqrYRWRXpjbg2q1Wk8aX3n8oSA+htBc79JqofcXdp5KpE4m1nq5WNpdeuPRwL2dgex2Uj67mxKNjfAfd8KtizSqHyyqbnkAAf57E8S3RGMyQlRsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724936; c=relaxed/simple; bh=qakqnYbp0Vf8pUMDYk4oYr8IE4ZL3eLBv+g1sFJb9YA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=akUmDYVVIuSGmGV7gFkixHT062RDTOVoWA0x28+MW8UV28sNLfRidSA0aENe72ybFakKb57Erm5JxtiMTb6SpKxfbGNCwwkLRwm0p324JrTiBNlE55uajxSLxL/Z2ftLexXwyZa38Wn7BO/DTUEEKpyDTZVez2v/aUAbM7xYzBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uPfNg-00069I-GW; Thu, 12 Jun 2025 12:42:00 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uPfNf-0036k1-0U; Thu, 12 Jun 2025 12:41:59 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1uPfNf-009UTw-0H; Thu, 12 Jun 2025 12:41:59 +0200 From: Oleksij Rempel To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: David Jander , Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v2 2/3] net: phy: dp83tg720: remove redundant 600ms post-reset delay Date: Thu, 12 Jun 2025 12:41:56 +0200 Message-Id: <20250612104157.2262058-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250612104157.2262058-1-o.rempel@pengutronix.de> References: <20250612104157.2262058-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Now that dp83tg720_soft_reset() introduces role-specific delays to avoid reset synchronization deadlocks, the fixed 600ms post-reset delay in dp83tg720_read_status() is no longer needed. The new logic provides both the required MDC timing and link stabilization, making the old empirical delay redundant and unnecessarily long. Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- changes v2: - move by Sob to the end of commit message --- drivers/net/phy/dp83tg720.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index a53ea6d6130b..92597d12ecb9 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -450,21 +450,11 @@ static int dp83tg720_read_status(struct phy_device *p= hydev) /* According to the "DP83TC81x, DP83TG72x Software * Implementation Guide", the PHY needs to be reset after a * link loss or if no link is created after at least 100ms. - * - * Currently we are polling with the PHY_STATE_TIME (1000ms) - * interval, which is still enough for not automotive use cases. */ ret =3D phy_init_hw(phydev); if (ret) return ret; =20 - /* Sleep 600ms for PHY stabilization post-reset. - * Empirically chosen value (not documented). - * Helps reduce reset bounces with link partners having similar - * issues. - */ - msleep(600); - /* After HW reset we need to restore master/slave configuration. * genphy_c45_pma_baset1_read_master_slave() call will be done * by the dp83tg720_config_aneg() function. --=20 2.39.5 From nobody Fri Oct 10 20:52:43 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E87631F92E for ; Thu, 12 Jun 2025 10:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724936; cv=none; b=Y1gJL8OsiponrtCbf8nzKS4/JIQEHpthh83uEY8SWQL4vevemWlF7lUmZtkLHmJDGqzDrh1GPFX42KywEW7CANoohltrhK5sliX7ZaSmHqyJejycoACtXPnV8VRDjr7N6hXEUFJO73/wBSzI3pSY3BkgTiOzM91NiH2KWhULt1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749724936; c=relaxed/simple; bh=ouu2cHZCiDwpO+QTY/I1XSm6jEuv/+YIdngIZFjwsBk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UuyU5vKqyD1ze2ITq0UEg3L7UIsDb51T38tX5xdu77HYanXT9fvIWitebGUN4vTgopo7ScbnWNzjHjeDtP+BZJZFuVZvG9JXyVMHQ6FTcI704+dQzOpmev1aD6roSp0p85fhoJOpgiL64QjyZTm8g8NCbi9DkZGTiuTSzgVh9yo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uPfNg-00069J-GV; Thu, 12 Jun 2025 12:42:00 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uPfNf-0036k2-0Z; Thu, 12 Jun 2025 12:41:59 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1uPfNf-009UU6-0L; Thu, 12 Jun 2025 12:41:59 +0200 From: Oleksij Rempel To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: David Jander , Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v2 3/3] net: phy: dp83tg720: switch to adaptive polling and remove random delays Date: Thu, 12 Jun 2025 12:41:57 +0200 Message-Id: <20250612104157.2262058-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250612104157.2262058-1-o.rempel@pengutronix.de> References: <20250612104157.2262058-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: David Jander Now that the PHY reset logic includes a role-specific asymmetric delay to avoid synchronized reset deadlocks, the previously used randomized polling intervals are no longer necessary. This patch removes the get_random_u32_below()-based logic and introduces an adaptive polling strategy: - Fast polling for a short time after link-down - Slow polling if the link remains down - Slower polling when the link is up This balances CPU usage and responsiveness while avoiding reset collisions. Additionally, the driver still relies on polling for all link state changes, as interrupt support is not implemented, and link-up events are not reliably signaled by the PHY. The polling parameters are now documented in the updated top-of-file comment. Co-developed-by: Oleksij Rempel Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- changes v2: - move by Sob to the end of commit message --- drivers/net/phy/dp83tg720.c | 94 ++++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 39 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index 92597d12ecb9..391c1d868808 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -52,15 +52,37 @@ * The functions that implement this logic are: * - dp83tg720_soft_reset() * - dp83tg720_get_next_update_time() + * + * 2. Polling-Based Link Detection and IRQ Support + * ----------------------------------------------- + * Due to the PHY-specific limitation described in section 1, link-up even= ts + * cannot be reliably detected via interrupts on the DP83TG720. Therefore, + * polling is required to detect transitions from link-down to link-up. + * + * While link-down events *can* be detected via IRQs on this PHY, this dri= ver + * currently does **not** implement interrupt support. As a result, all li= nk + * state changes must be detected using polling. + * + * Polling behavior: + * - When the link is up: slow polling (e.g. 1s). + * - When the link just went down: fast polling for a short time. + * - When the link stays down: fallback to slow polling. + * + * This design balances responsiveness and CPU usage. It sacrifices fast l= ink-up + * times in cases where the link is expected to remain down for extended p= eriods, + * assuming that such systems do not require immediate reactivity. */ =20 /* * DP83TG720S_POLL_ACTIVE_LINK - Polling interval in milliseconds when the= link * is active. - * DP83TG720S_POLL_NO_LINK_MIN - Minimum polling interval in milliseconds = when - * the link is down. - * DP83TG720S_POLL_NO_LINK_MAX - Maximum polling interval in milliseconds = when - * the link is down. + * DP83TG720S_POLL_NO_LINK - Polling interval in milliseconds when the + * link is down. + * DP83TG720S_FAST_POLL_DURATION_MS - Timeout in milliseconds for no-link + * polling after which polling interval is + * increased. + * DP83TG720S_POLL_SLOW - Slow polling interval when there is no + * link for a prolongued period. * DP83TG720S_RESET_DELAY_MS_MASTER - Delay after a reset before attempting * to establish a link again for master phy. * DP83TG720S_RESET_DELAY_MS_SLAVE - Delay after a reset before attempting @@ -71,9 +93,10 @@ * minimizing the number of reset retries while ensuring reliable link rec= overy * within a reasonable timeframe. */ -#define DP83TG720S_POLL_ACTIVE_LINK 1000 -#define DP83TG720S_POLL_NO_LINK_MIN 100 -#define DP83TG720S_POLL_NO_LINK_MAX 1000 +#define DP83TG720S_POLL_ACTIVE_LINK 421 +#define DP83TG720S_POLL_NO_LINK 149 +#define DP83TG720S_FAST_POLL_DURATION_MS 6000 +#define DP83TG720S_POLL_SLOW 1117 #define DP83TG720S_RESET_DELAY_MS_MASTER 97 #define DP83TG720S_RESET_DELAY_MS_SLAVE 149 =20 @@ -172,6 +195,7 @@ struct dp83tg720_stats { =20 struct dp83tg720_priv { struct dp83tg720_stats stats; + unsigned long last_link_down_jiffies; }; =20 /** @@ -575,50 +599,42 @@ static int dp83tg720_probe(struct phy_device *phydev) } =20 /** - * dp83tg720_get_next_update_time - Determine the next update time for PHY - * state + * dp83tg720_get_next_update_time - Return next polling interval for PHY s= tate * @phydev: Pointer to the phy_device structure * - * This function addresses a limitation of the DP83TG720 PHY, which cannot - * reliably detect or report a stable link state. To recover from such - * scenarios, the PHY must be periodically reset when the link is down. Ho= wever, - * if the link partner also runs Linux with the same driver, synchronized = reset - * intervals can lead to a deadlock where the link never establishes due to - * simultaneous resets on both sides. - * - * To avoid this, the function implements randomized polling intervals whe= n the - * link is down. It ensures that reset intervals are desynchronized by - * introducing a random delay between a configured minimum and maximum ran= ge. - * When the link is up, a fixed polling interval is used to minimize overh= ead. - * - * This mechanism guarantees that the link will reestablish within 10 seco= nds - * in the worst-case scenario. + * Implements adaptive polling interval logic depending on link state and + * downtime duration. See the "2. Polling-Based Link Detection and IRQ Sup= port" + * section at the top of this file for details. * - * Return: Time (in jiffies) until the next update event for the PHY state - * machine. + * Return: Time (in jiffies) until the next poll */ static unsigned int dp83tg720_get_next_update_time(struct phy_device *phyd= ev) { + struct dp83tg720_priv *priv =3D phydev->priv; unsigned int next_time_jiffies; =20 if (phydev->link) { - /* When the link is up, use a fixed 1000ms interval - * (in jiffies) - */ + priv->last_link_down_jiffies =3D 0; + + /* When the link is up, use a slower interval (in jiffies) */ next_time_jiffies =3D msecs_to_jiffies(DP83TG720S_POLL_ACTIVE_LINK); } else { - unsigned int min_jiffies, max_jiffies, rand_jiffies; - - /* When the link is down, randomize interval between min/max - * (in jiffies) - */ - min_jiffies =3D msecs_to_jiffies(DP83TG720S_POLL_NO_LINK_MIN); - max_jiffies =3D msecs_to_jiffies(DP83TG720S_POLL_NO_LINK_MAX); - - rand_jiffies =3D min_jiffies + - get_random_u32_below(max_jiffies - min_jiffies + 1); - next_time_jiffies =3D rand_jiffies; + unsigned long now =3D jiffies; + + if (!priv->last_link_down_jiffies) + priv->last_link_down_jiffies =3D now; + + if (time_before(now, priv->last_link_down_jiffies + + msecs_to_jiffies(DP83TG720S_FAST_POLL_DURATION_MS))) { + /* Link recently went down: fast polling */ + next_time_jiffies =3D + msecs_to_jiffies(DP83TG720S_POLL_NO_LINK); + } else { + /* Link has been down for a while: slow polling */ + next_time_jiffies =3D + msecs_to_jiffies(DP83TG720S_POLL_SLOW); + } } =20 /* Ensure the polling time is at least one jiffy */ --=20 2.39.5