From nobody Sat Oct 11 00:25:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A29231A51; Thu, 12 Jun 2025 10:09:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722986; cv=none; b=cIdGmSRftSxyxB//aDsAzAdcTffwcpHgC9wt9yAjpGIa5C5Z06pRZVo4mQuCVmNVMKSwyE8v4+5KAqAvC/bZRVvY9EmD724FCs1wkU/hGTo9qWcKoDPR46B5DEIr2vIeirGfeTgKROjDSXz5pZZOnrZb7EPBiFfO8SsaG1b1B20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722986; c=relaxed/simple; bh=/mkYOGjEhJNL1kZ3i9RqYk9WHfeEYu7oyXYZCYnaFx8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O/573p4mW2kBXme96Uv6dlAy+WNe1ENuvsOJ6KNhim71yjmKD2PDhW/lyQSIJYnFdYr/7dMMZdgbxruBBmvrI8totkz2J7Q90G5CM6ffROQ4SO0P1KQQj67ioMqaAkOztSU8M901RfuwOnArTbT1b6KPanLrQZwNZWeL0AMqHEc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Jun 2025 18:09:33 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Jun 2025 18:09:33 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v0 1/5] dt-bindings: arm: aspeed: Add AST2700 board compatible Date: Thu, 12 Jun 2025 18:09:29 +0800 Message-ID: <20250612100933.3007673-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree compatible string for AST2700 based boards ("aspeed,ast2700-evb" and "aspeed,ast2700") to the Aspeed SoC board bindings. This allows proper schema validation and enables support for AST2700 platforms. Signed-off-by: Ryan Chen --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 01333ac111fb..660529c81af9 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -102,5 +102,10 @@ properties: - quanta,s6q-bmc - ufispace,ncplite-bmc - const: aspeed,ast2600 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 =20 additionalProperties: true --=20 2.34.1 From nobody Sat Oct 11 00:25:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10D55235C1E; Thu, 12 Jun 2025 10:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722988; cv=none; b=W9DGuRxbfpPayYuwZCcQf3cKQo28Igs9xLSciQE9jSVL+HkEPLMnXajz+VK4w8zf5MLJ6oKuVGeTt0uplpsuK/umA49a+F9qQEJRWwEat7yGbhXLCu99poqRBNSBOa4wlQa8HmpO+mXfzahFEJJ2xhEtSe9OrRnjYiuEr2PoPBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722988; c=relaxed/simple; bh=aiMrGNjS5p+tByzckIyLBX9YNXk9V/fcpjkN4FQ8CYw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uMhelTX/+/SBDgojcKdS4ecxxo5Mmanaod8S964tVgboG8W1XkQYYKArDbZN6AcWd/vqRt1Gzjh0E9AjncXBNretm73c5daG2zfbZ9t1IJIiV5HR93enJsJ6JYpjf1Q9Yi+xrWdRV3kwuW2UMkWxaQaqRI69ab9/g0RDj9q1fYo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Jun 2025 18:09:33 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Jun 2025 18:09:33 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v0 2/5] arm64: Kconfig: Add Aspeed SoC family (ast2700) platform option Date: Thu, 12 Jun 2025 18:09:30 +0800 Message-ID: <20250612100933.3007673-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ARCH_ASPEED platform option to arm64 Kconfig, enabling support for Aspeed ast2700 and similar 7th generation Aspeed BMCs. Signed-off-by: Ryan Chen --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029aa4..03e6c168c87e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,12 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. =20 +config ARCH_ASPEED + bool "Aspeed SoC family" + help + Say yes if you intend to run on an Aspeed ast2700 or similar + seventh generation Aspeed BMCs. + menuconfig ARCH_BCM bool "Broadcom SoC Support" =20 --=20 2.34.1 From nobody Sat Oct 11 00:25:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ECF72397A4; Thu, 12 Jun 2025 10:09:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722991; cv=none; b=SAUhoiHa4qN6IeJ7+D+Dt1IeTCdqbBjQkTSfTarHVlEpNeuDWEy+EnmRKKc228hlStn2uG1I8yBQk5lywDmDW7Nwy3SSx9nl7eCgA9+9YhtV64ttMMM9Fh3PCI/EDR1Kpt11r4cN/MyE+eW+/30aVYPhZ2dHz1+sSQD0IxNivsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722991; c=relaxed/simple; bh=a+Z12Rpur5fOh4TBfnzexymTpZD4IqJnahSNwis/M7w=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BfNX2ilyCmkbMgLHnetoHJJkCDFzABtKTV5GJrb1/shpkkqqmz+RvWYABgkXGnGnn/3YNCDg8LA/LUBQyppOx5UBE9go8J4RvJ5by+0OCJW3K9ERDWLB4TkmDYw+OXori6ul8obQUP5/NqmL3jTT8I2+biFE9gRS2YLB4PhoS0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Jun 2025 18:09:33 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Jun 2025 18:09:33 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree Date: Thu, 12 Jun 2025 18:09:31 +0800 Message-ID: <20250612100933.3007673-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This add the initial device tree support for the ASPEED AST2700 SoC. - Add top-level compatible string "aspeed,ast2700" and set up address-cells/size-cells for 64-bit address space. - Describe a quad-core ARM Cortex-A35 CPU cluster with L2 cache, including cache properties and PSCI enable-method. - Add PMU and ARMv8 timer nodes with correct PPI interrupt wiring. - Model the dual-SoC architecture with two simple-bus nodes: soc0 (@0x10000000) and soc1 (@0x14000000). - Add syscon nodes for both SoCs (syscon0, syscon1) with clock/reset cell definitions and address mapping. - Add GICv3 interrupt controller node under soc0, with full register mapping and interrupt properties. - Hierarchical interrupt controller structure: - intc0 under soc0, with child intc0_11 node. - intc1 under soc1, with child intc1_0~intc1_5 nodes. - Add serial4 node under soc0, others serial node under soc1. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 380 ++++++++++++++++++++++ 1 file changed, 380 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dt= s/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..d197187bcf9f --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <1>; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x1>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x2>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + enable-method =3D "psci"; + reg =3D <0x0 0x3>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + }; + }; + + arm-pmu { + compatible =3D "arm,cortex-a35-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + soc0: soc@10000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x10000000 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + syscon0: syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg =3D <0x0 0x12c02000 0x1000>; + ranges =3D <0x0 0x0 0 0x12c02000 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + gic: interrupt-controller@12200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x12200000 0x10000>, /* GICD */ + <0 0x12280000 0x80000>, /* GICR */ + <0 0x40440000 0x1000>; /* GICC */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + interrupt-parent =3D <&gic>; + }; + + serial4: serial@12c1a000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x12c1a000 0x1000>; + clocks =3D <&syscon0 SCU0_CLK_GATE_UART4CLK>; + interrupts =3D ; + reg-shift =3D <2>; + status =3D "disabled"; + }; + }; + + soc1: soc@14000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0x14000000 0x10000000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + syscon1: syscon@14c02000 { + compatible =3D "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg =3D <0x0 0x14c02000 0x1000>; + ranges =3D <0x0 0x0 0x0 0x14c02000 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + serial12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended =3D + <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + }; +}; + +&soc0 { + intc0: interrupt-controller@12100000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x12100000 0x4000>; + ranges =3D <0x0 0x0 0x0 0x12100000 0x4000>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc0_11: interrupt-controller@1b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x1b00 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + ; + }; + }; +}; + +&soc1 { + intc1: interrupt-controller@14c18000 { + compatible =3D "simple-mfd"; + reg =3D <0 0x14c18000 0x400>; + ranges =3D <0x0 0x0 0x0 0x14c18000 0x400>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + intc1_0: interrupt-controller@100 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x100 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + intc1_1: interrupt-controller@110 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x110 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + intc1_2: interrupt-controller@120 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x120 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + intc1_3: interrupt-controller@130 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x130 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + intc1_4: interrupt-controller@140 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x140 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + intc1_5: interrupt-controller@150 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0x0 0x150 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D + <&intc0_11 5 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + serial0: serial@14c33000 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33000 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART0CLK>; + interrupts-extended =3D <&intc1_4 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_L= EVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial1: serial@14c33100 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33100 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART1CLK>; + interrupts-extended =3D <&intc1_4 8 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_L= EVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial2: serial@14c33200 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33200 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART2CLK>; + interrupts-extended =3D <&intc1_4 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_L= EVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial3: serial@14c33300 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33300 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART3CLK>; + interrupts-extended =3D <&intc1_4 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial5: serial@14c33400 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33400 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART5CLK>; + interrupts-extended =3D <&intc1_4 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial6: serial@14c33500 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33500 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART6CLK>; + interrupts-extended =3D <&intc1_4 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial7: serial@14c33600 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33600 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART7CLK>; + interrupts-extended =3D <&intc1_4 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial8: serial@14c33700 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33700 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART8CLK>; + interrupts-extended =3D <&intc1_4 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial9: serial@14c33800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33800 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART9CLK>; + interrupts-extended =3D <&intc1_4 15 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial10: serial@14c33900 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33900 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART10CLK>; + interrupts-extended =3D <&intc1_4 16 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial11: serial@14c33a00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33a00 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART11CLK>; + interrupts-extended =3D <&intc1_4 17 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial12: serial@14c33b00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33b00 0x100>; + clocks =3D <&syscon1 SCU1_CLK_GATE_UART12CLK>; + interrupts-extended =3D <&intc1_4 18 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + pinctrl-names =3D "default"; + }; + + serial13: serial@14c33c00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33c00 0x100>; + clocks =3D <&syscon1 SCU1_CLK_UART13>; + interrupts-extended =3D <&intc1_0 23 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + serial14: serial@14c33d00 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x14c33d00 0x100>; + clocks =3D <&syscon1 SCU1_CLK_UART14>; + interrupts-extended =3D <&intc1_1 23 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_= LEVEL_HIGH)>; + reg-shift =3D <2>; + status =3D "disabled"; + }; +}; + --=20 2.34.1 From nobody Sat Oct 11 00:25:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D99F23A58B; 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dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Jun 2025 18:09:34 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Jun 2025 18:09:34 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v0 4/5] arm64: dts: aspeed: Add AST2700 EVB device tree Date: Thu, 12 Jun 2025 18:09:32 +0800 Message-ID: <20250612100933.3007673-5-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add ast2700-evb.dts for the ASPEED AST2700 Evaluation Board. - Set board model and compatible strings: "aspeed,ast2700-evb", "aspeed,ast2700". - Reference the common AST2700 SoC device tree aspeed-g7.dtsi. - Define memory layout and reserved-memory regions for MCU firmware, ATF, and OP-TEE. - Add OP-TEE firmware node with SMC method. - Set up serial12 as the default console. Signed-off-by: Ryan Chen --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/Makefile | 4 ++ arch/arm64/boot/dts/aspeed/ast2700-evb.dts | 54 ++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/Makefile create mode 100644 arch/arm64/boot/dts/aspeed/ast2700-evb.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..d9c3e58b9ca5 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -35,3 +35,4 @@ subdir-y +=3D tesla subdir-y +=3D ti subdir-y +=3D toshiba subdir-y +=3D xilinx +subdir-y +=3D aspeed diff --git a/arch/arm64/boot/dts/aspeed/Makefile b/arch/arm64/boot/dts/aspe= ed/Makefile new file mode 100644 index 000000000000..ffe7e15017cc --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ASPEED) +=3D \ + ast2700-evb.dtb diff --git a/arch/arm64/boot/dts/aspeed/ast2700-evb.dts b/arch/arm64/boot/d= ts/aspeed/ast2700-evb.dts new file mode 100644 index 000000000000..ecd4b55931e7 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/ast2700-evb.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g7.dtsi" + +/ { + model =3D "ASPEED ast2700 Development Board"; + compatible =3D "aspeed,ast2700-evb", "aspeed,ast2700"; + + aliases { + serial12 =3D &serial12; + }; + + chosen { + stdout-path =3D &serial12; + }; + + firmware { + optee: optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + mcu_fw: mcu-firmware@42fe00000 { + reg =3D <0x4 0x2fe00000 0x200000>; + no-map; + }; + + atf: trusted-firmware-a@430000000 { + reg =3D <0x4 0x30000000 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg =3D <0x4 0x30080000 0x1000000>; + no-map; + }; + }; +}; + +&serial12 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Sat Oct 11 00:25:24 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3515223A566; Thu, 12 Jun 2025 10:09:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722994; cv=none; b=iV3z//Mrg1K96sptTbJ0uKJqEUNZVO35K1DDFd0vo56IW0ucyIC2q2KBRh7UwedMv3yYKlguaCyUlQPm8F3O56D8lYcJvhXSdp+DhaRjExsDwTy8C5h8Yse3lT2wccglEtVusljhNdvoQIQfOcfz/9Ui3aVy1Rp8LfY1qPNyyGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749722994; c=relaxed/simple; bh=fWTGdhzdZ6vdgiwY8u2G5FjOPqNxbmZQtTEseyvkd8s=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gS2P1aPmHbQsu+u2EkPMh1NjpGD2o/qWfc6aQ2Yv6C3W2YLLRppXZwWl6eBP6AKuNB3vS1dvEyf5xf/paz+N5URE+5LHgEjyTHWLdNxGyc3t+t5R/ggTwe6AvmFN5Ijo+8tgFImVrjogScmmPu25lu/c5FaT5GXMzoYA+8o7hfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 12 Jun 2025 18:09:34 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 12 Jun 2025 18:09:34 +0800 From: Ryan Chen To: ryan_chen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Catalin Marinas , Will Deacon , Arnd Bergmann , Bjorn Andersson , Geert Uytterhoeven , Nishanth Menon , , Taniya Das , Lad Prabhakar , Kuninori Morimoto , Eric Biggers , , , , , , Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , , , , Subject: [PATCH v0 5/5] arm64: configs: Update defconfig for AST2700 platform support Date: Thu, 12 Jun 2025 18:09:33 +0800 Message-ID: <20250612100933.3007673-6-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> References: <20250612100933.3007673-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Enable options for ASPEED AST2700 SoC. Signed-off-by: Ryan Chen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a9..c9d90aa07e59 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -38,6 +38,7 @@ CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy +CONFIG_ARCH_ASPEED=3Dy CONFIG_ARCH_BCM=3Dy CONFIG_ARCH_BCM2835=3Dy CONFIG_ARCH_BCM_IPROC=3Dy --=20 2.34.1