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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:28 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v4 01/10] dt-bindings: arm: fsl: support Engicam MicroGEA BMM board Date: Thu, 12 Jun 2025 11:07:46 +0200 Message-ID: <20250612090823.2519183-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA BMM board based on the Engicam MicroGEA SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index d3b5e6923e41..5feb62611e53 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -769,6 +769,13 @@ properties: - const: dh,imx6ull-dhcor-som - const: fsl,imx6ull =20 + - description: i.MX6ULL Engicam MicroGEA SoM based boards + items: + - enum: + - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFD2A220F50 for ; Thu, 12 Jun 2025 09:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719313; cv=none; b=gpDsDlPFQ4X1JBdmxcjMLueCtWqJdfG6z5VUrGz6mNmI8Z2oZ5X3iZDkdssk7Xq0Yd4FdYIhwjYyMcJRfIJeGOEh9Xff9P5SZhIEjt/6kGTs6NPY70AMQll/qrQmGl3hv4Z7N/cQB04VqEfLBK9YuqgJHdpgOvv1F98Z4yYnRkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719313; c=relaxed/simple; bh=33KJWBkI7rM8jT4VqOLvllhf3AJjAdnqppvUHNnIlHo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MNpGN4ndnrMw1HcPa/QcAdXbkgfvneCapkNrQoN2SlMIMnnowHaOLPH6RmYmHo6gnRx2VCIf5kJndmyACC+oQY63zNufngZ6EGPKi9ffnUaFHuZ6OOimLOe0cgjYQJCt0NVquFMNNAFQn/fyhNvQgMN0MYJewvqSOcUPZXrpdfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=BjKbST4f; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="BjKbST4f" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-adb2bb25105so125826766b.0 for ; Thu, 12 Jun 2025 02:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749719310; x=1750324110; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XOp2CZidLhOmD2AW6kGHp67OREEo6XfroyPiU2YyVaI=; b=BjKbST4f326d0u7S5flarvPBW62yJdxSx2/Y4sJe1xlLJrQAgo2SJ7tw46pxylhuk0 bNkH0kEjpQqgSp7H7JEim6GB3sCvJtzuFxijs7e947vqlUD/C1hsVLoYxQGHLYRrw1QT UgJNPgnF9GMWmPZ6WOSx7B6TA397ntLwKjUmo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749719310; x=1750324110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XOp2CZidLhOmD2AW6kGHp67OREEo6XfroyPiU2YyVaI=; b=uLhYoWjIFxpyWN9IkUZZklDZVzWkjVn0b1E+aBJJ/7baUi10L0Cefag0mRSpDmr6Ph B9ntM8PKDcRXn19Hhw7t0VrEDw5T6ea8W5kc+nAbn3X7dq1c4YHbOuQnXUeuJ0T6eQr9 1bUE0kVJJvFP5de5F9mfhl5qZkIF22y0iTF43968pbO3ir0s2QAH4Q9uEGbrTXN4gIHT 6+B6OxGAlnIiIOxaOV+RROZEJW9vuW5nVcYR9/Nu1CzTkr/SD8CoGfKlHmqASP4JQw9G C5Oe11TKsedvsRGeTyNREDJU/Z3uqxiGAM801tVEbXI+dlYOzCNVYSmxCeQfZ0gf071T 1wQg== X-Gm-Message-State: AOJu0Yw5X5LeaTHsnwW+oTxYjh3VckTIYhEipAg8TcvPkGFSE2QizPap zAgQ2zcqHJV+35BXMTNvArolSYnsHIohy6ws0QGPNHl5+ifxn4hVFc9c6itY5e2+J/ww9A7bYKm bJf/k X-Gm-Gg: ASbGncubx1hF0JdCFTr5KI92u1+EJDTXvq4lUlL/eOSCS6U9NFEG/EPLpqhph8zW2u0 K7immxXkM/0K9L/YpLebIxmNXDAj3IK7TSY9+pqn8DUX+bFfrh252cjqF/kegczMnwvHb0nuvn9 TGmCc++7S90Rr5GmQwk5o1RUd4A+1WWlpNDUoeH/EkGTapjVU2GC17p3jBZCG0BfE5+EfuPto+u SxIK7nZXePlrgaGg59pAvRyiaAeUJMK4WZTd+v5LIiqerOiekQjFig/XqADjeHIMQJnkv8ih5im QPQlY4omuUqdpZUDIvCscTFRDNRuTrqOwN3dUJGA1s10f3x/eE6slYh2CSJ4C7mswIF18xhRyHj 9trdVdsHN0j0z+clWTbBoIuy6tA== X-Google-Smtp-Source: AGHT+IGFdYyZwICEn5pUqccNAy05uHrtK7vypSlXvflXDY0Q2wzkFTnD0yY8JVc3QiFTMxGE2CiQwA== X-Received: by 2002:a17:907:9706:b0:ad2:2fa8:c0a7 with SMTP id a640c23a62f3a-adea25df1b4mr275919366b.21.1749719309960; Thu, 12 Jun 2025 02:08:29 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:29 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Frank Li , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 02/10] ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoM Date: Thu, 12 Jun 2025 11:07:47 +0200 Message-ID: <20250612090823.2519183-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v4: - Add Reviewed-by tag of Frank Li Changes in v3: - Drop an extra blank line from the iomuxc node. Changes in v2: - Change local-mac-address to 00 00 00 00 00 00. The actual value will be set by the bootloader. The previous one was assigned to Freescale Semiconductor. .../dts/nxp/imx/imx6ull-engicam-microgea.dtsi | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch= /arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi new file mode 100644 index 000000000000..43518bf07602 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + + #include "imx6ull.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull", "fsl,imx6ull"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x20000000>; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_phy_reset>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + local-mac-address =3D [00 00 00 00 00 00]; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <4000>; + reset-deassert-us =3D <4000>; + }; + }; +}; + +/* NAND */ +&gpmi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpmi_nand>; + nand-ecc-mode =3D "hw"; + nand-ecc-strength =3D <0>; + nand-ecc-step-size =3D <0>; + nand-on-flash-bbt; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins =3D < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_phy_reset: phy-resetgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61F4B22A1D4 for ; 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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:31 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Peng Fan , Frank Li , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 03/10] ARM: dts: imx6ul: support Engicam MicroGEA BMM board Date: Thu, 12 Jun 2025 11:07:48 +0200 Message-ID: <20250612090823.2519183-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA BMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan Reviewed-by: Frank Li --- Changes in v4: - Add Reviewed-by tag of Frank Li Changes in v3: - Rename sgtl5000 node to audio-codec. - Move the reg property of the audio-codec node right after the compatible property. - Drop an extra blank line from iomuxc and iomuxc_snvs nodes. Changes in v2: - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. - Add Reviewed-by tag of Peng Fan. arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-bmm.dts | 303 ++++++++++++++++++ 2 files changed, 304 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 8b3abe817e12..57f185198217 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -356,6 +356,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-pdk2.dtb \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ + imx6ull-engicam-microgea-bmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts new file mode 100644 index 000000000000..279d46c22cd7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-bmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-bmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + #sound-dai-cells =3D <0>; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&tsc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tsc>; + measure-delay-time =3D <0x9ffff>; + pre-charge-time =3D <0xfff>; + xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb2_vbus>; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x11008 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x000b0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x000b0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x000b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; 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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:32 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 04/10] ARM: imx_v6_v7_defconfig: cleanup with savedefconfig Date: Thu, 12 Jun 2025 11:07:49 +0200 Message-ID: <20250612090823.2519183-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generate imx_v6_v7_defconfig by doing: make imx_v6_v7_defconfig make savedefconfig cp defconfig arch/arm/configs/imx_v6_v7_defconfig No functional change. The goal here is to cleanup imx_v6_v7_defconfig file to make easier and cleaner the addition of new entries. Signed-off-by: Dario Binacchi --- Changes in v4: - Fix commit title. It was referring to a wrong configuration arch/arm/configs/imx_v6_v7_defconfig | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 062c1eb8dd60..d40ca9edd264 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_RELAY=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy CONFIG_PERF_EVENTS=3Dy +CONFIG_KEXEC=3Dy CONFIG_ARCH_MULTI_V6=3Dy CONFIG_ARCH_MXC=3Dy CONFIG_SOC_IMX31=3Dy @@ -32,7 +33,6 @@ CONFIG_ARM_PSCI=3Dy CONFIG_HIGHMEM=3Dy CONFIG_ARCH_FORCE_MAX_ORDER=3D13 CONFIG_CMDLINE=3D"noinitrd console=3Dttymxc0,115200" -CONFIG_KEXEC=3Dy CONFIG_CPU_FREQ=3Dy CONFIG_CPU_FREQ_STAT=3Dy CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=3Dy @@ -129,7 +129,6 @@ CONFIG_CS89x0_PLATFORM=3Dy CONFIG_QCA7000_SPI=3Dm # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=3Dy -CONFIG_SMC911X=3Dy CONFIG_SMSC911X=3Dy # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_MICREL_PHY=3Dy @@ -153,9 +152,7 @@ CONFIG_MWIFIEX_PCIE=3Dm CONFIG_WL12XX=3Dm CONFIG_WL18XX=3Dm CONFIG_WLCORE_SDIO=3Dm -# CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_INPUT_EVDEV=3Dy -CONFIG_INPUT_EVBUG=3Dm CONFIG_KEYBOARD_GPIO=3Dy CONFIG_KEYBOARD_SNVS_PWRKEY=3Dy CONFIG_KEYBOARD_IMX=3Dy @@ -190,9 +187,7 @@ CONFIG_SERIAL_IMX_CONSOLE=3Dy CONFIG_SERIAL_FSL_LPUART=3Dy CONFIG_SERIAL_FSL_LPUART_CONSOLE=3Dy CONFIG_SERIAL_DEV_BUS=3Dy -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=3Dy -CONFIG_I2C_MUX=3Dy CONFIG_I2C_MUX_GPIO=3Dy # CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_ALGOPCF=3Dm @@ -204,14 +199,9 @@ CONFIG_SPI_FSL_QUADSPI=3Dy CONFIG_SPI_GPIO=3Dy CONFIG_SPI_IMX=3Dy CONFIG_SPI_FSL_DSPI=3Dy -CONFIG_PINCTRL_IMX8MM=3Dy -CONFIG_PINCTRL_IMX8MN=3Dy -CONFIG_PINCTRL_IMX8MP=3Dy -CONFIG_PINCTRL_IMX8MQ=3Dy CONFIG_GPIO_SYSFS=3Dy CONFIG_GPIO_MXC=3Dy CONFIG_GPIO_SIOX=3Dm -CONFIG_GPIO_VF610=3Dy CONFIG_GPIO_MAX732X=3Dy CONFIG_GPIO_PCA953X=3Dy CONFIG_GPIO_PCA953X_IRQ=3Dy @@ -225,7 +215,6 @@ CONFIG_W1_SLAVE_THERM=3Dm CONFIG_POWER_RESET=3Dy CONFIG_POWER_RESET_SYSCON=3Dy CONFIG_POWER_RESET_SYSCON_POWEROFF=3Dy -CONFIG_POWER_SUPPLY=3Dy CONFIG_RN5T618_POWER=3Dm CONFIG_SENSORS_MC13783_ADC=3Dy CONFIG_SENSORS_GPIO_FAN=3Dy @@ -283,13 +272,13 @@ CONFIG_VIDEO_OV5645=3Dm CONFIG_VIDEO_ADV7180=3Dm CONFIG_IMX_IPUV3_CORE=3Dy CONFIG_DRM=3Dy -CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_MSM=3Dy CONFIG_DRM_PANEL_LVDS=3Dy -CONFIG_DRM_PANEL_SIMPLE=3Dy -CONFIG_DRM_PANEL_EDP=3Dy CONFIG_DRM_PANEL_SEIKO_43WVF1G=3Dy +CONFIG_DRM_PANEL_EDP=3Dy +CONFIG_DRM_PANEL_SIMPLE=3Dy CONFIG_DRM_DISPLAY_CONNECTOR=3Dy +CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_LVDS_CODEC=3Dm CONFIG_DRM_SII902X=3Dy CONFIG_DRM_TI_TFP410=3Dy @@ -310,7 +299,6 @@ CONFIG_LCD_PLATFORM=3Dy CONFIG_BACKLIGHT_CLASS_DEVICE=3Dy CONFIG_BACKLIGHT_PWM=3Dy CONFIG_BACKLIGHT_GPIO=3Dy -CONFIG_FRAMEBUFFER_CONSOLE=3Dy CONFIG_LOGO=3Dy CONFIG_SOUND=3Dy CONFIG_SND=3Dy @@ -380,11 +368,8 @@ CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy -CONFIG_NEW_LEDS=3Dy -CONFIG_LEDS_CLASS=3Dy CONFIG_LEDS_GPIO=3Dy CONFIG_LEDS_PWM=3Dy -CONFIG_LEDS_TRIGGERS=3Dy CONFIG_LEDS_TRIGGER_TIMER=3Dy CONFIG_LEDS_TRIGGER_ONESHOT=3Dy CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy @@ -453,7 +438,6 @@ CONFIG_EXT3_FS_POSIX_ACL=3Dy CONFIG_EXT3_FS_SECURITY=3Dy CONFIG_QUOTA=3Dy CONFIG_QUOTA_NETLINK_INTERFACE=3Dy -# CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_AUTOFS_FS=3Dy CONFIG_FUSE_FS=3Dy CONFIG_ISO9660_FS=3Dm @@ -490,5 +474,4 @@ CONFIG_PRINTK_TIME=3Dy CONFIG_MAGIC_SYSRQ=3Dy CONFIG_DEBUG_FS=3Dy # CONFIG_SLUB_DEBUG is not set -# CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9147622DFF3 for ; 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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:34 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 05/10] ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER Date: Thu, 12 Jun 2025 11:07:50 +0200 Message-ID: <20250612090823.2519183-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA BMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index d40ca9edd264..917bc8a27794 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -180,6 +180,7 @@ CONFIG_TOUCHSCREEN_COLIBRI_VF50=3Dy CONFIG_INPUT_MISC=3Dy CONFIG_INPUT_MMA8450=3Dy CONFIG_INPUT_GPIO_BEEPER=3Dm +CONFIG_INPUT_PWM_BEEPER=3Dy CONFIG_SERIO_SERPORT=3Dm # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=3Dy --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53A8322FE18 for ; Thu, 12 Jun 2025 09:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719320; cv=none; b=ZgCnM80dCB2zZGe6BhTi86dePpCaYiaRBnzpyvyETUIrg9n2LLt8caVDGhk7iKWqx+HBOI6Bh8iczJayZZDodteV4cm0HseqbK224sji0Pda6W5uTwbHU0T9VzZ70yPjDNiPPfx61MK+9JmaXZST5cpJ7oblimnsLgo7MJ5+ajU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719320; c=relaxed/simple; bh=YxFgDvHxfy4wrScb+l1g58rALcetSmeE8HAFFojcXp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LdgwBN0Llp0415Sap0y75nxkZF7JBFNj/zhigHo2C7XjdOZJoMk5yGJHsk2xgc6dboCF+HnlhbU5dN+u3lAlmWbTtN96ywv/VSbTe1hJ6h/ym+NDZcycC/77rw7/qA/Ap7S7POBpPFeOB/ZAPQPotEu64zyx8dIRuw0fB/hSElI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=UxMBGiFI; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="UxMBGiFI" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-606b6dbe316so1536956a12.3 for ; Thu, 12 Jun 2025 02:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749719316; x=1750324116; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OE60H8an/td5GcTGMnbuvQU05tobHbDXITR9FPp9RlE=; b=UxMBGiFIM6O8F1G0NbhpWzlGfRLqfAfm2cKeoWB9i5/+LtZWO1VNZ+tB1sBUM8E5pE E6yXu7iJuhccFEpMF2XxFfDKSu1TufW9Ss0i+zojxrWyye7q82tJL4wz8sEfTwnwIgy2 388gzMeZmbzZA0AGsVG7jsfs+dPeI1o13GcO4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749719316; x=1750324116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OE60H8an/td5GcTGMnbuvQU05tobHbDXITR9FPp9RlE=; b=Z3+ePv6DKNajjrUHFxeJd9jOC5vMEiI5AAUx6e+3f81STdH/S1j/SPKsCSkltB0b2F SmH/GY4aLoIDIb5L6OzyUpFL5ogt4MFURRa8fW654Z3mD2Pl/YUWZ6D7wZZcEizlVQnl xn+YKEfTYHQ/XcjkX/HyUs81UQWRl/b/BoIrMlNTCi5KBY73ovyX2fZruXSbL0yf8kMg OhNoLfQ8C/H4LqMVExq9MmvR4MAP9qLAgNdaVKZAMD8sd4AQsVvQ3g5RXSqhNfRr19j2 84nyVJqC/9YytPTvgCoRiDlhUySIt2Lf2W/jumO8J56z4ux6hwds03IIdtIaWhwoPAjA 1QdA== X-Gm-Message-State: AOJu0Yyg/fMHBSOihCC93tjfV0YBOuBmLgJ2+1uJfDveH9K4QBeP0vwQ IfGi8tauS71/ArJmxzpHScWMluV9qdayNf1g+LzsGUIKAN4PEhXQ6hQW03P1oNnAF47mZqd/rj0 anj9/ X-Gm-Gg: ASbGncuep2++z5hz43RXJlFDXtqQX0Qomei1JFRKvFYIMm4p4EgPHZSgI4vjoVTlQXJ eTEqlX0DZCDfsCcur8KRWyBMzhTetYsntIjED1yZsdv/4HQGbp5gWt7ab0/bl9q9Uqrv49xyX1p qbclLYRRFXSlKCzUrYF7bp5oHKiaJcfphLgnk8dlyMV2hQA/htDaWXjnNofumJX6gO/04ukDV+X EWeIcl8nZiiftUShzyetLl1ypSLH79mPY6VIGVicv2qHH0vvkd81aH62Fr+LH5IRxwiAEoJL6ms GNnW2EswV1gwC7CXbfe77pnJv9MCKSCfvhpPqSgWO6jJQsjE/HbSLrBW1lcsGy8UCBGMuIGVlnJ SMsFvfKm7SxKU53IR+Zg1iESjMhljS2DhJCWb X-Google-Smtp-Source: AGHT+IFcDn8H6yXePDjRLYWwZpyHkFaAuz+TfNP7U5ZpLT7TwfQNs0Ve8Q5TEbBgBhShu+X5lj3DUQ== X-Received: by 2002:a17:907:1b1b:b0:ad2:4da6:f58c with SMTP id a640c23a62f3a-ade897ab542mr699899466b.46.1749719316389; Thu, 12 Jun 2025 02:08:36 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:36 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v4 06/10] dt-bindings: arm: fsl: support Engicam MicroGEA RMM board Date: Thu, 12 Jun 2025 11:07:51 +0200 Message-ID: <20250612090823.2519183-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA RMM board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5feb62611e53..58492b1cd468 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull =20 --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23977230BFB for ; Thu, 12 Jun 2025 09:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719322; cv=none; b=plvyLZJXCfv9lGT5bHtoxS7JcIb+RkKlCPDm42ZGtjfySWtsF2BQRwXnRjn4uQdpYPE+ved4IeRh1LKfwdA+iIpblPcv5Ch2EPcWtv/IBepz3RPpQ2iC7DhI3o3H2htGagjTwyjo8elaJgKODfbjRKmfKG/DF7lgZd3DvuGXEI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719322; c=relaxed/simple; bh=J18YJG3VlQkYbokWuevm7l92zJXJCW2ejUNKtpbGZj8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OAbw2S/h2Rv538agcWFItJdCuzO2EkHJHPlOFTmw7Ao5fx6uZwNeGrApi5tGezuxQs3xOLgZNlVuvHr+Gxet7wkvQwxE3s7uMfYrkyfg3bUHtbr2Szfi3swIHFOEi9wE18gMy7ZvEJCRgwstJuy0h9AUHuphqh4hL9GHFBDpdEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=VknWwHVd; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="VknWwHVd" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-ad89333d603so145572866b.2 for ; Thu, 12 Jun 2025 02:08:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749719318; x=1750324118; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ncgHuik/0sMUegckJw8LnO6mW6Me0WOvEDXQPt1J5GI=; b=VknWwHVd95obtzCT45q29Eah+bNeto8F24r32M4MPX8N7oYWBD9ojyX6qZ/xICUrkG qcgdFlRcbXCVyq4SVcHZOvO0hwStUazQMBdgwgUX1Hb5GL7IHAFYg0nHrJEzFSY1dU60 q7Oo4NZhnB4XMYxLd64/HLZMPQ60UFsUmY7vA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749719318; x=1750324118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ncgHuik/0sMUegckJw8LnO6mW6Me0WOvEDXQPt1J5GI=; b=F4E2X4e3BAOdTq78LLSrADQCHASKEuLzXvHDjG1aLOWOrGXnYEBIprWFCH58GSv1PO Ew2/gvK7jGWvyu/Slto7M+wwbQPk/IYzgMgMrB7mZ5IXf3Vsv0x1ge9XeIJmEbq5jzZu 58fpR7v7U4172+QuSkHnP2XDxJbX45/a0xu7cjU3TnI9gFuBtwT5XrP9jxXclQBBaLmz MD2XcSAgzrxDZS3Yk93VH7/GcNvOdfwQhwdBWrjeMxGfaRbQyDiw6SlcEiSAr8xo886s g+sAMOxcahJSxE+WLadcTlCH6NgX3wGnE/LhifAnCE6soo1qTW2C3YH9PS2siriUT8B0 esnQ== X-Gm-Message-State: AOJu0YzvBcfn6x5Azsc3fu9RX/rz5q3S67SwGIfnJ/phqjiRnpZs2zRW GN7tTx2ZP3I2124xB/3H1VNTW6pg+RVy5P0jQMkpw9c6HfJZNHQ0yPAR66nhbvohUL0bKJn3Tg8 nTfHm X-Gm-Gg: ASbGnctOP4orPhTKrCurVPUJwsYVXDhKQIDYcow00iegP7CQlT70GH01Q+6nrddxjCu sDlESiaIYYeIFHnwc+/Nkyv/glxnPPSaIq3tuhvRPQaQ+baqhgqkIXxac7taZ5h+96vbhujA1iV Z42C0wmKQg6jLzwtDEUdS/aXK1nuUJyZ9s/rGANLPuIyhP65023kDPFiYOpZHJc/JUHAIi69bkZ YlIFWb+q0tLRvYmJZNd3O/l7Nhgfv2m3u5cmvpxCmgATcnKm/oYv2w0KxJGdLUXTiCjRaJCB+9j JCdWvY76vSI03UItzTJ+1WEzDP2+SGRk1hZj9wZ6vAOGmtE4q5ShlgOGpRQlEgpYMdNKAFIPvEq nUCBAfcWKRMCwScM9hcPcn4CoxA== X-Google-Smtp-Source: AGHT+IFfA1wkO38alBM5BUFfuJuDQhOGzl8kgjSS1awhNl0FdmtWUKiJTlY3QMPXda8hfP3G/UmtAQ== X-Received: by 2002:a17:907:97d4:b0:ad5:749b:a735 with SMTP id a640c23a62f3a-ade89519c5bmr640896266b.27.1749719317994; Thu, 12 Jun 2025 02:08:37 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:37 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Peng Fan , Frank Li , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 07/10] ARM: dts: imx6ul: support Engicam MicroGEA RMM board Date: Thu, 12 Jun 2025 11:07:52 +0200 Message-ID: <20250612090823.2519183-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan Reviewed-by: Frank Li --- Changes in v4: - Add Reviewed-by tag of Frank Li Changes in v3: - Rename sgtl5000 node to audio-codec. - Move the reg property of the audio-codec node right after the compatible property. - Drop an extra blank line from iomuxc and iomuxc_snvs nodes. Changes in v2: - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. - Add Reviewed-by tag of Peng Fan arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-rmm.dts | 360 ++++++++++++++++++ 2 files changed, 361 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 57f185198217..32dfd69b8d8b 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..5d1cc8a1f555 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-rmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-rmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>; + + led-0 { + gpios =3D <&gpio2 10 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpio2 11 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <100000>; + status =3D "okay"; + + touchscreen: touchscreen@38 { + compatible =3D"edt,edt-ft5306"; + reg =3D <0x38>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_touchscreen>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <8 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio2 14 GPIO_ACTIVE_LOW>; + report-rate-hz =3D <6>; + /* settings valid only for Hycon touchscreen */ + touchscreen-size-x =3D <1280>; + touchscreen-size-y =3D <800>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + #sound-dai-cells =3D <0>; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb1_vbus>; + disable-over-current; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb2_vbus>; + disable-over-current; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x130b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_touchscreen: touchgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x17059 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_reg_usb1: regusb1grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_reg_ext_pwr: reg-ext-pwrgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x17059 + >; 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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:39 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v4 08/10] dt-bindings: arm: fsl: support Engicam MicroGEA GTW board Date: Thu, 12 Jun 2025 11:07:53 +0200 Message-ID: <20250612090823.2519183-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA GTW board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v3) Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 58492b1cd468..99ff7c78544b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-gtw # i.MX6ULL Engicam Micr= oGEA GTW Board - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull --=20 2.43.0 From nobody Sat Oct 11 00:26:54 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAFD923771C for ; Thu, 12 Jun 2025 09:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719324; cv=none; b=CjxrdKEhXqZR4slbnmAREGhuYBULTTXTWROSkOCQeOTQlZWHeyLRcGM96SRNSi3Cmf6CZAEXw7iGPHnJeRS5PUWeelbPpimdedA4uytohJA6t+4rnGNnenHMkW9bku5G1K6RKgyMOCeFrFIi3kL/iKp8lpK/uyx2n8de2rVXfdA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749719324; c=relaxed/simple; bh=LlJGcEz9mTLbDxR3Qqs5f/RJJVnu0uru4pS0PLwKA8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B3sbBtbg+CHFMOuaQ7zRezTvjaPD5K82fiaMql6awUnr17Hbn35oKLBtNN1WyM8iZkNrXntogP4ED4UbqfN3We9lt71dHMX1KQja7i758DD01wm3qJxrBTO1tkAC87NGVLNKCr75JNE6WR3jUqR21IIxDKZ6MCfaYdQ+KVi3+ZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=VDRpn9KG; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="VDRpn9KG" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-6084dfb4cd5so3189033a12.0 for ; Thu, 12 Jun 2025 02:08:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749719321; x=1750324121; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0e2lyscbGTEpgjA+Tcmkq75W9+66FuZZqCaAVTn3nUE=; b=VDRpn9KGOjMovm9FupBYBzwpUFa17kWlj1Z3zgq4aa2y7sRk0RK87JOeoh4N+0hf3O g5erA23C977D7oy6o2oPsY4Gs4To/zi/9H3h2d9aCKKccR1zcDzOVGnNV7pdRLTBXKVu DsJ+wtTiWzNDJk9FACDO4yIKIQKfrPEdJGyMs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749719321; x=1750324121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0e2lyscbGTEpgjA+Tcmkq75W9+66FuZZqCaAVTn3nUE=; b=G3/MCgDMmYbS3YUBKkCsyMC45JNdGy0KhMUWD2aU9SETWlYzSReEhYyUUWRUujLTBY rDxuNviqRlzWIXAdyMvVMXADiZHxKsDRyq0N7+ILnMN1vSf2LFxFbzhCD75+7cR+tIDX LBRy2U4qGtJheGV65n5u3S0MoWcRaeAviJ1iQfHkiyncYAUQLNaGbxQnV5i7CMr9MP/c p7/7iWsylBa8tH1VTGagCMftx414lQmu6Ff0nRipiTFJifVtYR/ED4cmu3pojma1YNAR I2KPlrxmcJajeXtPg2veYkIVuXlTT4l8DqSGc4wM3EckW+6KbhcJM6sot1lVF3i81sj0 FFhg== X-Gm-Message-State: AOJu0YzmGa6WXi1y9zhMr2wQdHYQGLml3CAnEl10lm0/lIF8zGJmJ6w3 tOaObmV2IgE1azNMBlmLH9kzq7VCxQsHSa9B4aOj3xYTUt9fnddjhd2dIS7CmyfORS88ss1JMqs rQN2a X-Gm-Gg: ASbGncvY9gEi9r1J9Ocuphg/j++3qozpBu3BO9J03oLD58reDyCuUiW8zDvuCaZlu3I PfZTCfKpiKwiVLwJ6+yk0j0hADP8uZXdht0vwiePNSsGj6MbrrXXrRdehuWfngq9oB83hHtuAvr Bg5IPaYtWNcMKxJxNZdvk6saVo4K0AeEw4SGgYDUN8d0rXJKUGbFLxmF7IQuDo8lFGTd8Hv3rTa 1n5eiJYlqkOkkGVRKb9TtwEgvTXOI/sP9/77LDgRcyufSIhlxohMNMdI94XpkxTvngerNlK3i7t iAg2x8EbkTjyQxdwd7ThU5sCKOqjHX8iYDOneCFr4y+/6rn3Mc+aR8IA4pwKZeEwC59vomcsLZt foELvUjPh4quKGdKWUcoiq2k6Eg== X-Google-Smtp-Source: AGHT+IGD0uwuwW/CU0Mqju/lT59H/tBc/6GgQq2Oak3Rd1d0+MeMDo7RKy+/oH3hKEDgeIrjUO+llg== X-Received: by 2002:a17:907:6d1a:b0:ad2:2fdb:b0ab with SMTP id a640c23a62f3a-adea56d1e61mr253704666b.29.1749719321062; Thu, 12 Jun 2025 02:08:41 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:40 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Frank Li , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 09/10] ARM: dts: imx6ul: support Engicam MicroGEA GTW board Date: Thu, 12 Jun 2025 11:07:54 +0200 Message-ID: <20250612090823.2519183-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v4: - Add Reviewed-by tag of Frank Li Changes in v3: - Drop an extra blank line from the iomuxc node. Changes in v2: - Drop an extra blank line - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-gtw.dts | 162 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 32dfd69b8d8b..de4142e8f3ce 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-gtw.dtb \ imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts new file mode 100644 index 000000000000..d500f8839102 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-gtw", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL GTW Board"; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_keys>; + + user-button { + label =3D "User button"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>, <&pinctrl_pwrled>; + + led-0 { + gpios =3D <&gpio5 7 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + led-1 { + gpios =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + gpios =3D <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios =3D <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_hub: usb-hub { + compatible =3D "smsc,usb3503a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_hub>; + reset-gpios =3D <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x130b0 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x130b0 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_pwrled: ledsgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x130b0 + >; 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([2.196.42.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adead4cf274sm99933366b.31.2025.06.12.02.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 02:08:42 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Matteo Lisi , Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 10/10] ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503 Date: Thu, 12 Jun 2025 11:07:55 +0200 Message-ID: <20250612090823.2519183-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> References: <20250612090823.2519183-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA GTW board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 917bc8a27794..3181775a214d 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -335,6 +335,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=3Dm CONFIG_USB_SERIAL_OPTION=3Dm CONFIG_USB_TEST=3Dm CONFIG_USB_EHSET_TEST_FIXTURE=3Dm +CONFIG_USB_HSIC_USB3503=3Dy CONFIG_USB_ONBOARD_DEV=3Dy CONFIG_NOP_USB_XCEIV=3Dy CONFIG_USB_MXS_PHY=3Dy --=20 2.43.0