From nobody Sat Oct 11 04:07:48 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DE7F225417 for ; Thu, 12 Jun 2025 08:14:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749716091; cv=none; b=KmHQTFAB8vl22UTF6jFu1TroaE5c+esXEuzh8PZz0KH98BvMGuPTOvUJ8fXLEGSBpKKPo/Jb1oag8DmqJ8A9BZeS0Hnpt+U8qQxhcQ92LQ++a0cdOnNzsXxseOGZPFMThS1lqJtaYpPJlBsPRHb5mIVTSs4iTWkS1zKy64v+8qM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749716091; c=relaxed/simple; bh=K7A9Oc5iBHVWHcFvJZJZLvJZIt7HtKz0exJw6/vU5Ws=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=goxmvbIiD1HLfUFtpTHB325gGPKjbvCIjMq6Wc8rQ7z9Q8Y1tcmIeGU7M+1WPits3paQ2c76RZXy1t7U9euaYnCuBtJhgl7NWV+eL8GFLGbNmoQQgJw3njMR8Dpab2e0mNoP0dmSg5u1XoR7iZsnympy7jnfXVnnZqPEQjIeaC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=FAKfVBg3; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="FAKfVBg3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749716088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sLNWxLQwILmLg6XdGZjj+lx4bdvP1n9cHv2pzNA9N64=; b=FAKfVBg38Jx4Txz7Ey7iTJu85m0xj43TgFzVJrvfKwbnoSQg4511ljsmf6lyqIQ137Z8ag LxKtqGUZHgFogElTv6rI0UXtOI+3GaoALmNF/SX8OKBSHWW25E7//8SF02kcqIBiVSVlX1 J0drNWMZUK1G9KaymcaIQ3G8D8NJaDA= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-8-OZrnFiOEPs-xZ0iFa7PHyA-1; Thu, 12 Jun 2025 04:14:45 -0400 X-MC-Unique: OZrnFiOEPs-xZ0iFa7PHyA-1 X-Mimecast-MFC-AGG-ID: OZrnFiOEPs-xZ0iFa7PHyA_1749716082 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A4B90195609F; Thu, 12 Jun 2025 08:14:42 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.28]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 84D5B195609D; Thu, 12 Jun 2025 08:14:37 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v9 6/9] drm/i915/display: Add drm_panic support Date: Thu, 12 Jun 2025 10:01:03 +0200 Message-ID: <20250612081344.225200-7-jfalempe@redhat.com> In-Reply-To: <20250612081344.225200-1-jfalempe@redhat.com> References: <20250612081344.225200-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 4 laptops, Haswell (with 128MB of eDRAM), Comet Lake, Raptor Lake, and Lunar Lake. For hardware using DPT, it's not possible to disable tiling, as you will need to reconfigure the way the GPU is accessing the framebuffer, so this will be handled by the following patches. Signed-off-by: Jocelyn Falempe --- v4: * Add support for Xe driver. =20 v6: * Use struct intel_display instead of drm_i915_private for intel_atomic_pl= ane.c =20 v7: * Fix mismatch {} in intel_panic_flush() (Jani Nikula) v8: * Use intel_bo_panic_setup() and intel_bo_panic_finish(). .../gpu/drm/i915/display/intel_atomic_plane.c | 81 ++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 15ede7678636..c310207e23e6 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -33,19 +33,23 @@ =20 #include #include +#include =20 #include #include #include +#include #include #include #include +#include =20 #include "gem/i915_gem_object.h" #include "i915_scheduler_types.h" #include "i915_vma.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" +#include "intel_bo.h" #include "intel_cdclk.h" #include "intel_cursor.h" #include "intel_display_rps.h" @@ -53,6 +57,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -1266,14 +1271,88 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct intel_plane *iplane =3D to_intel_plane(plane); + struct intel_display *display =3D to_intel_display(iplane); + struct drm_framebuffer *fb =3D plane_state->hw.fb; + struct drm_gem_object *obj; + + obj =3D intel_fb_bo(fb); + + intel_bo_panic_finish(obj); + + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer= .*/ + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(display->fbde= v.fbdev)) { + struct iosys_map map; + + intel_fbdev_get_map(display->fbdev.fbdev, &map); + drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height); + return; + } + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct intel_display *display =3D to_intel_display(plane->dev); + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state =3D to_intel_plane_state(plane->state); + fb =3D plane_state->hw.fb; + obj =3D intel_fb_bo(fb); + if (!obj) + return -ENODEV; + + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(display->fbde= v.fbdev)) { + intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); + } else { + int ret; + /* Can't disable tiling if DPT is in use */ + if (intel_fb_uses_dpt(fb)) + return -EOPNOTSUPP; + ret =3D intel_bo_panic_setup(obj, sb); + if (ret) + return ret; + } + sb->width =3D fb->width; + sb->height =3D fb->height; + /* Use the generic linear format, because tiling, RC, CCS, CC + * will be disabled in disable_tiling() + */ + sb->format =3D drm_format_info(fb->format->format); + sb->pitch[0] =3D fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs =3D { .prepare_fb =3D intel_prepare_plane_fb, .cleanup_fb =3D intel_cleanup_plane_fb, }; =20 +static const struct drm_plane_helper_funcs intel_primary_plane_helper_func= s =3D { + .prepare_fb =3D intel_prepare_plane_fb, + .cleanup_fb =3D intel_cleanup_plane_fb, + .get_scanout_buffer =3D intel_get_scanout_buffer, + .panic_flush =3D intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } =20 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_pla= ne_state, --=20 2.49.0