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Thu, 12 Jun 2025 00:49:35 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:5b9:e73a:2e58:5a47]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2364e63d42esm7893295ad.74.2025.06.12.00.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 00:49:35 -0700 (PDT) From: Chen-Yu Tsai To: Liam Girdwood , Mark Brown Cc: Chen-Yu Tsai , Jaroslav Kysela , Takashi Iwai , Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiaxin Yu , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] ASoC: mediatek: mt8183-afe-pcm: Support >32 bit DMA addresses Date: Thu, 12 Jun 2025 15:48:58 +0800 Message-ID: <20250612074901.4023253-8-wenst@chromium.org> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog In-Reply-To: <20250612074901.4023253-1-wenst@chromium.org> References: <20250612074901.4023253-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AFE DMA hardware supports up to 34 bits for DMA addresses. This is missing from the driver and prevents reserved memory regions from working properly when the allocated region is above the 4GB line. Fill in the related register offsets for each DAI, and also set the DMA mask. Also fill in the LSB end register offsets for completeness. Fixes: a94aec035a12 ("ASoC: mediatek: mt8183: add platform driver") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chen-Yu Tsai --- Changes in v3: - Rebased on top of "mt8183-afe-pcm: Shorten source code" --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediate= k/mt8183/mt8183-afe-pcm.c index 9b6b45c646e6..7383184097a4 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -6,6 +6,7 @@ // Author: KaiChieh Chuang =20 #include +#include #include #include #include @@ -432,6 +433,9 @@ static const struct snd_soc_component_driver mt8183_afe= _pcm_dai_component =3D { .reg_ofs_base =3D AFE_##_id##_BASE, \ .reg_ofs_cur =3D AFE_##_id##_CUR, \ .reg_ofs_end =3D AFE_##_id##_END, \ + .reg_ofs_base_msb =3D AFE_##_id##_BASE_MSB, \ + .reg_ofs_cur_msb =3D AFE_##_id##_CUR_MSB, \ + .reg_ofs_end_msb =3D AFE_##_id##_END_MSB, \ .fs_reg =3D (_fs_reg), \ .fs_shift =3D _id##_MODE_SFT, \ .fs_maskbit =3D _id##_MODE_MASK, \ @@ -463,11 +467,17 @@ static const struct snd_soc_component_driver mt8183_a= fe_pcm_dai_component =3D { #define AFE_VUL12_BASE AFE_VUL_D2_BASE #define AFE_VUL12_CUR AFE_VUL_D2_CUR #define AFE_VUL12_END AFE_VUL_D2_END +#define AFE_VUL12_BASE_MSB AFE_VUL_D2_BASE_MSB +#define AFE_VUL12_CUR_MSB AFE_VUL_D2_CUR_MSB +#define AFE_VUL12_END_MSB AFE_VUL_D2_END_MSB #define AWB2_HD_ALIGN_SFT AWB2_ALIGN_SFT #define VUL12_DATA_SFT VUL12_MONO_SFT #define AFE_HDMI_BASE AFE_HDMI_OUT_BASE #define AFE_HDMI_CUR AFE_HDMI_OUT_CUR #define AFE_HDMI_END AFE_HDMI_OUT_END +#define AFE_HDMI_BASE_MSB AFE_HDMI_OUT_BASE_MSB +#define AFE_HDMI_CUR_MSB AFE_HDMI_OUT_CUR_MSB +#define AFE_HDMI_END_MSB AFE_HDMI_OUT_END_MSB =20 static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] =3D { MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1), @@ -764,6 +774,10 @@ static int mt8183_afe_pcm_dev_probe(struct platform_de= vice *pdev) struct reset_control *rstc; int i, irq_id, ret; =20 + ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34)); + if (ret) + return ret; + afe =3D devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); if (!afe) return -ENOMEM; --=20 2.50.0.rc1.591.g9c95f17f64-goog