From nobody Sat Oct 11 04:13:36 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127BA21FF2B; Thu, 12 Jun 2025 07:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749712627; cv=none; b=CHKq1v3JAKGupN0IO5S3c26uPrOcanZExBqDRjr8QoMeAyScbNlK1Y9cdkiCkhUOTthZ5DMvQ2GudQ5dUsmMfNuWhVetMcyOZje7QJCpcHNiyS3wRvZUXkD0otEHkYj7Uk9vFWFZAIMIVJp+299++ZANLYbS5WxkHfjNXu73gTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749712627; c=relaxed/simple; bh=ORizRwkW5UGM2nvyiuP4pbNItvtgyRDfOGWPvRvoAEM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a9/pmT5db+M9qa4+gqsb5+skFSXmupCZ129S1kUEubjWtneFqbunivszrnnsFdMLJHUGDtwJ84hp+ftL9PUcVcO8WRtPpEf6FK/dhs9hMNqkw9ZO/Y38jluUxj9zmCVmKSXOI1UVRPmlfV6I+8u5LbhkMIlj/kiubHmSjqwgyv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=oaqzUFZp; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oaqzUFZp" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55C7H03V2800922; Thu, 12 Jun 2025 02:17:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1749712620; bh=ku/jjd89ljx7CQ5vE12Yi2egUmf/++KmoKuuLcxDrro=; h=From:To:Subject:Date:In-Reply-To:References; b=oaqzUFZp9FQrWVnDkTMNXahxCIRh4TaOyrZEgnr/ynPWmL50v+KH+gBbYv7v+TDWl mwUiVCm9ioeHmGQOcEK4hFDsH/W0gwWduy7GRrUCIU/OJJkOAMvYyVdwFGaljS4kj8 PssZme2Q9JEs9EM/5r4VLDPJyVJJcNjO5iiXVw+s= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55C7GxVl1619085 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 12 Jun 2025 02:16:59 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 12 Jun 2025 02:16:59 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 12 Jun 2025 02:16:59 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55C7FTKd1608959; Thu, 12 Jun 2025 02:16:55 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v2 17/17] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2 Date: Thu, 12 Jun 2025 12:45:21 +0530 Message-ID: <20250612071521.3116831-18-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612071521.3116831-1-s-adivi@ti.com> References: <20250612071521.3116831-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update glue layer to support PKTDMA V2 for non DMAengine users. The updates include - Handling absence of TISCI - Direct IRQs - Autopair: Lack of PSIL pair. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-glue.c | 91 ++++++++++++++++++++++---------- drivers/dma/ti/k3-udma-private.c | 48 +++++++++++++++-- drivers/dma/ti/k3-udma.h | 2 + 3 files changed, 110 insertions(+), 31 deletions(-) diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c index f87d244cc2d67..886d57dadacae 100644 --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c @@ -244,6 +244,9 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_= tx_channel *tx_chn) const struct udma_tisci_rm *tisci_rm =3D tx_chn->common.tisci_rm; struct ti_sci_msg_rm_udmap_tx_ch_cfg req; =20 + if (!tisci_rm->tisci) + return 0; + memset(&req, 0, sizeof(req)); =20 req.valid_params =3D TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | @@ -502,21 +505,26 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx= _channel *tx_chn) { int ret; =20 - ret =3D xudma_navss_psil_pair(tx_chn->common.udmax, - tx_chn->common.src_thread, - tx_chn->common.dst_thread); - if (ret) { - dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (tx_chn->common.udmax->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + } else { + ret =3D xudma_navss_psil_pair(tx_chn->common.udmax, + tx_chn->common.src_thread, + tx_chn->common.dst_thread); + if (ret) { + dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } =20 - tx_chn->psil_paired =3D true; + tx_chn->psil_paired =3D true; =20 - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); =20 - xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); + } =20 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); return 0; @@ -682,7 +690,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_= rx_channel *rx_chn) TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID; =20 - req.nav_id =3D tisci_rm->tisci_dev_id; req.index =3D rx_chn->udma_rchan_id; req.rx_fetch_size =3D rx_chn->common.hdesc_size >> 2; /* @@ -702,11 +709,18 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glu= e_rx_channel *rx_chn) req.rx_chan_type =3D TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR; req.rx_atype =3D rx_chn->common.atype_asel; =20 + if (!tisci_rm->tisci) { + // TODO: look at the chan settings + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG, + UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE); + return 0; + } + + req.nav_id =3D tisci_rm->tisci_dev_id; ret =3D tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req); if (ret) dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n", - rx_chn->udma_rchan_id, ret); - + rx_chn->udma_rchan_id, ret); return ret; } =20 @@ -755,8 +769,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glu= e_rx_channel *rx_chn, } =20 if (xudma_is_pktdma(rx_chn->common.udmax)) { - rx_ringfdq_id =3D flow->udma_rflow_id + + if (tisci_rm->tisci) + rx_ringfdq_id =3D flow->udma_rflow_id + xudma_get_rflow_ring_offset(rx_chn->common.udmax); + else + rx_ringfdq_id =3D flow->udma_rflow_id; rx_ring_id =3D 0; } else { rx_ring_id =3D flow_cfg->ring_rxq_id; @@ -803,6 +820,13 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glu= e_rx_channel *rx_chn, rx_ringfdq_id =3D k3_ringacc_get_ring_id(flow->ringrxfdq); } =20 + if (!tisci_rm->tisci) { + xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA, + UDMA_CHAN_RT_CTL_TDOWN | UDMA_CHAN_RT_CTL_PAUSE); + rx_chn->flows_ready++; + return 0; + } + memset(&req, 0, sizeof(req)); =20 req.valid_params =3D @@ -1307,6 +1331,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_r= x_channel *rx_chn, if (!rx_chn->remote) return -EINVAL; =20 + if (!tisci_rm->tisci) + return 0; + rx_ring_id =3D k3_ringacc_get_ring_id(flow->ringrx); rx_ringfdq_id =3D k3_ringacc_get_ring_id(flow->ringrxfdq); =20 @@ -1348,6 +1375,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_= rx_channel *rx_chn, if (!rx_chn->remote) return -EINVAL; =20 + if (!tisci_rm->tisci) + return 0; + memset(&req, 0, sizeof(req)); req.valid_params =3D TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | @@ -1383,21 +1413,26 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_= rx_channel *rx_chn) if (rx_chn->flows_ready < rx_chn->flow_num) return -EINVAL; =20 - ret =3D xudma_navss_psil_pair(rx_chn->common.udmax, - rx_chn->common.src_thread, - rx_chn->common.dst_thread); - if (ret) { - dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); - return ret; - } + if (rx_chn->common.udmax->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN); + } else { + ret =3D xudma_navss_psil_pair(rx_chn->common.udmax, + rx_chn->common.src_thread, + rx_chn->common.dst_thread); + if (ret) { + dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret); + return ret; + } =20 - rx_chn->psil_paired =3D true; + rx_chn->psil_paired =3D true; =20 - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, + UDMA_CHAN_RT_CTL_EN); =20 - xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, - UDMA_PEER_RT_EN_ENABLE); + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); + } =20 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en"); return 0; diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-priv= ate.c index 05228bf000333..5fccb8d18c898 100644 --- a/drivers/dma/ti/k3-udma-private.c +++ b/drivers/dma/ti/k3-udma-private.c @@ -3,18 +3,28 @@ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * Author: Peter Ujfalusi */ +#include +#include +#include +#include #include #include =20 int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead) { - return navss_psil_pair(ud, src_thread, dst_thread); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return navss_psil_pair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_pair); =20 int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, u32 dst_t= hread) { - return navss_psil_unpair(ud, src_thread, dst_thread); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return navss_psil_unpair(ud, src_thread, dst_thread); + + return 0; } EXPORT_SYMBOL(xudma_navss_psil_unpair); =20 @@ -159,15 +169,32 @@ void xudma_##res##rt_write(struct udma_##res *p, int = reg, u32 val) \ EXPORT_SYMBOL(xudma_##res##rt_write) XUDMA_RT_IO_FUNCTIONS(tchan); XUDMA_RT_IO_FUNCTIONS(rchan); +XUDMA_RT_IO_FUNCTIONS(rflow); =20 int xudma_is_pktdma(struct udma_dev *ud) { - return ud->match_data->type =3D=3D DMA_TYPE_PKTDMA; + return (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA || + ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2); } EXPORT_SYMBOL(xudma_is_pktdma); =20 int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id) { + if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + __be32 addr[2] =3D {0, 0}; + struct of_phandle_args out_irq; + int ret; + + out_irq.np =3D dev_of_node(ud->dev); + out_irq.args_count =3D 1; + out_irq.args[0] =3D udma_tflow_id; + ret =3D of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + return irq_create_of_mapping(&out_irq); + } + const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; =20 return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow); @@ -176,6 +203,21 @@ EXPORT_SYMBOL(xudma_pktdma_tflow_get_irq); =20 int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id) { + if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + __be32 addr[2] =3D {0, 0}; + struct of_phandle_args out_irq; + int ret; + + out_irq.np =3D dev_of_node(ud->dev); + out_irq.args_count =3D 1; + out_irq.args[0] =3D udma_rflow_id; + ret =3D of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + return irq_create_of_mapping(&out_irq); + } + const struct udma_oes_offsets *oes =3D &ud->soc_data->oes; =20 return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow); diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index b54962601f1e2..fea1213f65fe0 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -736,6 +736,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int re= g); void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val); bool xudma_rflow_is_gp(struct udma_dev *ud, int id); int xudma_get_rflow_ring_offset(struct udma_dev *ud); +u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg); +void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val); =20 int xudma_is_pktdma(struct udma_dev *ud); =20 --=20 2.34.1