From nobody Sat Oct 11 04:13:36 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1138620E708; Thu, 12 Jun 2025 07:16:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749712611; cv=none; b=DZBtZtcxV7zGH7skmiNOZ6bQwzldvi8yQZWn5SdLhUo4seqbeYYrH5O1nZjTFDl3p6caTjubE/vYgxsQHEuxgycjDWNyp4w+AR48fR6gMzCX/spm8raK8BL/RIxkqqhQe5Qz21HM9wCMXaq1zSx4tV/4lmVCWC0N8eKXR0E1foA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749712611; c=relaxed/simple; bh=mcBXc25SezpNu8Fu64THzBJQKzh+U1PDCzlOrEY1Qgo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eoFVVqb5z+p5fUMarugtilDQEj52sKgsplenw6y0mDsTQneMJkE5y5xQOv4ReG/hcuW0kCiYNOqpI9BG75YRD+bNXv+DENA3dw5nzOLRS4L1MUF3iTUW3s6FFGej1Yr3+7Cs2R1Mgm0iZyaNI0hKiknrMKeL6mwE8YjOhWU/xrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=DvnjpSKQ; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="DvnjpSKQ" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55C7Gjd91594338; Thu, 12 Jun 2025 02:16:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1749712605; bh=xZjpcaW9/RcazNOi9/Zz8F7DxKc8J2VCaUNbDIvFSCc=; h=From:To:Subject:Date:In-Reply-To:References; b=DvnjpSKQu+01Lnt5YCKHmpidkYifVFHiXcZ1eeAso8PNsVw0QeJBvciya/nCmotjc LPG2Ng3PRgkOlR3T3k6mtHrP5AVF1CjZP4/T3g0w9HiiqOa++7nN3ULVYCgawyGhnm HuHejDCmPGU500HNV3nPOQY8LwaJiqTqFSduWNRw= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55C7GiPU3448800 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 12 Jun 2025 02:16:45 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 12 Jun 2025 02:16:44 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 12 Jun 2025 02:16:44 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55C7FTKa1608959; Thu, 12 Jun 2025 02:16:40 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v2 14/17] dmaengine: ti: k3-psil-am62l: Add AM62Lx PSIL and PDMA data Date: Thu, 12 Jun 2025 12:45:18 +0530 Message-ID: <20250612071521.3116831-15-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250612071521.3116831-1-s-adivi@ti.com> References: <20250612071521.3116831-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add PSIL and PDMA data for AM62Lx SoC. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/Makefile | 3 +- drivers/dma/ti/k3-psil-am62l.c | 132 +++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 1 + 4 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/ti/k3-psil-am62l.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index 257e8141d7fe0..d282251b68058 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -13,6 +13,7 @@ k3-psil-lib-objs :=3D k3-psil.o \ k3-psil-am62.o \ k3-psil-am62a.o \ k3-psil-j784s4.o \ - k3-psil-am62p.o + k3-psil-am62p.o \ + k3-psil-am62l.o obj-$(CONFIG_TI_K3_PSIL) +=3D k3-psil-lib.o obj-$(CONFIG_TI_DMA_CROSSBAR) +=3D dma-crossbar.o diff --git a/drivers/dma/ti/k3-psil-am62l.c b/drivers/dma/ti/k3-psil-am62l.c new file mode 100644 index 0000000000000..45f5aac32f6a0 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62l.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.t= i.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D ch, \ + .default_flow_id =3D -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D ch, \ + .pkt_mode =3D 1, \ + .default_flow_id =3D -1 \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_NATIVE, \ + .pkt_mode =3D 1, \ + .needs_epib =3D 1, \ + .psd_size =3D 16, \ + .mapped_channel_id =3D ch, \ + .flow_start =3D flow_base, \ + .flow_num =3D flow_cnt, \ + .default_flow_id =3D flow_base, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x, ch) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .pdma_acc32 =3D 1, \ + .pdma_burst =3D 1, \ + .mapped_channel_id =3D ch, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62l_src_ep_map[] =3D { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400, 0), + PSIL_PDMA_XY_PKT(0x4401, 2), + PSIL_PDMA_XY_PKT(0x4402, 4), + PSIL_PDMA_XY_PKT(0x4403, 6), + PSIL_PDMA_XY_PKT(0x4404, 8), + PSIL_PDMA_XY_PKT(0x4405, 10), + PSIL_PDMA_XY_PKT(0x4406, 12), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4300, 16), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4301, 24), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4302, 32), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XY_TR(0x4303, 40), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500, 48), + PSIL_PDMA_MCASP(0x4501, 50), + PSIL_PDMA_MCASP(0x4502, 52), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0x4700, 65), + /* PDMA_MAIN0 - ADC */ + PSIL_PDMA_XY_TR(0x4503, 80), + PSIL_PDMA_XY_TR(0x4504, 81), + PSIL_ETHERNET(0x4600, 96, 96, 16), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62l_dst_ep_map[] =3D { + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xC400, 1), + PSIL_PDMA_XY_PKT(0xC401, 3), + PSIL_PDMA_XY_PKT(0xC402, 5), + PSIL_PDMA_XY_PKT(0xC403, 7), + PSIL_PDMA_XY_PKT(0xC404, 9), + PSIL_PDMA_XY_PKT(0xC405, 11), + PSIL_PDMA_XY_PKT(0xC406, 13), + /* PDMA_MAIN0 - SPI0 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC300, 17), + /* PDMA_MAIN0 - SPI1 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC301, 25), + /* PDMA_MAIN0 - SPI2 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC302, 33), + /* PDMA_MAIN0 - SPI3 - CH0-3 */ + PSIL_PDMA_XY_TR(0xC303, 41), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xC500, 49), + PSIL_PDMA_MCASP(0xC501, 51), + PSIL_PDMA_MCASP(0xC502, 53), + /* PDMA_MAIN0 - SHA */ + PSIL_PDMA_XY_TR(0xC700, 64), + /* PDMA_MAIN0 - AES */ + PSIL_PDMA_XY_TR(0xC701, 66), + /* PDMA_MAIN0 - CRC32 - CH0-1 */ + PSIL_PDMA_XY_TR(0xC702, 67), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 64, 64, 2), + PSIL_ETHERNET(0xc601, 66, 66, 2), + PSIL_ETHERNET(0xc602, 68, 68, 2), + PSIL_ETHERNET(0xc603, 70, 70, 2), + PSIL_ETHERNET(0xc604, 72, 72, 2), + PSIL_ETHERNET(0xc605, 74, 74, 2), + PSIL_ETHERNET(0xc606, 76, 76, 2), + PSIL_ETHERNET(0xc607, 78, 78, 2), +}; + +struct psil_ep_map am62l_ep_map =3D { + .name =3D "am62l", + .src =3D am62l_src_ep_map, + .src_count =3D ARRAY_SIZE(am62l_src_ep_map), + .dst =3D am62l_dst_ep_map, + .dst_count =3D ARRAY_SIZE(am62l_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index a577be97e3447..961b73df7a6bb 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -46,5 +46,6 @@ extern struct psil_ep_map am62_ep_map; extern struct psil_ep_map am62a_ep_map; extern struct psil_ep_map j784s4_ep_map; extern struct psil_ep_map am62p_ep_map; +extern struct psil_ep_map am62l_ep_map; =20 #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index c4b6f0df46861..2a843f36261bc 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -28,6 +28,7 @@ static const struct soc_device_attribute k3_soc_devices[]= =3D { { .family =3D "J784S4", .data =3D &j784s4_ep_map }, { .family =3D "AM62PX", .data =3D &am62p_ep_map }, { .family =3D "J722S", .data =3D &am62p_ep_map }, + { .family =3D "AM62LX", .data =3D &am62l_ep_map }, { /* sentinel */ } }; =20 --=20 2.34.1