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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2025 06:21:24.7025 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77ed16a9-c306-463a-719e-08dda9795b8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8467 Content-Type: text/plain; charset="utf-8" The HDMA IP supports the simple mode (non-linked list). In this mode the channel registers are configured to initiate a single DMA data transfer. The channel can be configured in simple mode via peripheral param of dma_slave_config param. Signed-off-by: Devendra K Verma --- drivers/dma/dw-edma/dw-edma-core.c | 10 +++++ drivers/dma/dw-edma/dw-edma-core.h | 2 + drivers/dma/dw-edma/dw-hdma-v0-core.c | 53 ++++++++++++++++++++++++++- include/linux/dma/edma.h | 8 ++++ 4 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index c2b88cc99e5d..4dafd6554277 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -235,9 +235,19 @@ static int dw_edma_device_config(struct dma_chan *dcha= n, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + struct dw_edma_peripheral_config *pconfig =3D config->peripheral_config; + unsigned long flags; + + if (WARN_ON(config->peripheral_config && + config->peripheral_size !=3D sizeof(*pconfig))) + return -EINVAL; =20 + spin_lock_irqsave(&chan->vc.lock, flags); memcpy(&chan->config, config, sizeof(*config)); + + chan->non_ll_en =3D pconfig ? pconfig->non_ll_en : false; chan->configured =3D true; + spin_unlock_irqrestore(&chan->vc.lock, flags); =20 return 0; } diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9e0b15..c0266976aa22 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -86,6 +86,8 @@ struct dw_edma_chan { u8 configured; =20 struct dma_slave_config config; + + bool non_ll_en; }; =20 struct dw_edma_irq { diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe909..3237c807a18e 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chun= k *chunk) readl(chunk->ll_region.vaddr.io); } =20 -static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +static void dw_hdma_v0_ll_start(struct dw_edma_chunk *chunk, bool first) { struct dw_edma_chan *chan =3D chunk->chan; struct dw_edma *dw =3D chan->dw; @@ -263,6 +263,57 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk= *chunk, bool first) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } =20 +static void dw_hdma_v0_non_ll_start(struct dw_edma_chunk *chunk) +{ + struct dw_edma_chan *chan =3D chunk->chan; + struct dw_edma *dw =3D chan->dw; + struct dw_edma_burst *child; + u32 val; + + list_for_each_entry(child, &chunk->burst->list, list) { + SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0)); + + /* Source address */ + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, lower_32_bits(child->sar)); + SET_CH_32(dw, chan->dir, chan->id, sar.msb, upper_32_bits(child->sar)); + + /* Destination address */ + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, lower_32_bits(child->dar)); + SET_CH_32(dw, chan->dir, chan->id, dar.msb, upper_32_bits(child->dar)); + + /* Transfer size */ + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); + + /* Interrupt setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK | + HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN; + + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN; + + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); + + /* Channel control setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, control1); + val &=3D ~HDMA_V0_LINKLIST_EN; + SET_CH_32(dw, chan->dir, chan->id, control1, val); + + /* Ring the doorbell */ + SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); + } +} + +static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +{ + struct dw_edma_chan *chan =3D chunk->chan; + + if (!chan->non_ll_en) + dw_hdma_v0_ll_start(chunk, first); + else + dw_hdma_v0_non_ll_start(chunk); +} + static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw =3D chan->dw; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747689f6..82d808013a66 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -101,6 +101,14 @@ struct dw_edma_chip { struct dw_edma *dw; }; =20 +/** + * struct dw_edma_peripheral_config - peripheral spicific configurations + * @non_ll_en: enable non-linked list mode of operations + */ +struct dw_edma_peripheral_config { + bool non_ll_en; +}; + /* Export to the platform drivers */ #if IS_REACHABLE(CONFIG_DW_EDMA) int dw_edma_probe(struct dw_edma_chip *chip); --=20 2.43.0