From nobody Sat Oct 11 00:42:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 432F221CC5D; Wed, 11 Jun 2025 21:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749678511; cv=none; b=YWqUvn21kMtUf7pb7hnirnf4GINUqPDKZ/8zqyyCUyZvfOxTu/QDLMKh5yjg/l3Y9h6PtiIs2MsCYyW5GCkB9VilRGv9W7K3ipHuvqnXhUaS9HKcYv5+Ci8sIF1L+fUrJgBF7haQl+MpWl9n2Busu5DBDyuyKPZrnOJiT81QvtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749678511; c=relaxed/simple; bh=1DZZD4FZcsjJllv0se6Cxs7D753+HnCfVphExKcrBrM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t5TNd1EXWwHsDAqbzKMpNP98sm4qZqPJoS5/CFqBFAsGCGBcQism/nCiBAQraI3wbMDoxV10cVfpts7CePYw9ClsDxh0ocDFx8YOHp6ET3943wvdVE8/BPv9hYjshVgtcQEnyfZVeIduBx7YjyvZOkuetEHmpMseKrXbLo2FliM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=RpV9QkIZ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="RpV9QkIZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1749678507; bh=1DZZD4FZcsjJllv0se6Cxs7D753+HnCfVphExKcrBrM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RpV9QkIZM07oSWPYP+3CivXV6O8AORZD+eNgWccoVp6DoJYxvOzJK2VGpbfyHIaPP NpXFEzNRidq5PYV2zfuhyiLOZsZHqcgIw34LVpolcsYeyNQMc20Jq/Pfl69XE1Bev+ NAzS26bbewJS99qunCqOyHoX7PLKPre4qPcxtDdDvXXXPAg2Z4mM5wzbzn/O0qsL9o c5WPkt1WzMLF3P/uDD5ERyModWtqH8XL2V81zMsp1qT08G3YDrgMwBRSl/k9wEm4pr gCUz+aams06njY+b8+tknv0q63P/Y9uiTT8oZptNNUNiy884kdLFiaS+nGHCKZ30Z9 amPMd+wZLjclQ== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 427C817E14DE; Wed, 11 Jun 2025 23:48:27 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 12 Jun 2025 00:47:47 +0300 Subject: [PATCH 1/3] dt-bindings: display: vop2: Add optional PLL clock property for rk3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250612-rk3576-hdmitx-fix-v1-1-4b11007d8675@collabora.com> References: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> In-Reply-To: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, Andy Yan , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.14.2 As with the RK3588 SoC, RK3576 also allows the use of HDMI PHY PLL as an alternative and more accurate pixel clock source for VOP2. Document the optional PLL clock property. Moreover, given that this is part of a series intended to address some recent display problems, provide the appropriate tags to facilitate backporting. Fixes: c3b7c5a4d7c1 ("dt-bindings: display: vop2: Add rk3576 support") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea Reviewed-by: Rob Herring (Arm) Tested-by: Nicolas Frattaroli --- .../bindings/display/rockchip/rockchip-vop2.yaml | 56 +++++++++++++++++-= ---- 1 file changed, 44 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index f546d481b7e5f496e1684f95edaa2fb97b840503..93da1fb9adc47b20dafc5fb03ee= 72f458a0f6228 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -64,10 +64,10 @@ properties: - description: Pixel clock for video port 0. - description: Pixel clock for video port 1. - description: Pixel clock for video port 2. - - description: Pixel clock for video port 3. - - description: Peripheral(vop grf/dsi) clock. - - description: Alternative pixel clock provided by HDMI0 PHY PLL. - - description: Alternative pixel clock provided by HDMI1 PHY PLL. + - {} + - {} + - {} + - {} =20 clock-names: minItems: 5 @@ -77,10 +77,10 @@ properties: - const: dclk_vp0 - const: dclk_vp1 - const: dclk_vp2 - - const: dclk_vp3 - - const: pclk_vop - - const: pll_hdmiphy0 - - const: pll_hdmiphy1 + - {} + - {} + - {} + - {} =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -175,10 +175,24 @@ allOf: then: properties: clocks: - maxItems: 5 + minItems: 5 + items: + - {} + - {} + - {} + - {} + - {} + - description: Alternative pixel clock provided by HDMI PHY PL= L. =20 clock-names: - maxItems: 5 + minItems: 5 + items: + - {} + - {} + - {} + - {} + - {} + - const: pll_hdmiphy0 =20 interrupts: minItems: 4 @@ -208,11 +222,29 @@ allOf: properties: clocks: minItems: 7 - maxItems: 9 + items: + - {} + - {} + - {} + - {} + - {} + - description: Pixel clock for video port 3. + - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY P= LL. + - description: Alternative pixel clock provided by HDMI1 PHY P= LL. =20 clock-names: minItems: 7 - maxItems: 9 + items: + - {} + - {} + - {} + - {} + - {} + - const: dclk_vp3 + - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 =20 interrupts: maxItems: 1 --=20 2.49.0 From nobody Sat Oct 11 00:42:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 089002459D2; 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Wed, 11 Jun 2025 23:48:36 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 12 Jun 2025 00:47:48 +0300 Subject: [PATCH 2/3] arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com> References: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> In-Reply-To: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, Andy Yan , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.14.2 As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more accurate pixel clock source for VOP2, which is actually mandatory to ensure proper support for display modes handling. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI PHY. Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea Tested-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 1086482f04792325dc4c22fb8ceeb27eef59afe4..6a13fe0c3513fb2ff7cd535aa70= e3386c37696e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -2391,6 +2391,7 @@ hdptxphy: hdmiphy@2b000000 { reg =3D <0x0 0x2b000000 0x0 0x2000>; clocks =3D <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; clock-names =3D "ref", "apb"; + #clock-cells =3D <0>; resets =3D <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; reset-names =3D "apb", "init", "cmn", "lane"; --=20 2.49.0 From nobody Sat Oct 11 00:42:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8048246BD8; Wed, 11 Jun 2025 21:48:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749678529; cv=none; b=BqcjPag/0/NoS3C8G108NVe5iBcy4YgjyZaPgUD0yCM6Tc9GcXToah6wqp41vhxXeqyWExPStXKUYaXnEvLvoDdoxCOvpfQ4wOJLbX9J1WnG605QszJs6IfCYVxVutnk+iu5SiBZizvByT4Es48T714dii66vqT5A7fMBCykA0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749678529; c=relaxed/simple; bh=p125Qdh7AXpcJlrV+7yqlZZwam5I0mnuIIk+bsJi8UU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jehTSceDXq4wo1appcXu70F3UOJ1vdHDSDRPeHkRp9fKN6OV5uNThmxov70mPe9yQCOR5atiOpJbyRu/l6Epci36QnHGsiFM4gxNBPJFyxpmOhL7ckxSQpTsHTkenuYL2BKpDQipUQ1T+WhQDJ57fhwOYmnCbcz45pXPTxLG3Tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EidgVnMi; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EidgVnMi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1749678526; bh=p125Qdh7AXpcJlrV+7yqlZZwam5I0mnuIIk+bsJi8UU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EidgVnMiQFzztrReyrHUBVJ/dgBh0iS528uSU6ZSU0dw/oVXjLTONw6yvYb3IBPqR fKgkeucn1eAdTsG9IGr5r2aUrGrxN6zYq7QdHqiCmC4B2zFZDg7TQ2Scgu1sd8Vkma /SDNw9lX2QVSf79dLPn5C6nN0SqBisjOIt9F2xoXzfsDGUwlygMqnwXUlB33nyq/cD J+eh0MSZQk8Vd1Il9blFhNbKZsEAk+7KZhyEnvNY1mRQzI+tfGnnc6nJ1MWCJYMAHN elozjHQDkEKzQZ3L1vxI/6Li0jeFjXFFpvi0NF2PChhCmw9F5Y1S3CwcqhF6ed1T5e 1bPu91kPSGFTQ== Received: from localhost (unknown [212.93.144.165]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id EFA8C17E0342; Wed, 11 Jun 2025 23:48:45 +0200 (CEST) From: Cristian Ciocaltea Date: Thu, 12 Jun 2025 00:47:49 +0300 Subject: [PATCH 3/3] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com> References: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> In-Reply-To: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, Andy Yan , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.14.2 Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi"), the workaround of passing the rate from DW HDMI QP bridge driver via phy_set_bus_width() became partially broken, as it cannot reliably handle mode switches anymore. Attempting to fix this up at PHY level would not only introduce additional hacks, but it would also fail to adequately resolve the display issues that are a consequence of the system CRU limitations. Instead, proceed with the solution already implemented for RK3588: make use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This will not only address the aforementioned problem, but it should also facilitate the proper operation of display modes up to 4K@60Hz. It's worth noting that anything above 4K@30Hz still requires high TMDS clock ratio and scrambling support, which hasn't been mainlined yet. Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") Cc: stable@vger.kernel.org Signed-off-by: Cristian Ciocaltea Tested-By: Detlev Casanova Tested-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 6a13fe0c3513fb2ff7cd535aa70e3386c37696e4..b1ac23035dd789f0478bf10c78c= 74ef167d94904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1155,12 +1155,14 @@ vop: vop@27d00000 { <&cru HCLK_VOP>, <&cru DCLK_VP0>, <&cru DCLK_VP1>, - <&cru DCLK_VP2>; + <&cru DCLK_VP2>, + <&hdptxphy>; clock-names =3D "aclk", "hclk", "dclk_vp0", "dclk_vp1", - "dclk_vp2"; + "dclk_vp2", + "pll_hdmiphy0"; iommus =3D <&vop_mmu>; power-domains =3D <&power RK3576_PD_VOP>; rockchip,grf =3D <&sys_grf>; --=20 2.49.0