From nobody Sat Oct 11 04:13:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890001E378C; Thu, 12 Jun 2025 06:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749710810; cv=none; b=MmzMRam2GgGMtgOa45bQQw8vnx4VTYEXtcTTENI1UzXbitcCPWkk1tfi4ZFYhnNTPLAChcIDilUd3EcSt8IfNCY9yVJ/338C/HGY63b+2dOHrigivF6YJexSxqEGDzkOMDyEB0U8NuAIgE/4+X8O/OI2tVnvJgjmcfMKFNXE8Hw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749710810; c=relaxed/simple; bh=8tdgdYgfMaFIYKxuLPz3G1JT90EuYmnj28QnPFEq9YU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BXyxi48RT7TeauibGpY4IFAARa6opSc4gezQHXk1cZTONAmrqPeWuxtTQefBpQr6tRLcuKnhjJazVEKS5O815JGN79k/u/NON6+vl1W5u9nClI1qwb5aaWW+I3od7KUYu3jlIWAZ7c7P+sTEtMd/nHp9odP83fSH1TL0i9hwC0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rzwN99A7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rzwN99A7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 22A02C4CEF0; Thu, 12 Jun 2025 06:46:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749710810; bh=8tdgdYgfMaFIYKxuLPz3G1JT90EuYmnj28QnPFEq9YU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rzwN99A7FaWXA8SCybauJwdq6kGfD4lJLaVAqDz4RuqWYTqt3AV60JT7jYrlyJgad KVedWqihxkQX/mfpFe7nawjsca8JsclFiTbSmPaPQFg8a40zrIdofXSsgTtNbAMZVk QAIbx0IQx1/YQzXZggaPYRc49XeeYQ6VAjHFQLN2PUf2JTyulLiMiCO8uhSO6BVOGD 76au7k0ul6nt+2N5mm+KCYqQrVdfCRbCzDsPmrULH8GOZWkx8zPXuQ+b0O49avNMQa xQuDmDxCAA9XZz0GNrvq2rtSyMcPWZgnO2h/kcFYrpF/bDg43+xpDnHLUKJFL5x92d jk5TEzPtNrGGg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E58FC71136; Thu, 12 Jun 2025 06:46:50 +0000 (UTC) From: George Moussalem via B4 Relay Date: Thu, 12 Jun 2025 10:46:14 +0400 Subject: [PATCH v13 2/2] arm64: dts: qcom: ipq5018: Add tsens node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com> References: <20250612-ipq5018-tsens-v13-0-a210f3683240@outlook.com> In-Reply-To: <20250612-ipq5018-tsens-v13-0-a210f3683240@outlook.com> To: Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Sricharan Ramabadhran , George Moussalem Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749710807; l=5419; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=MsKWr8/oQjZxIGUe4c9vPMrH2HVq4c/DwY1iNr6WoVs=; b=B4oK/7A/MVXqMX7hGZTLTshh4CBlGG/3Z6xMK3hA7jSC7r8rTa0V2+GsDZt3fB/PcfAvO9A87 x3wEfZoJtEICoQDS1EH4STHKXnbHtPgSY7f9lnMK0Qc2LUyZrB8v/W/ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Sricharan Ramabadhran IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem nodes and adding 4 thermal sensors (zones). The critical trip temperature is set to 120'C with an action to reboot. In addition, adding a cooling device to the CPU thermal zone which uses CPU frequency scaling. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..1b33ccf1a1b1af721b9690ae2c3= 5eb82985205f5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -39,6 +40,7 @@ cpu0: cpu@0 { next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@1 { @@ -49,6 +51,7 @@ cpu1: cpu@1 { next-level-cache =3D <&l2_0>; clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; }; =20 l2_0: l2-cache { @@ -182,6 +185,117 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + qfprom: qfprom@a0000 { + compatible =3D "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg =3D <0x000a0000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_mode: mode@249 { + reg =3D <0x249 0x1>; + bits =3D <0 3>; + }; + + tsens_base1: base1@249 { + reg =3D <0x249 0x2>; + bits =3D <3 8>; + }; + + tsens_base2: base2@24a { + reg =3D <0x24a 0x2>; + bits =3D <3 8>; + }; + + tsens_s0_p1: s0-p1@24b { + reg =3D <0x24b 0x2>; + bits =3D <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg =3D <0x24c 0x1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg =3D <0x24c 0x2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg =3D <0x24d 0x2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg =3D <0x24e 0x2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg =3D <0x24f 0x1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg =3D <0x24f 0x2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg =3D <0x250 0x2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg =3D <0x251 0x2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg =3D <0x254 0x1>; + bits =3D <0 6>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,ipq5018-tsens"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + + nvmem-cells =3D <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names =3D "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts =3D ; + interrupt-names =3D "uplow"; + #qcom,sensors =3D <5>; + #thermal-sensor-cells =3D <1>; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; @@ -631,6 +745,70 @@ pcie@0 { }; }; =20 + thermal-zones { + cpu-thermal { + thermal-sensors =3D <&tsens 2>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + + cpu_alert: cpu-passive { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gephy-thermal { + thermal-sensors =3D <&tsens 4>; + + trips { + gephy-critical { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors =3D <&tsens 3>; + + trips { + top-glue-critical { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + ubi32-thermal { + thermal-sensors =3D <&tsens 1>; + + trips { + ubi32-critical { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.49.0