From nobody Sat Oct 11 02:55:41 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14A252E8884 for ; Wed, 11 Jun 2025 22:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682088; cv=none; b=KtPex2C9s7K3fnD7qgNfI4LhsnutxM1Df3ILnadl76oMfRMVcTghmXh8kgjCEuT0D/vdsbg6rfF5ySn9hdeHxMXj6CsgSNK0fIjYxm+nIhdc3R74ZmkHvqdWaKqrq9YM+9A7VNCR63Fx0oEN1wI1/1aPGQ5nImEYQW2BMxCcdk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682088; c=relaxed/simple; bh=agTLIs+7ZgnhH/9jfFd6zwG8Wf/TcWn7XJunEBhtSx4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Mx/d3+pmUPN+nbn7fq+91QvFyAPcPJA7FurvnPc6rKxpw/fooIZbHVNb1nRVUFbjOg354fR/mzP+x8gbg08FK+6jwpMcMWg4BTKA0kA0W/wlXcQmqgGkCUYGjAHmSnHS8KMs0RJTW/Jho51kz07jGlMN9dqQ2W3AiiEHGtpDZhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=XBb9ZyZ0; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="XBb9ZyZ0" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-3132c1942a1so443821a91.2 for ; Wed, 11 Jun 2025 15:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749682086; x=1750286886; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Q1jGPlsD+uHDpRgxTkjVCkrhVGHj4h2DSBv3sZnUZ6I=; b=XBb9ZyZ0aIx/1zh4cX0XMmptSqx7eZkrg7fdjMQ+iwDXLvy0a2SfkfCnaqlrKsweXW uicWjN8U2LytcbXJzstyQGhTHMKwjwVf3HTrwA3jfHQjvKo7sEnteqVioOT8y1yFl0ld j7IwMBPRPxYMhj3t/YVeTOdGgEqNIvRUUcspYvmusDPUb5p6gYl8Nh3acpfx1StWiJlz HOgkPRslXRI61TDeCC4xc6Af2uTx8yZhdm+CPbUo8EfT4lS8q/LqV53GXQJ9fUCCBIH6 xRQRMCYQAkbbjJIndMsHI42dx4AYJKbo8qfBuwg9Cwm+UU98cLyGqyoX4Bzq3tljA+q5 lZ5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749682086; x=1750286886; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Q1jGPlsD+uHDpRgxTkjVCkrhVGHj4h2DSBv3sZnUZ6I=; b=taXw8Nci/I/1Sy6lYlP0kIMtvtCFodkDCjApQ8d6ysgGvkNggAARx4NFjD3VIrtBYG fj3WRDcBUAeHKeMZ5xwktSVFDFMBRCa0l0tGbJmxfgvMltsrRC4JU+uqnI1f46dXXmNr 9Bbo++VEEVOJIHEA0DOk8LGOYyC5h3olv96HVUajiKVqXJ1sMTXtWCYMlQjMCYNt0wrK KlebcrBEPvFkEQlfCLxiU9HV8nC5aCaPMwbmw7tG70aR5g/ZUOM25s+TKkYMPogR9zPm WB0hHNZppZn39CinCbwCAMhzb33sjwTibB2noozRjCM5v+Mk4SI1zk+QkFqK+2N/nxAb wzeg== X-Forwarded-Encrypted: i=1; AJvYcCXR5OCePAstG5cJvFvyOyeFpdKzzc5Ftjj5DSoPPm/QSzK43X8ljD8sEU0ogd0I2PctHmSR4V+bDNctr4I=@vger.kernel.org X-Gm-Message-State: AOJu0Yz5+LiAJ5IAvHWtrqt5eygbKj2/CHQWHiZ5rtO3kf5WFaWwj052 Bu5/c+hq1Dpg81mA/20SN01HKL8wlj5T6PJEV9Ma0WfHkmDy+ADTRk7+espWSoYvP3R9eTlntmC yEd2JYg== X-Google-Smtp-Source: AGHT+IGHoNvr6Cnk8J+KREg0HNO21SSc1Je6u1/AJsjFVgdYxx6GvgmCCTNG7aYe4NPsZfXP33le5zKfeT8= X-Received: from pjbsb6.prod.google.com ([2002:a17:90b:50c6:b0:312:2b3:7143]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1b41:b0:311:c1ec:7d12 with SMTP id 98e67ed59e1d1-313c08cf229mr1001910a91.23.1749682086599; Wed, 11 Jun 2025 15:48:06 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 11 Jun 2025 15:45:44 -0700 In-Reply-To: <20250611224604.313496-2-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250611224604.313496-2-seanjc@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250611224604.313496-43-seanjc@google.com> Subject: [PATCH v3 41/62] iommu/amd: Factor out helper for manipulating IRTE GA/CPU info From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split the guts of amd_iommu_update_ga() to a dedicated helper so that the logic can be shared with flows that put the IRTE into posted mode. Opportunistically move amd_iommu_update_ga() and its new helper above amd_iommu_activate_guest_mode() so that it's all co-located. Signed-off-by: Sean Christopherson --- drivers/iommu/amd/iommu.c | 87 +++++++++++++++++++++------------------ 1 file changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index bb804bbc916b..15718b7b8bd4 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3804,6 +3804,52 @@ static const struct irq_domain_ops amd_ir_domain_ops= =3D { .deactivate =3D irq_remapping_deactivate, }; =20 +static void __amd_iommu_update_ga(struct irte_ga *entry, int cpu) +{ + if (cpu >=3D 0) { + entry->lo.fields_vapic.destination =3D + APICID_TO_IRTE_DEST_LO(cpu); + entry->hi.fields.destination =3D + APICID_TO_IRTE_DEST_HI(cpu); + entry->lo.fields_vapic.is_run =3D true; + } else { + entry->lo.fields_vapic.is_run =3D false; + } +} + +/* + * Update the pCPU information for an IRTE that is configured to post IRQs= to + * a vCPU, without issuing an IOMMU invalidation for the IRTE. + * + * If the vCPU is associated with a pCPU (@cpu >=3D 0), configure the Dest= ination + * with the pCPU's APIC ID and set IsRun, else clear IsRun. I.e. treat vC= PUs + * that are associated with a pCPU as running. This API is intended to be= used + * when a vCPU is scheduled in/out (or stops running for any reason), to d= o a + * fast update of IsRun and (conditionally) Destination. + * + * Per the IOMMU spec, the Destination, IsRun, and GATag fields are not ca= ched + * and thus don't require an invalidation to ensure the IOMMU consumes fre= sh + * information. + */ +int amd_iommu_update_ga(int cpu, void *data) +{ + struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; + struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; + + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || + !entry || !entry->lo.fields_vapic.guest_mode) + return 0; + + if (!ir_data->iommu) + return -ENODEV; + + __amd_iommu_update_ga(entry, cpu); + + return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, + ir_data->irq_2_irte.index, entry); +} +EXPORT_SYMBOL(amd_iommu_update_ga); + int amd_iommu_activate_guest_mode(void *data) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; @@ -3985,45 +4031,4 @@ int amd_iommu_create_irq_domain(struct amd_iommu *io= mmu) =20 return 0; } - -/* - * Update the pCPU information for an IRTE that is configured to post IRQs= to - * a vCPU, without issuing an IOMMU invalidation for the IRTE. - * - * If the vCPU is associated with a pCPU (@cpu >=3D 0), configure the Dest= ination - * with the pCPU's APIC ID and set IsRun, else clear IsRun. I.e. treat vC= PUs - * that are associated with a pCPU as running. This API is intended to be= used - * when a vCPU is scheduled in/out (or stops running for any reason), to d= o a - * fast update of IsRun and (conditionally) Destination. - * - * Per the IOMMU spec, the Destination, IsRun, and GATag fields are not ca= ched - * and thus don't require an invalidation to ensure the IOMMU consumes fre= sh - * information. - */ -int amd_iommu_update_ga(int cpu, void *data) -{ - struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; - struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; - - if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || - !entry || !entry->lo.fields_vapic.guest_mode) - return 0; - - if (!ir_data->iommu) - return -ENODEV; - - if (cpu >=3D 0) { - entry->lo.fields_vapic.destination =3D - APICID_TO_IRTE_DEST_LO(cpu); - entry->hi.fields.destination =3D - APICID_TO_IRTE_DEST_HI(cpu); - entry->lo.fields_vapic.is_run =3D true; - } else { - entry->lo.fields_vapic.is_run =3D false; - } - - return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, - ir_data->irq_2_irte.index, entry); -} -EXPORT_SYMBOL(amd_iommu_update_ga); #endif --=20 2.50.0.rc1.591.g9c95f17f64-goog