From nobody Sat Oct 11 02:58:45 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DBAA2D29DF for ; Wed, 11 Jun 2025 22:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682048; cv=none; b=MVfa47IwUaQ+IX0LWk3XV8SwMXG08FvzI8koC/CbspWlYSF6ygT51Gkr1aMBl0eQ5B8NicwGyjY4U1hemhWoYovxLeLfnGglb3c2tJkiIWZ3VmLsm+Im7Des42AZyGRrMcDQFLiXVjm9i5dxdSeicQPd7tVTTGlqvayoHZ0wC+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682048; c=relaxed/simple; bh=547ahGwYktSn5Nv2W53Rc8bmaZFK3eiGWpUYnwdvnmw=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=NY3oOWGZuhls7Duc7t8oTl+p2y91OWEDhfOEkCXhehLaak2DX7LqDT9TZ1QHNFdpZkMfB3GNhmfjKNLKE8C1uLny8LAnE5EFJ+jWFuW1RX3qTIpfwBynorvKoeguRkqIRD3aLydVy2wVhKHE0fu1o8nZ8jDASGYlPxdXiuWgCd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=q+k/Dw0c; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="q+k/Dw0c" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-311b6d25163so282644a91.0 for ; Wed, 11 Jun 2025 15:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749682045; x=1750286845; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Y7mFXgOTZx56ZNft/YcUy8E2TW8/wko5wqyDmOqvjJg=; b=q+k/Dw0cER5rTtOYX0COH92Xxt7CFPsK46j5Pi8tgZiVf7K7m3CJfTmFrvjRKMv98p AkK7YvO98ZjGBoxHL/gvzNc9fdelrB6NSHueztmyS/tQYgCJ8NsgMYnVuPt6pFX3pBWm OHdIZDpvf4IqArDvZ6vfgcuAxw1UjdB9qzuRtYrFh4DTGvZOLNNBEif7gA9eGg1ngqF9 mTXtGgT7sGiJPX2hsqLt1z+1tvnK/F78MdfMmPsse/QOyqsCu3HDyqa+dVwdHuK6jQ9M YdYhKzWqbj+5tpB7YUJ1FW4ZOocDQvh25cRxlXARIiGlUNNkhKOIcZJjljtimfK/xQDj VTRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749682045; x=1750286845; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Y7mFXgOTZx56ZNft/YcUy8E2TW8/wko5wqyDmOqvjJg=; b=vSox/5wan1zBhV88TpRusjiWNKyCHAA858p9mEHQo29cZYiIhT+KrXQio2qDMxj2PJ BYLTlXh5sWzTlZTVjpXYJ3I4IdoQj0KWwXdw2yE6B5AdwqGfTEMmgmWR5lJUmXwxN3Ic bIW7BerLzttlfluXVp64IkVs9E0CjK/rq+cI693vI4GAiyzwi0jBSSH3ngIZ1nL3y9eM wi2LCBbZ66/yQoX5Rp9w/V9nODuLKRq8YKgzyG72EPIzuznPADCv8U/3vU31vc0IN7Uk vLtmRP3LKJJJ2XJ3qzvD51IGYKW/pt2jBJW8/dLWpPyalQyoajBA1oYM926VU+TbTWe8 0JvA== X-Forwarded-Encrypted: i=1; AJvYcCWFUWeg+t4rgMS8AhUKi6ZI/AO4jSk4tOytmbRkj4cKKbXdsQfaQZCqZbHIWcjxVQ0RlNe0hyj2z17ZE18=@vger.kernel.org X-Gm-Message-State: AOJu0Yx/gIXgeF9ElSa/HS60GnAztOf2+JHasygLfKVtwkO6DewgDb2n CbVWIAaZldsAa1fXQwZxbESp3kSHYNsxk0hOtjQoc4UVzyjBVpUCpWmSmu72ryhOunMpfFlsYAK oWKCpyA== X-Google-Smtp-Source: AGHT+IHhbL/TBZCG5Y/ATXxmlqQOVoqO8b5Q5McIR7KBGzNPtc92BdBjMfFoGArRz+XJKDhkjLGjJDSDCHk= X-Received: from pjbqi5.prod.google.com ([2002:a17:90b:2745:b0:30a:31eb:ec8e]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:510f:b0:313:2754:5910 with SMTP id 98e67ed59e1d1-313bfbc310bmr1845151a91.15.1749682045371; Wed, 11 Jun 2025 15:47:25 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 11 Jun 2025 15:45:20 -0700 In-Reply-To: <20250611224604.313496-2-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250611224604.313496-2-seanjc@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250611224604.313496-19-seanjc@google.com> Subject: [PATCH v3 17/62] KVM: SVM: Add enable_ipiv param, never set IsRunning if disabled From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maxim Levitsky Let userspace "disable" IPI virtualization for AVIC via the enable_ipiv module param, by never setting IsRunning. SVM doesn't provide a way to disable IPI virtualization in hardware, but by ensuring CPUs never see IsRunning=3D1, every IPI in the guest (except for self-IPIs) will generate a VM-Exit. To avoid setting the real IsRunning bit, while still allowing KVM to use each vCPU's entry to update GA log entries, simply maintain a shadow of the entry, without propagating IsRunning updates to the real table when IPI virtualization is disabled. Providing a way to effectively disable IPI virtualization will allow KVM to safely enable AVIC on hardware that is susceptible to erratum #1235, which causes hardware to sometimes fail to detect that the IsRunning bit has been cleared by software. Note, the table _must_ be fully populated, as broadcast IPIs skip invalid entries, i.e. won't generate VM-Exit if every entry is invalid, and so simply pointing the VMCB at a common dummy table won't work. Alternatively, KVM could allocate a shadow of the entire table, but that'd be a waste of 4KiB since the per-vCPU entry doesn't actually consume an additional 8 bytes of memory (vCPU structures are large enough that they are backed by order-N pages). Signed-off-by: Maxim Levitsky [sean: keep "entry" variables, reuse enable_ipiv, split from erratum] Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 32 ++++++++++++++++++++++++++------ arch/x86/kvm/svm/svm.c | 2 ++ arch/x86/kvm/svm/svm.h | 8 ++++++++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 0c0be274d29e..48c737e1200a 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -292,6 +292,13 @@ static int avic_init_backing_page(struct kvm_vcpu *vcp= u) /* Setting AVIC backing page address in the phy APIC ID table */ new_entry =3D avic_get_backing_page_address(svm) | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; + svm->avic_physical_id_entry =3D new_entry; + + /* + * Initialize the real table, as vCPUs must have a valid entry in order + * for broadcast IPIs to function correctly (broadcast IPIs ignore + * invalid entries, i.e. aren't guaranteed to generate a VM-Exit). + */ WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 return 0; @@ -769,8 +776,6 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) { struct kvm_vcpu *vcpu =3D &svm->vcpu; - struct kvm *kvm =3D vcpu->kvm; - struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); unsigned long flags; u64 entry; =20 @@ -788,7 +793,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, * will update the pCPU info when the vCPU awkened and/or scheduled in. * See also avic_vcpu_load(). */ - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); @@ -998,14 +1003,26 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 + svm->avic_physical_id_entry =3D entry; + + /* + * If IPI virtualization is disabled, clear IsRunning when updating the + * actual Physical ID table, so that the CPU never sees IsRunning=3D1. + * Keep the APIC ID up-to-date in the entry to minimize the chances of + * things going sideways if hardware peeks at the ID. + */ + if (!enable_ipiv) + entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); @@ -1030,7 +1047,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) * can't be scheduled out and thus avic_vcpu_{put,load}() can't run * recursively. */ - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) @@ -1049,7 +1066,10 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) avic_update_iommu_vcpu_affinity(vcpu, -1, 0); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); + svm->avic_physical_id_entry =3D entry; + + if (enable_ipiv) + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); =20 diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0ad1a6d4fb6d..56d11f7b4bef 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -231,6 +231,7 @@ module_param(tsc_scaling, int, 0444); */ static bool avic; module_param(avic, bool, 0444); +module_param(enable_ipiv, bool, 0444); =20 module_param(enable_device_posted_irqs, bool, 0444); =20 @@ -5594,6 +5595,7 @@ static __init int svm_hardware_setup(void) enable_apicv =3D avic =3D avic && avic_hardware_setup(); =20 if (!enable_apicv) { + enable_ipiv =3D false; svm_x86_ops.vcpu_blocking =3D NULL; svm_x86_ops.vcpu_unblocking =3D NULL; svm_x86_ops.vcpu_get_apicv_inhibit_reasons =3D NULL; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index f225d0bed152..939ff0e35a2b 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -307,6 +307,14 @@ struct vcpu_svm { u32 ldr_reg; u32 dfr_reg; =20 + /* This is essentially a shadow of the vCPU's actual entry in the + * Physical ID table that is programmed into the VMCB, i.e. that is + * seen by the CPU. If IPI virtualization is disabled, IsRunning is + * only ever set in the shadow, i.e. is never propagated to the "real" + * table, so that hardware never sees IsRunning=3D1. + */ + u64 avic_physical_id_entry; + /* * Per-vCPU list of irqfds that are eligible to post IRQs directly to * the vCPU (a.k.a. device posted IRQs, a.k.a. IRQ bypass). The list --=20 2.50.0.rc1.591.g9c95f17f64-goog