From nobody Sat Oct 11 01:19:45 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00D762D0289 for ; Wed, 11 Jun 2025 22:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682045; cv=none; b=Y+daEP6bn2QUggY//TMM1dK96hsBQg0i3E1ngNKccpEPFjY2y7vMKaIK/AFe1etkAe9efOzkhJ1/lE3x8lz/Mmhe8zdUcvwdDevgpVd6kVWUdw0yry6gIG4s9YwYChbj9rrXJ1jbggio2Pdj+N1NW/lILgIUZmo3SJKT7UpZz+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682045; c=relaxed/simple; bh=+hv/L1bIbXZPSlj1hiWZXItfDwwPTIV42fY47pjIvko=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=elwcYtauDeyL9aIfyVQUJ9FpkfI3k3/aeMVZ9jnZPOISKTDtPsUuqSEOLuZyL7b/GD385aEasiKnRLMOpGPMX7lmAxUO7NeftPE7EjSVfgSnpbkbum7oHNl1r8RJiaOeq5F7tfKs4mkseRzXdqZllKki+9nB3mtD9wcMQDAdjeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=c13GGK2k; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="c13GGK2k" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-747af0bf0ebso257996b3a.1 for ; Wed, 11 Jun 2025 15:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749682042; x=1750286842; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=uVzEHyBaRiJNDQh5a5Dx7H8kv7wjszZU3WXvYcKHvtU=; b=c13GGK2kPYyJ2BAUi2iyLhwVQXBHN3TyysTZeSeumO5pOKSxonFudIW+ENXfxYocMT Gv5bHVA7svt6Z7LTl2wcT4K38t1jjE01IAVK1DbMMhayQqL4UJqKSrIR1VMscRMuQDQp pAM7LlkXOwCfWqB8+ipZb3odrxegS2yGykQrhf7eynDTwgwpy5Gn5uQ2DnHVkqDVctDl QC13qA+BuXsCQAw62rcpWQRcji17AxI+Ke2QyrgFJq1W9QN8V0a6pJDSgRv82K0U1+3G 465bWPEr+KPdpb37jQ7S4S3WjY2D/ovbInOXkWJDBjArZukt6PTnWIUDhGiFsRU3VN2E Vgww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749682042; x=1750286842; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uVzEHyBaRiJNDQh5a5Dx7H8kv7wjszZU3WXvYcKHvtU=; b=ilFI1rqB3hMInjQVBS6ulQIU5VBJzFr4QTRxRy6Bmx+9DqvK2KlDSYyQ4eeGlEPOnP LuAR6RkHA1vE8MoJGPiZOU7objbpo/orxl7RTVfh/JkEge9/of+2PTvTnQAw1w7ebfzs 9GWZUEsUNftHbDq7kjgbetXmVDolLPijYeLKJs2dGtzG8dwpcxWq7YwegOb8TNmh4XVy IimtyTq2dOXDOh6/znnW1kffZWqjvPP2blw4JsTTFJPQ6G7IL7CFWzLXCWiTnKEr5NUb vv5GZ76diUf2ttHt0K6/l4Q7a/uBAglovTjx6eWM2oHBptaYZuFwMh1SjwNyC28n+i7n 1xnQ== X-Forwarded-Encrypted: i=1; AJvYcCXzYDPBeU5xAbLQqXJ7BAtjrhshd8mZmVVG9fU25mdfyQpaff3P8SzzDi8BC3NezKj8YnyldOv3IYpik1A=@vger.kernel.org X-Gm-Message-State: AOJu0YxqqOfzH1iPyVH4BRFBBhBJOdwI6rjD04NVMVUd8+4Bb2+FsUDR SShjCVLMcWvbmyUnBtMRIPxmeEeUPOfDBx/nVVWqQXmrMftNpmBmqtWakQOH4b1taQFKGOSrkOo 6nOQ1yA== X-Google-Smtp-Source: AGHT+IFakcvyKnqCueAUeZlAT109XlS9YCn8fDNscX2Sisdyt0t4bYMkEX6AxhE9x+pXQlvyQldIB86adbU= X-Received: from pfnx17.prod.google.com ([2002:aa7:84d1:0:b0:746:27ff:87f8]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:72a1:b0:210:1c3a:6804 with SMTP id adf61e73a8af0-21f9bbb2da4mr712401637.31.1749682042326; Wed, 11 Jun 2025 15:47:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 11 Jun 2025 15:45:18 -0700 In-Reply-To: <20250611224604.313496-2-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250611224604.313496-2-seanjc@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250611224604.313496-17-seanjc@google.com> Subject: [PATCH v3 15/62] KVM: SVM: Drop superfluous "cache" of AVIC Physical ID entry pointer From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the vCPU's pointer to its AVIC Physical ID entry, and simply index the table directly. Caching a pointer address is completely unnecessary for performance, and while the field technically caches the result of the pointer calculation, it's all too easy to misinterpret the name and think that the field somehow caches the _data_ in the table. No functional change intended. Suggested-by: Maxim Levitsky Tested-by: Sairaj Kodilkar Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 27 +++++++++++++++------------ arch/x86/kvm/svm/svm.h | 1 - 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index bf18b0b643d9..0c0be274d29e 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -294,8 +294,6 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 - svm->avic_physical_id_cache =3D &kvm_svm->avic_physical_id_table[id]; - return 0; } =20 @@ -770,13 +768,16 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct kvm_kernel_irqfd *irqfd, struct amd_iommu_pi_data *pi) { + struct kvm_vcpu *vcpu =3D &svm->vcpu; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); unsigned long flags; u64 entry; =20 if (WARN_ON_ONCE(!pi->ir_data)) return -EINVAL; =20 - irqfd->irq_bypass_vcpu =3D &svm->vcpu; + irqfd->irq_bypass_vcpu =3D vcpu; irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); @@ -787,7 +788,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, * will update the pCPU info when the vCPU awkened and/or scheduled in. * See also avic_vcpu_load(). */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); @@ -964,17 +965,18 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu= , int cpu, bool r) =20 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); int h_physical_id =3D kvm_cpu_get_apicid(cpu); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK= )) return; =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -996,14 +998,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); @@ -1011,13 +1013,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) =20 void avic_vcpu_put(struct kvm_vcpu *vcpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -1027,7 +1030,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) * can't be scheduled out and thus avic_vcpu_{put,load}() can't run * recursively. */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) @@ -1046,7 +1049,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) avic_update_iommu_vcpu_affinity(vcpu, -1, 0); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index ec5d77d42a49..f225d0bed152 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -306,7 +306,6 @@ struct vcpu_svm { =20 u32 ldr_reg; u32 dfr_reg; - u64 *avic_physical_id_cache; =20 /* * Per-vCPU list of irqfds that are eligible to post IRQs directly to --=20 2.50.0.rc1.591.g9c95f17f64-goog