From nobody Sat Oct 11 01:19:06 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A373B262FD7 for ; Wed, 11 Jun 2025 22:47:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682034; cv=none; b=aI4/0Lkce44WE3GDI1dCI3hVt/kEq6RaalwyyIxvFRVinClXG11EJKQyUWRwNc7j0wulrR7qNgZIv2LehMZf23psOJ8/QBwhEH1y0qasDF3/P3/+2vzekoorQPRDMEjtsCsmoPAjapbkUCklfX4lyUMh8ImM0Vth4qdTKdlZSrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749682034; c=relaxed/simple; bh=hEiCQzEBv68hmHUNBF+zRpCEthWLf82WC5scO76qyP8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=fl35eF0gL/drqZNFmw115q+Uk4btoRtzuvxCX4uY8f/cgJgDN8XcJTH839NwnJHMU1cH5/wDfR6iYbx+kLaI5AoDCJwrV4u2pROwEPiKH0WqpDkYr3D08DrFfB9KM5B7oJYhX1wg2NMh+YlnnNcN3vEdSnP5powXzYLQFT9vyDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=uJ2eEBif; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="uJ2eEBif" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-b2eeff19115so270475a12.0 for ; Wed, 11 Jun 2025 15:47:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749682032; x=1750286832; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=I8oMP1EOncIUD9US+9qQ69z324nW43UQ9Vgx7SP4DmY=; b=uJ2eEBifG4aTVZqARlTYGMF/Jad4xApy5MNWj8o7hJM7VVGzfiK3ea5wgMrroFua30 WOTSDDpErka2DjgcX97hdRfmum2P7JvoV3PCaNVdwfNKP/Y9voc0vUWDzwn+F9knSf2y iylJaJ/i0ooJOoYf14SzUjRR4iaXoyjcJkseHl4zkdfn3WWLl8ocbOWiz5Hl9ii/Ib/Z gut4ncm8Xj3AVYm0+33aqjZVG0EaLiN55fWpAJmRt9a2RVMtylHoZbvdk7asSHYLUzeR wES1qEDtJPYQvGec9qDQ+PfA5Ft+rJkeJG3O6GD0Ot6fnCROdIxVFc1PRv73/U9oiiMj 2JUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749682032; x=1750286832; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=I8oMP1EOncIUD9US+9qQ69z324nW43UQ9Vgx7SP4DmY=; b=kmEeAk5B38Wjc/ahazZOPnNs/tsYwREa0Fvdqg0nve7dx5HhOpgaJ1pdOSUsjQlaXc pm/DjmwSPai8cHtpguUMe0dvgsUDqxCQzvIqsrzIrp/miKd777iaDan3PrWjSYkGizhl wxwCeqyRu/UZ/n8FGCUiPWHoEa2WaJg4vQ7OuFPC35o34sagBxz2berVkoAjL9NsIQp7 adSvU042TKnJ0K2JeLkzLHQoms7SmSJwX8USTKXr6H54UeUE5yTsIiFn2o2BJHrGOgg6 eO5hU+nC1H6LY7UysiOUi3SoLXdDeP73/JPVzpMdaME2uzKj/RhdkaxEcWqXu3rVg1EK oMXA== X-Forwarded-Encrypted: i=1; AJvYcCXGaLL0LTAUPyuGUHOpsmYjM09MMgAjpbTzBOzcmw+PBpcKG8yi9M4xHFR57GZCvWHsgTGfwncXTvgIjE4=@vger.kernel.org X-Gm-Message-State: AOJu0YyV4U/uy7E+LxJEeIy0gODrOTuu8oVYCAPMoC6lA+1kqf/uTmE0 OIXF1j6av+Bk1b4lVjVl1Nz1IDRTaVGyGiWvSIQdU+Ko7oR+/UB7iKF/jvZyzD+go2jDQoHrBhD eIea8Mw== X-Google-Smtp-Source: AGHT+IFCw4nm3TFxQYvAdNmh6gnDBKhiV2T9Iv4xzvZMX9NqKTRoM2Z40bqRwgvAKgtWr8chRpb35/3TV8M= X-Received: from pgn7.prod.google.com ([2002:a63:d47:0:b0:b2e:ce0c:b3fb]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:728a:b0:1f5:8622:5ed5 with SMTP id adf61e73a8af0-21f866001b6mr7401056637.3.1749682031934; Wed, 11 Jun 2025 15:47:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 11 Jun 2025 15:45:12 -0700 In-Reply-To: <20250611224604.313496-2-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250611224604.313496-2-seanjc@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250611224604.313496-11-seanjc@google.com> Subject: [PATCH v3 09/62] KVM: SVM: Drop pointless masking of kernel page pa's with AVIC HPA masks From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Sairaj Kodilkar , Vasant Hegde , Maxim Levitsky , Joao Martins , Francesco Lavra , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop AVIC_HPA_MASK and all its users, the mask is just the 4KiB-aligned maximum theoretical physical address for x86-64 CPUs, as x86-64 is currently defined (going beyond PA52 would require an entirely new paging mode, which would arguably create a new, different architecture). All usage in KVM masks the result of page_to_phys(), which on x86-64 is guaranteed to be 4KiB aligned and a legal physical address; if either of those requirements doesn't hold true, KVM has far bigger problems. Drop masking the avic_backing_page with AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK for all the same reasons, but keep the macro even though it's unused in functional code. It's a distinct architectural define, and having the definition in software helps visualize the layout of an entry. And to be hyper-paranoid about MAXPA going beyond 52, add a compile-time assert to ensure the kernel's maximum supported physical address stays in bounds. The unnecessary masking in avic_init_vmcb() also incorrectly assumes that SME's C-bit resides between bits 51:11; that holds true for current CPUs, but isn't required by AMD's architecture: In some implementations, the bit used may be a physical address bit Key word being "may". Opportunistically use the GENMASK_ULL() version for AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK, which is far more readable than a set of repeating Fs. Tested-by: Sairaj Kodilkar Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) --- arch/x86/include/asm/svm.h | 4 +--- arch/x86/kvm/svm/avic.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 89a666952b01..36f67c69ea66 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -253,7 +253,7 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) =20 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) -#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) +#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12) #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) @@ -288,8 +288,6 @@ enum avic_ipi_failure_cause { static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D=3D= AVIC_MAX_PHYSICAL_ID); static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D= =3D X2AVIC_MAX_PHYSICAL_ID); =20 -#define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) - #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0) #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 5344ae76c590..4b882148f2c0 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -241,9 +241,9 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *= vmcb) phys_addr_t lpa =3D __sme_set(page_to_phys(kvm_svm->avic_logical_id_table= _page)); phys_addr_t ppa =3D __sme_set(page_to_phys(kvm_svm->avic_physical_id_tabl= e_page)); =20 - vmcb->control.avic_backing_page =3D bpa & AVIC_HPA_MASK; - vmcb->control.avic_logical_id =3D lpa & AVIC_HPA_MASK; - vmcb->control.avic_physical_id =3D ppa & AVIC_HPA_MASK; + vmcb->control.avic_backing_page =3D bpa; + vmcb->control.avic_logical_id =3D lpa; + vmcb->control.avic_physical_id =3D ppa; vmcb->control.avic_vapic_bar =3D APIC_DEFAULT_PHYS_BASE; =20 if (kvm_apicv_activated(svm->vcpu.kvm)) @@ -301,9 +301,12 @@ static int avic_init_backing_page(struct kvm_vcpu *vcp= u) if (!entry) return -EINVAL; =20 - new_entry =3D __sme_set((page_to_phys(svm->avic_backing_page) & - AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | - AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); + /* Note, fls64() returns the bit position, +1. */ + BUILD_BUG_ON(__PHYSICAL_MASK_SHIFT > + fls64(AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK)); + + new_entry =3D __sme_set(page_to_phys(svm->avic_backing_page)) | + AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(*entry, new_entry); =20 svm->avic_physical_id_cache =3D entry; @@ -903,8 +906,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, enable_remapped_mode =3D false; =20 /* Try to enable guest_mode in IRTE */ - pi.base =3D __sme_set(page_to_phys(svm->avic_backing_page) & - AVIC_HPA_MASK); + pi.base =3D __sme_set(page_to_phys(svm->avic_backing_page)); pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, svm->vcpu.vcpu_id); pi.is_guest_mode =3D true; --=20 2.50.0.rc1.591.g9c95f17f64-goog