From nobody Fri Oct 3 20:25:50 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2676824DCE4 for ; Wed, 11 Jun 2025 21:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749677773; cv=none; b=tk25PwrqsGKLEq/3vWN6D+r4sRf8bUTUdf/xUCbPyJeNgaxRJ94d2vepw0kq4XEULMppu3c4oPgtxdCT5xohQId1Fpd/1JMUGIIOY9H6PPDZSm3wQfjl4jlIe2Za4hL9G4/bXCKNhwUXb+rTEai/M+hWp2GFFl0794oD7P3IdFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749677773; c=relaxed/simple; bh=rgEWFRNx9AOzae/hY5m5+rHU8BL+ZKgpKWt+nqQu+9M=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=lCkhd+tCVoIjpXWhsvvEtF9hZCsEievu4RnGfOvst/5mewBJUS5MZMSE9gcLqX+fetX8YtO9MyEt0uLYiv/frZzfWYDgVpVagPe9C/sz0qWC4eEEBNaAe9ZLJZX2Ogg5Evb/QnUwAbdbw4MbXMvDhAPbk3v9b011aqYBC5afsx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=vOaZWIud; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="vOaZWIud" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-747d143117eso224855b3a.3 for ; Wed, 11 Jun 2025 14:36:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1749677771; x=1750282571; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=btr0cphDsMq+/yUhHVR8RE1UTj6gq99THk7CUF4LA9c=; b=vOaZWIudYIMGyMoh3vqNil8JDEeQfOG28mWLwxRjo/c+Z3TqMRJM91P5lCw3/6PdXK C7sRbvJJk99OqnDGVo3NmNKns9q29uDhJ7RP5j7wLc7MVrEGfuNyJYUG1Ci0yy3tkElD gXfPhXD6sS/uXjbdWTg6Zx7j9jJUA3hhasEpg7gUWMO2bEZhxxEJdxbi/K7wGA21rudx 8utetzuoze8s9TCikfc80vQO2QkUXX9MBxuLY3QXn1IHT5OLMtRA0e/ev+86QYKeQYCV +WkG6PMF3OMMMYEfDuDCoR3vuwiIlXsMPO1tuOkxtJ7XNBWS8vEa4BbHtLgQYe6DwRZK 9DAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749677771; x=1750282571; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=btr0cphDsMq+/yUhHVR8RE1UTj6gq99THk7CUF4LA9c=; b=CxXAHk/qhfnhcwWn/0ciTMniLLav+xJuc+RJ9JhZpU6PXzmzk4pv7CvLQ2NKBtEIda AXm3kfHqgsHzL8Dt5WCYOpxWkR2AeWqmhHXNknF5L5lS7roVO2DEgRM6DUDEeWBrB6wF P6vaGEVLhGe/47QhVZCVFVZgaahuZEjCLtUWA7E0y7MAwC1fV7emS4g9f/XIWzLUUCF2 TjwCNGrUyNqmGaoln6JNQXtpPbkrxInLicBrl06Vsw/7vIuesDasm6YI2r3uXDb1jKwc Ru+rLoqb981gPLufjoF6pkBHZ6kUNk8Ij922Qq67ux+DXtGmT/cv/X2U4pVoItYCrv0D XdXQ== X-Forwarded-Encrypted: i=1; AJvYcCUp5mBi5xMU+iq6klk7ZTMTJYBuYcm1vGR00XH5Kc5WmlcrB+qXkKcWa51kI22S/rFt6q7mrzdrqQ75cxU=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9ANoMvqu/K6QSLs9ePO1t/fE4joHBnAmi1nv3VgNBFiqJNrkI EhqgSiaBG7VdyzAcKEZCoGwh1OE3Vqp4n2jLG11JGFtlmIsL62Gc7XZQvWL5EiNB8jKRKLim9N+ 3rw+cnA== X-Google-Smtp-Source: AGHT+IFsPfyLnlFkwEO+3G76q5pk5GAKqTVHEuqReQsV0DBZ81IuIEqthkXBqU0MXTWDMH0fmDduzmsim6M= X-Received: from pfwp55.prod.google.com ([2002:a05:6a00:26f7:b0:746:2a27:3025]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:ad2:b0:742:a5f2:9c51 with SMTP id d2e1a72fcca58-7487e288d11mr630129b3a.16.1749677771627; Wed, 11 Jun 2025 14:36:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 11 Jun 2025 14:35:45 -0700 In-Reply-To: <20250611213557.294358-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250611213557.294358-1-seanjc@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250611213557.294358-7-seanjc@google.com> Subject: [PATCH v2 06/18] KVM: x86: Move KVM_{GET,SET}_IRQCHIP ioctl helpers to irq.c From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Vitaly Kuznetsov Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kai Huang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the ioctl helpers for getting/setting fully in-kernel IRQ chip state to irq.c, partly to trim down x86.c, but mostly in preparation for adding a Kconfig to control support for in-kernel I/O APIC, PIC, and PIT emulation. No functional change intended. Signed-off-by: Sean Christopherson Acked-by: Kai Huang --- arch/x86/kvm/irq.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/irq.h | 3 +++ arch/x86/kvm/x86.c | 55 --------------------------------------------- 3 files changed, 59 insertions(+), 55 deletions(-) diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c index 97d68d837929..da47e2165389 100644 --- a/arch/x86/kvm/irq.c +++ b/arch/x86/kvm/irq.c @@ -12,6 +12,7 @@ #include #include =20 +#include "ioapic.h" #include "irq.h" #include "i8254.h" #include "x86.h" @@ -178,3 +179,58 @@ bool kvm_arch_irqchip_in_kernel(struct kvm *kvm) { return irqchip_in_kernel(kvm); } + +int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) +{ + struct kvm_pic *pic =3D kvm->arch.vpic; + int r; + + r =3D 0; + switch (chip->chip_id) { + case KVM_IRQCHIP_PIC_MASTER: + memcpy(&chip->chip.pic, &pic->pics[0], + sizeof(struct kvm_pic_state)); + break; + case KVM_IRQCHIP_PIC_SLAVE: + memcpy(&chip->chip.pic, &pic->pics[1], + sizeof(struct kvm_pic_state)); + break; + case KVM_IRQCHIP_IOAPIC: + kvm_get_ioapic(kvm, &chip->chip.ioapic); + break; + default: + r =3D -EINVAL; + break; + } + return r; +} + +int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) +{ + struct kvm_pic *pic =3D kvm->arch.vpic; + int r; + + r =3D 0; + switch (chip->chip_id) { + case KVM_IRQCHIP_PIC_MASTER: + spin_lock(&pic->lock); + memcpy(&pic->pics[0], &chip->chip.pic, + sizeof(struct kvm_pic_state)); + spin_unlock(&pic->lock); + break; + case KVM_IRQCHIP_PIC_SLAVE: + spin_lock(&pic->lock); + memcpy(&pic->pics[1], &chip->chip.pic, + sizeof(struct kvm_pic_state)); + spin_unlock(&pic->lock); + break; + case KVM_IRQCHIP_IOAPIC: + kvm_set_ioapic(kvm, &chip->chip.ioapic); + break; + default: + r =3D -EINVAL; + break; + } + kvm_pic_update_irq(pic); + return r; +} diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h index 33dd5666b656..aa77a6b2828c 100644 --- a/arch/x86/kvm/irq.h +++ b/arch/x86/kvm/irq.h @@ -66,6 +66,9 @@ void kvm_pic_update_irq(struct kvm_pic *s); int kvm_pic_set_irq(struct kvm_kernel_irq_routing_entry *e, struct kvm *kv= m, int irq_source_id, int level, bool line_status); =20 +int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip); +int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip); + static inline int irqchip_split(struct kvm *kvm) { int mode =3D kvm->arch.irqchip_mode; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 50e9fa57b859..311a670b6652 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6395,61 +6395,6 @@ static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm = *kvm, return 0; } =20 -static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *c= hip) -{ - struct kvm_pic *pic =3D kvm->arch.vpic; - int r; - - r =3D 0; - switch (chip->chip_id) { - case KVM_IRQCHIP_PIC_MASTER: - memcpy(&chip->chip.pic, &pic->pics[0], - sizeof(struct kvm_pic_state)); - break; - case KVM_IRQCHIP_PIC_SLAVE: - memcpy(&chip->chip.pic, &pic->pics[1], - sizeof(struct kvm_pic_state)); - break; - case KVM_IRQCHIP_IOAPIC: - kvm_get_ioapic(kvm, &chip->chip.ioapic); - break; - default: - r =3D -EINVAL; - break; - } - return r; -} - -static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *c= hip) -{ - struct kvm_pic *pic =3D kvm->arch.vpic; - int r; - - r =3D 0; - switch (chip->chip_id) { - case KVM_IRQCHIP_PIC_MASTER: - spin_lock(&pic->lock); - memcpy(&pic->pics[0], &chip->chip.pic, - sizeof(struct kvm_pic_state)); - spin_unlock(&pic->lock); - break; - case KVM_IRQCHIP_PIC_SLAVE: - spin_lock(&pic->lock); - memcpy(&pic->pics[1], &chip->chip.pic, - sizeof(struct kvm_pic_state)); - spin_unlock(&pic->lock); - break; - case KVM_IRQCHIP_IOAPIC: - kvm_set_ioapic(kvm, &chip->chip.ioapic); - break; - default: - r =3D -EINVAL; - break; - } - kvm_pic_update_irq(pic); - return r; -} - void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *mems= lot) { =20 --=20 2.50.0.rc1.591.g9c95f17f64-goog