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Wed, 11 Jun 2025 11:45:15 -0400 (EDT) From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= To: Mauro Carvalho Chehab , Geert Uytterhoeven , Sakari Ailus , Tomi Valkeinen , Laurent Pinchart , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Laurent Pinchart Subject: [PATCH v3 1/4] media: rcar-csi2: Clarify usage of mbps and msps Date: Wed, 11 Jun 2025 17:44:42 +0200 Message-ID: <20250611154445.123412-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> References: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The helper function to deal with calculating the link speed is designed in such a way that it returns the correct type bps (bits per second) for D-PHY and sps (symbols per second) for C-PHY. And for historical reasons the function kept the name mbps. This is confusing, fix it by having the function only deal with bps values as this is the most common use-case and convert bps to sps in the only function where it is needed to configure the C-PHY. Signed-off-by: Niklas S=C3=B6derlund Tested-by: Tomi Valkeinen Reviewed-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/media/platform/renesas/rcar-csi2.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/pla= tform/renesas/rcar-csi2.c index 9979de4f6ef1..358e7470befc 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -975,10 +975,6 @@ static int rcsi2_calc_mbps(struct rcar_csi2 *priv, uns= igned int bpp, =20 mbps =3D div_u64(freq * 2, MEGA); =20 - /* Adjust for C-PHY, divide by 2.8. */ - if (priv->cphy) - mbps =3D div_u64(mbps * 5, 14); - return mbps; } =20 @@ -1203,9 +1199,13 @@ static int rcsi2_wait_phy_start_v4h(struct rcar_csi2= *priv, u32 match) return -ETIMEDOUT; } =20 -static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps) +static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) { const struct rcsi2_cphy_setting *conf; + int msps; + + /* Adjust for C-PHY symbols, divide by 2.8. */ + msps =3D div_u64(mbps * 5, 14); =20 for (conf =3D cphy_setting_table_r8a779g0; conf->msps !=3D 0; conf++) { if (conf->msps > msps) @@ -1301,7 +1301,7 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 = *priv, const struct rcar_csi2_format *format; const struct v4l2_mbus_framefmt *fmt; unsigned int lanes; - int msps; + int mbps; int ret; =20 /* Use the format on the sink pad to compute the receiver config. */ @@ -1314,9 +1314,9 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 = *priv, if (ret) return ret; =20 - msps =3D rcsi2_calc_mbps(priv, format->bpp, lanes); - if (msps < 0) - return msps; + mbps =3D rcsi2_calc_mbps(priv, format->bpp, lanes); + if (mbps < 0) + return mbps; =20 /* Reset LINK and PHY*/ rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); @@ -1352,7 +1352,7 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 = *priv, rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); =20 /* C-PHY settings */ - ret =3D rcsi2_c_phy_setting_v4h(priv, msps); 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Wed, 11 Jun 2025 11:45:18 -0400 (EDT) From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= To: Mauro Carvalho Chehab , Geert Uytterhoeven , Sakari Ailus , Tomi Valkeinen , Laurent Pinchart , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Laurent Pinchart Subject: [PATCH v3 2/4] media: rcar-csi2: Rework macros to access AFE lanes Date: Wed, 11 Jun 2025 17:44:43 +0200 Message-ID: <20250611154445.123412-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> References: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Each AFE lane has a set of control and offset registers. The registers themself are undocumented but later datasheets program more of them with magic values. Before exploding the driver with more defines to name them all rework the AFE ones to be able to address all controls and offsets. Also move a stray define that is out of sequence. There is no functional change. Signed-off-by: Niklas S=C3=B6derlund Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- * Changes since v2 - Improve spelling in commit message. * Changes since v1 - Adjust line length. --- drivers/media/platform/renesas/rcar-csi2.c | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/pla= tform/renesas/rcar-csi2.c index 358e7470befc..cdd358b4a973 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -177,15 +177,14 @@ struct rcar_csi2; #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 =20 /* V4H CORE registers */ -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2= )) /* n =3D 0 - 15 */ -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2= )) /* n =3D 0 - 15 */ -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2= )) /* n =3D 0 - 15 */ -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2= )) /* n =3D 0 - 15 */ -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2= )) /* n =3D 0 - 15 */ + +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0x22040 + ((l) = * 0x400) + ((n) * 2)) +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0x22060 + ((l) = * 0x400) + ((n) * 2)) +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0x22080 + ((l) = * 0x400) + ((n) * 2)) + #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) = /* n =3D 0 - 11 */ #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n =3D 0 -= 15 */ #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)= ) /* n =3D 0 - 3 */ -#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c =20 /* V4H C-PHY */ #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n =3D 0 - = 3 */ @@ -197,6 +196,7 @@ struct rcar_csi2; #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = =3D 0 - 6 */ +#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = =3D 0 - 6 */ @@ -1246,11 +1246,11 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2= *priv, int mbps) rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2); rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2); =20 - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x000= 1); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x000= 1); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x000= 1); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x= 0001); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x= 0001); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x= 0001); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0); =20 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); @@ -1267,13 +1267,13 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2= *priv, int mbps) /* Configure data line order. */ rsci2_set_line_order(priv, priv->line_orders[0], V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG, - V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9)); + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9)); rsci2_set_line_order(priv, priv->line_orders[1], V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, - V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(9)); + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 9)); 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Wed, 11 Jun 2025 11:45:20 -0400 (EDT) From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= To: Mauro Carvalho Chehab , Geert Uytterhoeven , Sakari Ailus , Tomi Valkeinen , Laurent Pinchart , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Laurent Pinchart Subject: [PATCH v3 3/4] media: rcar-csi2: Update start procedure for V4H Date: Wed, 11 Jun 2025 17:44:44 +0200 Message-ID: <20250611154445.123412-4-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> References: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Prepare for adding D-PHY support to the driver by first updating the generic startup procedure that covers both C-PHY and D-PHY operations. The starting procedure where updated in later versions of the datasheet. Most of the configuration is only documented as tables of magic values in the documentation. Each step is however marked with a T marker, inject these markers in the comments to make it easier to map driver to documentation. Signed-off-by: Niklas S=C3=B6derlund Tested-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/media/platform/renesas/rcar-csi2.c | 84 +++++++++++++++------- 1 file changed, 58 insertions(+), 26 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/pla= tform/renesas/rcar-csi2.c index cdd358b4a973..7ba637d8683b 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -1199,7 +1199,8 @@ static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 = *priv, u32 match) return -ETIMEDOUT; } =20 -static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) +static const struct rcsi2_cphy_setting * +rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) { const struct rcsi2_cphy_setting *conf; int msps; @@ -1214,7 +1215,7 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *= priv, int mbps) =20 if (!conf->msps) { dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", m= sps); - return -ERANGE; + return NULL; } =20 /* C-PHY specific */ @@ -1278,27 +1279,14 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2= *priv, int mbps) /* TODO: This registers is not documented. */ rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); =20 - /* Leave Shutdown mode */ - rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); - rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); - - /* Wait for calibration */ - if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { - dev_err(priv->dev, "PHY calibration failed\n"); - return -ETIMEDOUT; - } - - /* C-PHY setting - analog programing*/ - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9), co= nf->lane29); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 7), co= nf->lane27); - - return 0; + return conf; } =20 static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { const struct rcar_csi2_format *format; + const struct rcsi2_cphy_setting *cphy; const struct v4l2_mbus_framefmt *fmt; unsigned int lanes; int mbps; @@ -1318,24 +1306,35 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi= 2 *priv, if (mbps < 0) return mbps; =20 - /* Reset LINK and PHY*/ + /* T0: Reset LINK and PHY*/ rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); =20 - /* PHY static setting */ - rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); + /* T1: PHY static setting */ + rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | + V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | + V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); rcsi2_write(priv, V4H_FLDC_REG, 0); rcsi2_write(priv, V4H_FLDD_REG, 0); rcsi2_write(priv, V4H_IDIC_REG, 0); rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); =20 - /* Reset CSI2 */ + rcsi2_write(priv, V4M_FRXM_REG, + V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | + V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); + rcsi2_write(priv, V4M_OVR1_REG, + V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | + V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); + + /* T2: Reset CSI2 */ rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); =20 /* Registers static setting through APB */ /* Common setting */ + rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(10), 0x0030); + rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(2), 0x1444= ); rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd= ); rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); @@ -1350,15 +1349,48 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi= 2 *priv, rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(1), 0x0400); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x41f6); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(0), 0x0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(3), 0x43f6); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x3000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x7000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(7), 0x0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(5), 0x4000); =20 - /* C-PHY settings */ - ret =3D rcsi2_c_phy_setting_v4h(priv, mbps); - if (ret) - return ret; + /* T3: PHY settings */ + cphy =3D rcsi2_c_phy_setting_v4h(priv, mbps); + if (!cphy) + return -ERANGE; =20 + /* T4: Leave Shutdown mode */ + rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); + rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); + + /* T5: Wait for calibration */ + if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { + dev_err(priv->dev, "PHY calibration failed\n"); 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Wed, 11 Jun 2025 11:45:22 -0400 (EDT) From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= To: Mauro Carvalho Chehab , Geert Uytterhoeven , Sakari Ailus , Tomi Valkeinen , Laurent Pinchart , linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Subject: [PATCH v3 4/4] media: rcar-csi2: Add D-PHY support for V4H Date: Wed, 11 Jun 2025 17:44:45 +0200 Message-ID: <20250611154445.123412-5-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> References: <20250611154445.123412-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add D-PHY support for V4H in addition to the already support C-PHY support. The common start-up procedure for C-PHY and D-PHY are shared, only PHY setup differ. Extend the V4H setup with D-PHY support as documented in the datasheet (Rev.1.21). Most of the start-up procedure is only documented as magic values in tables, there is little documentation to make the settings more clear. Wherever possible formulas or lookup tables are used as they are documented in the datasheet. Signed-off-by: Niklas S=C3=B6derlund Tested-by: Tomi Valkeinen --- * Fixes since v2 - Stire DESKEW settings in an array and loop over it instead of opene coding it. * Fixes since v1 - Init cphy variables to not trigger false -Wmaybe-uninitialized warning. - Adjust line lengths. --- drivers/media/platform/renesas/rcar-csi2.c | 240 ++++++++++++++++++++- 1 file changed, 230 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/pla= tform/renesas/rcar-csi2.c index 7ba637d8683b..1fd36823c8e9 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -172,6 +172,7 @@ struct rcar_csi2; #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10 +#define V4H_PPI_RW_DDLCAL_CFG_n_REG(n) (0x21c40 + ((n) * 2)) /* n =3D 0 = - 7 */ #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 @@ -185,6 +186,13 @@ struct rcar_csi2; #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) = /* n =3D 0 - 11 */ #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n =3D 0 -= 15 */ #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)= ) /* n =3D 0 - 3 */ +#define V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG 0x23fe0 + +#define V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, n) (0x26000 + ((l) * 0x400) = + ((n) * 2)) +#define V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, n) (0x26080 + ((l) * 0x400) += ((n) * 2)) +#define V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, n) (0x26100 + ((l) * 0x400)= + ((n) * 2)) +#define V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_LP_= n_REG(4, (n)) +#define V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_H= S_RX_n_REG(4, (n)) =20 /* V4H C-PHY */ #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n =3D 0 - = 3 */ @@ -1282,11 +1290,203 @@ rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, in= t mbps) return conf; } =20 +struct rcsi2_d_phy_setting_v4h_lut_value { + unsigned int mbps; + unsigned char cfg_1; + unsigned char cfg_5_94; + unsigned char cfg_5_30; + unsigned char lane_ctrl_2_8; + unsigned char rw_hs_rx_3_83; + unsigned char rw_hs_rx_3_20; + unsigned char rw_hs_rx_6; + unsigned char rw_hs_rx_1; +}; + +static const struct rcsi2_d_phy_setting_v4h_lut_value * +rcsi2_d_phy_setting_v4h_lut_lookup(int mbps) +{ + static const struct rcsi2_d_phy_setting_v4h_lut_value values[] =3D { + { 4500, 0x3f, 0x07, 0x00, 0x01, 0x02, 0x01, 0x0d, 0x10 }, + { 4000, 0x47, 0x08, 0x01, 0x01, 0x05, 0x01, 0x0f, 0x0d }, + { 3600, 0x4f, 0x09, 0x01, 0x01, 0x06, 0x01, 0x10, 0x0b }, + { 3230, 0x57, 0x0a, 0x01, 0x01, 0x06, 0x01, 0x12, 0x09 }, + { 3000, 0x47, 0x08, 0x00, 0x00, 0x03, 0x01, 0x0f, 0x0c }, + { 2700, 0x4f, 0x09, 0x01, 0x00, 0x06, 0x01, 0x10, 0x0b }, + { 2455, 0x57, 0x0a, 0x01, 0x00, 0x06, 0x01, 0x12, 0x09 }, + { 2250, 0x5f, 0x0b, 0x01, 0x00, 0x08, 0x01, 0x13, 0x08 }, + { 2077, 0x67, 0x0c, 0x01, 0x00, 0x06, 0x02, 0x15, 0x0d }, + { 1929, 0x6f, 0x0d, 0x02, 0x00, 0x06, 0x02, 0x17, 0x0d }, + { 1800, 0x77, 0x0e, 0x02, 0x00, 0x06, 0x02, 0x18, 0x0d }, + { 1688, 0x7f, 0x0f, 0x02, 0x00, 0x08, 0x02, 0x1a, 0x0d }, + { 1588, 0x87, 0x10, 0x02, 0x00, 0x08, 0x02, 0x1b, 0x0d }, + { 1500, 0x8f, 0x11, 0x03, 0x00, 0x08, 0x02, 0x1d, 0x0c }, + }; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(values); i++) + if (values[i].mbps >=3D mbps) + return &values[i]; + + return NULL; +} + +static int rcsi2_d_phy_setting_v4h(struct rcar_csi2 *priv, int mbps) +{ + const struct rcsi2_d_phy_setting_v4h_lut_value *lut =3D + rcsi2_d_phy_setting_v4h_lut_lookup(mbps); + u16 val; + + rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0000); + rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), mbps > 1500 ? = 0x0028 : 0x0068); + rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0050); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(0), 0x0063); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1132); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), 0x1340); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(2), 0x4b13); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(4), 0x000a); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(6), 0x800a); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(7), 0x1109); + + if (mbps > 1500) { + val =3D roundup(5 * mbps / 64, 1); + rcsi2_write16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(3), val); + } + + if (lut) { + rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(1), + lut->cfg_1, 0x00ff); + rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), + lut->cfg_5_94 << 4, 0x03f0); + rcsi2_modify16(priv, V4H_PPI_RW_DDLCAL_CFG_n_REG(5), + lut->cfg_5_30 << 0, 0x000f); + + for (unsigned int l =3D 0; l < 5; l++) + rcsi2_modify16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 8), + lut->lane_ctrl_2_8 << 12, 0x1000); + } + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x463c); + + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x= 0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0x= 0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x= 0001); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x= 0000); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0x= 0000); + + rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(6), 0x0009); + + val =3D mbps > 1500 ? 0x0800 : 0x0802; + for (unsigned int l =3D 0; l < 5; l++) + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 12), = val); + + val =3D mbps > 1500 ? 0x0000 : 0x0002; + for (unsigned int l =3D 0; l < 5; l++) + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 13), = val); + + if (mbps >=3D 80) { + if (mbps >=3D 2560) + val =3D 6; + else if (mbps >=3D 1280) + val =3D 5; + else if (mbps >=3D 640) + val =3D 4; + else if (mbps >=3D 320) + val =3D 3; + else if (mbps >=3D 160) + val =3D 2; + else if (mbps >=3D 80) + val =3D 1; + + rcsi2_modify16(priv, + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9), + val << 5, 0xe0); + } + + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(0), 0x091c); + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(7), 0x3b06); + + val =3D roundup(1200 / mbps, 1) + 12; + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 0), val << 8= , 0xf0); + + val =3D mbps > 1500 ? 0x0004 : 0x0008; + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, 1), val); + + val =3D mbps > 2500 ? 0x669a : mbps > 1500 ? 0xe69a : 0xe69b; + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 2), val); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, 0), 0x163c); + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(0), 0x163c); + + if (lut) { + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 1), + lut->rw_hs_rx_1, 0xff); + } + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), 0x9209); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 4), 0x0096); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 5), 0x0100); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), 0x2d02); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_write16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 7), 0x1b06); + + if (lut) { + /* Documentation LUT have two values but document writing both + * values in a single write. + */ + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 3), + lut->rw_hs_rx_3_83 << 3 | lut->rw_hs_rx_3_20, 0x1ff); + + for (unsigned int l =3D 0; l < 4; l++) + rcsi2_modify16(priv, V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, 6), + lut->rw_hs_rx_6 << 8, 0xff00); + } + + static const u16 deskew_fine[] =3D { + 0x0404, 0x040c, 0x0414, 0x041c, 0x0423, 0x0429, 0x0430, 0x043a, + 0x0445, 0x044a, 0x0450, 0x045a, 0x0465, 0x0469, 0x0472, 0x047a, + 0x0485, 0x0489, 0x0490, 0x049a, 0x04a4, 0x04ac, 0x04b4, 0x04bc, + 0x04c4, 0x04cc, 0x04d4, 0x04dc, 0x04e4, 0x04ec, 0x04f4, 0x04fc, + 0x0504, 0x050c, 0x0514, 0x051c, 0x0523, 0x0529, 0x0530, 0x053a, + 0x0545, 0x054a, 0x0550, 0x055a, 0x0565, 0x0569, 0x0572, 0x057a, + 0x0585, 0x0589, 0x0590, 0x059a, 0x05a4, 0x05ac, 0x05b4, 0x05bc, + 0x05c4, 0x05cc, 0x05d4, 0x05dc, 0x05e4, 0x05ec, 0x05f4, 0x05fc, + 0x0604, 0x060c, 0x0614, 0x061c, 0x0623, 0x0629, 0x0632, 0x063a, + 0x0645, 0x064a, 0x0650, 0x065a, 0x0665, 0x0669, 0x0672, 0x067a, + 0x0685, 0x0689, 0x0690, 0x069a, 0x06a4, 0x06ac, 0x06b4, 0x06bc, + 0x06c4, 0x06cc, 0x06d4, 0x06dc, 0x06e4, 0x06ec, 0x06f4, 0x06fc, + 0x0704, 0x070c, 0x0714, 0x071c, 0x0723, 0x072a, 0x0730, 0x073a, + 0x0745, 0x074a, 0x0750, 0x075a, 0x0765, 0x0769, 0x0772, 0x077a, + 0x0785, 0x0789, 0x0790, 0x079a, 0x07a4, 0x07ac, 0x07b4, 0x07bc, + 0x07c4, 0x07cc, 0x07d4, 0x07dc, 0x07e4, 0x07ec, 0x07f4, 0x07fc, + }; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(deskew_fine); i++) { + rcsi2_write16(priv, V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG, + deskew_fine[i]); + } + + return 0; +} + static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { + const struct rcsi2_cphy_setting *cphy =3D NULL; const struct rcar_csi2_format *format; - const struct rcsi2_cphy_setting *cphy; const struct v4l2_mbus_framefmt *fmt; unsigned int lanes; int mbps; @@ -1318,7 +1518,8 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 = *priv, rcsi2_write(priv, V4H_FLDC_REG, 0); rcsi2_write(priv, V4H_FLDD_REG, 0); rcsi2_write(priv, V4H_IDIC_REG, 0); - rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); + rcsi2_write(priv, V4H_PHY_MODE_REG, + priv->cphy ? V4H_PHY_MODE_CPHY : V4H_PHY_MODE_DPHY); rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); =20 rcsi2_write(priv, V4M_FRXM_REG, @@ -1361,9 +1562,15 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2= *priv, rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(5), 0x4000); =20 /* T3: PHY settings */ - cphy =3D rcsi2_c_phy_setting_v4h(priv, mbps); - if (!cphy) - return -ERANGE; + if (priv->cphy) { + cphy =3D rcsi2_c_phy_setting_v4h(priv, mbps); + if (!cphy) + return -ERANGE; + } else { + ret =3D rcsi2_d_phy_setting_v4h(priv, mbps); + if (ret) + return ret; + } =20 /* T4: Leave Shutdown mode */ rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); @@ -1376,11 +1583,23 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi= 2 *priv, } =20 /* T6: Analog programming */ - for (unsigned int l =3D 0; l < 3; l++) { - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), - cphy->lane29); - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 7), - cphy->lane27); + if (priv->cphy) { + for (unsigned int l =3D 0; l < 3; l++) { + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), + cphy->lane29); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 7), + cphy->lane27); + } + } else { + u16 val_2_9 =3D mbps > 2500 ? 0x14 : mbps > 1500 ? 0x04 : 0x00; + u16 val_2_15 =3D mbps > 1500 ? 0x03 : 0x00; + + for (unsigned int l =3D 0; l < 5; l++) { + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 9), + val_2_9); + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, 15), + val_2_15); + } } =20 /* T7: Wait for stop state */ @@ -2245,6 +2464,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a= 779g0 =3D { .start_receiver =3D rcsi2_start_receiver_v4h, .use_isp =3D true, .support_cphy =3D true, + .support_dphy =3D true, }; =20 static const struct rcsi2_register_layout rcsi2_registers_v4m =3D { --=20 2.49.0