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Wed, 11 Jun 2025 05:59:21 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 1/8] dt-bindings: dma: marvell,mmp-dma: Add SpacemiT PDMA compatibility Date: Wed, 11 Jun 2025 20:57:16 +0800 Message-ID: <20250611125723.181711-2-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add "spacemit,pdma-1.0" compatible string to support SpacemiT PDMA controller in the Marvell MMP DMA device tree bindings. This enables: - Support for SpacemiT PDMA controller configuration - New optional properties for platform-specific integration: * clocks: Clock controller for the DMA * resets: Reset controller for the DMA Also, add explicit #dma-cells property definition to avoid "make dtbs_check W=3D3" warnings about unevaluated properties. The #dma-cells property is defined as 2 cells to maintain compatibility with existing ARM device trees. The first cell specifies the DMA request line number, while the second cell is currently unused by the driver but required for backward compatibility with PXA device tree files. Signed-off-by: Guodong Xu --- .../bindings/dma/marvell,mmp-dma.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml b/D= ocumentation/devicetree/bindings/dma/marvell,mmp-dma.yaml index d447d5207be0..e117a81414bd 100644 --- a/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml +++ b/Documentation/devicetree/bindings/dma/marvell,mmp-dma.yaml @@ -18,6 +18,7 @@ properties: - marvell,pdma-1.0 - marvell,adma-1.0 - marvell,pxa910-squ + - spacemit,pdma-1.0 =20 reg: maxItems: 1 @@ -32,6 +33,21 @@ properties: A phandle to the SRAM pool $ref: /schemas/types.yaml#/definitions/phandle =20 + clocks: + description: Clock for the controller + maxItems: 1 + + resets: + description: Reset controller for the DMA controller + maxItems: 1 + + '#dma-cells': + const: 2 + description: + The first cell contains the DMA request number for the peripheral + device. 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charset="utf-8" Add support for retrieving and enabling an optional clock using devm_clk_get_optional_enabled() during mmp_pdma_probe(). Signed-off-by: Guodong Xu --- drivers/dma/mmp_pdma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index a95d31103d30..4a6dbf558237 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 @@ -1019,6 +1020,7 @@ static int mmp_pdma_probe(struct platform_device *op) { struct mmp_pdma_device *pdev; struct mmp_dma_platdata *pdata =3D dev_get_platdata(&op->dev); + struct clk *clk; int i, ret, irq =3D 0; int dma_channels =3D 0, irq_num =3D 0; const enum dma_slave_buswidth widths =3D @@ -1037,6 +1039,10 @@ static int mmp_pdma_probe(struct platform_device *op) if (IS_ERR(pdev->base)) return PTR_ERR(pdev->base); =20 + clk =3D devm_clk_get_optional_enabled(pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + if (pdev->dev->of_node) { /* Parse new and deprecated dma-channels properties */ if (of_property_read_u32(pdev->dev->of_node, "dma-channels", --=20 2.43.0 From nobody Sat Oct 11 04:11:29 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EF9B283CAA for ; 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charset="utf-8" Add support for hardware reset control in the MMP PDMA driver using the devm_reset_control_get_optional_exclusive_deasserted() API. The reset controller is retrieved without a specific reset name, allowing platforms to define a single default reset line for the PDMA controller. Signed-off-by: Guodong Xu --- drivers/dma/mmp_pdma.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index 4a6dbf558237..fe627efeaff0 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include =20 @@ -1021,6 +1022,7 @@ static int mmp_pdma_probe(struct platform_device *op) struct mmp_pdma_device *pdev; struct mmp_dma_platdata *pdata =3D dev_get_platdata(&op->dev); struct clk *clk; + struct reset_control *rst; int i, ret, irq =3D 0; int dma_channels =3D 0, irq_num =3D 0; const enum dma_slave_buswidth widths =3D @@ -1043,6 +1045,11 @@ static int mmp_pdma_probe(struct platform_device *op) if (IS_ERR(clk)) return PTR_ERR(clk); =20 + rst =3D devm_reset_control_get_optional_exclusive_deasserted(pdev->dev, + NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + if (pdev->dev->of_node) { /* Parse new and deprecated dma-channels properties */ if (of_property_read_u32(pdev->dev->of_node, "dma-channels", --=20 2.43.0 From nobody Sat Oct 11 04:11:29 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 158AE288C89 for ; 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Wed, 11 Jun 2025 06:00:08 -0700 (PDT) Received: from localhost.localdomain ([2409:8a00:31a4:6520:3d67:ceb1:7c60:9098]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236030925e3sm86984115ad.53.2025.06.11.05.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 06:00:07 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 4/8] dma: mmp_pdma: Add SpacemiT PDMA support with 64-bit addressing Date: Wed, 11 Jun 2025 20:57:19 +0800 Message-ID: <20250611125723.181711-5-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the MMP PDMA driver to support SpacemiT PDMA controllers with 64-bit physical addressing capabilities, as used in the K1 SoC. This change introduces a flexible architecture that maintains compatibility with existing 32-bit Marvell platforms while adding 64-bit support. Key changes: - Add struct mmp_pdma_config to abstract platform-specific behaviors - Implement 64-bit address support through: * New high address registers (DDADRH, DSADRH, DTADRH) * DCSR_LPAEEN bit for Long Physical Address Extension mode * Helper functions for 32/64-bit address handling - Add "spacemit,pdma-1.0" compatible string with associated config - Extend descriptor structure to support 64-bit addresses - Refactor address handling code to be platform-agnostic - Add proper DMA mask configuration for both 32-bit and 64-bit modes The implementation uses a configuration-based approach to keeps all platform-specific code isolated in config structures. It maintains clean separation between 32-bit and 64-bit code paths, provides consistent API for both addressing modes and preserves backward compatibility. Signed-off-by: Guodong Xu --- drivers/dma/mmp_pdma.c | 236 +++++++++++++++++++++++++++++++++++------ 1 file changed, 205 insertions(+), 31 deletions(-) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index fe627efeaff0..57313754b611 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -25,9 +25,12 @@ #define DCSR 0x0000 #define DALGN 0x00a0 #define DINT 0x00f0 -#define DDADR 0x0200 +#define DDADR(n) (0x0200 + ((n) << 4)) #define DSADR(n) (0x0204 + ((n) << 4)) #define DTADR(n) (0x0208 + ((n) << 4)) +#define DDADRH(n) (0x0300 + ((n) << 4)) +#define DSADRH(n) (0x0304 + ((n) << 4)) +#define DTADRH(n) (0x0308 + ((n) << 4)) #define DCMD 0x020c =20 #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ @@ -44,6 +47,7 @@ #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ +#define DCSR_LPAEEN BIT(21) /* Long Physical Address Extension Enable */ #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ #define DCSR_EORINTR BIT(9) /* The end of Receive */ =20 @@ -76,6 +80,16 @@ struct mmp_pdma_desc_hw { u32 dsadr; /* DSADR value for the current transfer */ u32 dtadr; /* DTADR value for the current transfer */ u32 dcmd; /* DCMD value for the current transfer */ + /* + * The following 32-bit words are only used in the 64-bit, ie. + * LPAE (Long Physical Address Extension) mode. + * They are used to specify the high 32 bits of the descriptor's + * addresses. + */ + u32 ddadrh; /* High 32-bit of DDADR */ + u32 dsadrh; /* High 32-bit of DSADR */ + u32 dtadrh; /* High 32-bit of DTADR */ + u32 rsvd; /* reserved */ } __aligned(32); =20 struct mmp_pdma_desc_sw { @@ -120,12 +134,36 @@ struct mmp_pdma_phy { struct mmp_pdma_chan *vchan; }; =20 +/** + * struct mmp_pdma_ops - Operations for the MMP PDMA controller + * @set_desc: Function to program descriptor addresses into DDADR/DDADRH + * channel registers + * @addr_split: Function to split DMA address into 32-bit low/high parts + * for hardware programming + * @addr_join: Function to combine 32-bit low/high values into 64-bit + * for software processing + * @reg_read64: Function to read and combine two 32-bit registers into + * 64-bit value + * @run_bits: Control bits in DCSR register for channel start/stop + * @dma_mask: DMA addressing capability of controller. 0 to use OF/platf= orm + * settings, or explicit mask like DMA_BIT_MASK(32/64) + */ +struct mmp_pdma_ops { + void (*set_desc)(struct mmp_pdma_phy *phy, dma_addr_t addr); + void (*addr_split)(u32 *lower, u32 *upper, dma_addr_t addr); + u64 (*addr_join)(u32 lower, u32 upper); + u64 (*reg_read64)(void __iomem *base, u32 low_offset, u32 high_offset); + u32 run_bits; + u64 dma_mask; +}; + struct mmp_pdma_device { int dma_channels; void __iomem *base; struct device *dev; struct dma_device device; struct mmp_pdma_phy *phy; + const struct mmp_pdma_ops *config; spinlock_t phy_lock; /* protect alloc/free phy channels */ }; =20 @@ -138,24 +176,89 @@ struct mmp_pdma_device { #define to_mmp_pdma_dev(dmadev) \ container_of(dmadev, struct mmp_pdma_device, device) =20 -static int mmp_pdma_config_write(struct dma_chan *dchan, - struct dma_slave_config *cfg, - enum dma_transfer_direction direction); +/* For 32-bit version */ +static void addr_split_32(u32 *lower, u32 *upper __maybe_unused, + dma_addr_t addr) +{ + *lower =3D addr; +} + +static void set_desc_32(struct mmp_pdma_phy *phy, dma_addr_t addr) +{ + writel(addr, phy->base + DDADR(phy->idx)); +} + +static u64 addr_join_32(u32 lower, u32 upper __maybe_unused) +{ + return lower; +} =20 -static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr) +static u64 reg_read64_32(void __iomem *base, u32 low_offset, + u32 high_offset __maybe_unused) { - u32 reg =3D (phy->idx << 4) + DDADR; + return readl(base + low_offset); +} =20 - writel(addr, phy->base + reg); +/* For 64-bit version */ +static void addr_split_64(u32 *lower, u32 *upper, dma_addr_t addr) +{ + *lower =3D lower_32_bits(addr); + *upper =3D upper_32_bits(addr); +} + +static void set_desc_64(struct mmp_pdma_phy *phy, dma_addr_t addr) +{ + writel(lower_32_bits(addr), phy->base + DDADR(phy->idx)); + writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx)); +} + +static u64 addr_join_64(u32 lower, u32 upper) +{ + return ((u64)upper << 32) | lower; +} + +static u64 reg_read64_64(void __iomem *base, u32 low_offset, + u32 high_offset) +{ + return addr_join_64(readl(base + low_offset), + readl(base + high_offset)); } =20 +/* Helper functions */ +static inline void pdma_desc_set_addr(struct mmp_pdma_device *pdev, + u32 *addr_low, u32 *addr_high, + dma_addr_t addr) +{ + pdev->config->addr_split(addr_low, addr_high, addr); +} + +static inline u64 pdma_read_addr(struct mmp_pdma_phy *phy, + struct mmp_pdma_device *pdev, + u32 reg_low, u32 reg_high) +{ + return pdev->config->reg_read64(phy->base, reg_low, reg_high); +} + +static inline u64 pdma_desc_addr(struct mmp_pdma_device *pdev, + u32 addr_low, u32 addr_high) +{ + return pdev->config->addr_join(addr_low, addr_high); +} + +static int mmp_pdma_config_write(struct dma_chan *dchan, + struct dma_slave_config *cfg, + enum dma_transfer_direction direction); + static void enable_chan(struct mmp_pdma_phy *phy) { u32 reg, dalgn; + struct mmp_pdma_device *pdev; =20 if (!phy->vchan) return; =20 + pdev =3D to_mmp_pdma_dev(phy->vchan->chan.device); + reg =3D DRCMR(phy->vchan->drcmr); writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); =20 @@ -167,18 +270,29 @@ static void enable_chan(struct mmp_pdma_phy *phy) writel(dalgn, phy->base + DALGN); =20 reg =3D (phy->idx << 2) + DCSR; - writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); + writel(readl(phy->base + reg) | pdev->config->run_bits, + phy->base + reg); } =20 static void disable_chan(struct mmp_pdma_phy *phy) { - u32 reg; + u32 reg, dcsr; =20 if (!phy) return; =20 reg =3D (phy->idx << 2) + DCSR; - writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); + dcsr =3D readl(phy->base + reg); + + if (phy->vchan) { + struct mmp_pdma_device *pdev; + + pdev =3D to_mmp_pdma_dev(phy->vchan->chan.device); + writel(dcsr & ~pdev->config->run_bits, phy->base + reg); + } else { + /* If no vchan, just clear the RUN bit */ + writel(dcsr & ~DCSR_RUN, phy->base + reg); + } } =20 static int clear_chan_irq(struct mmp_pdma_phy *phy) @@ -297,6 +411,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pch= an) static void start_pending_queue(struct mmp_pdma_chan *chan) { struct mmp_pdma_desc_sw *desc; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(chan->chan.device); =20 /* still in running, irq will start the pending list */ if (!chan->idle) { @@ -331,7 +446,7 @@ static void start_pending_queue(struct mmp_pdma_chan *c= han) * Program the descriptor's address into the DMA controller, * then start the DMA transaction */ - set_desc(chan->phy, desc->async_tx.phys); + pdev->config->set_desc(chan->phy, desc->async_tx.phys); enable_chan(chan->phy); chan->idle =3D false; } @@ -447,6 +562,7 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan, size_t len, unsigned long flags) { struct mmp_pdma_chan *chan; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(dchan->device); struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new; size_t copy =3D 0; =20 @@ -478,13 +594,17 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan, chan->byte_align =3D true; =20 new->desc.dcmd =3D chan->dcmd | (DCMD_LENGTH & copy); - new->desc.dsadr =3D dma_src; - new->desc.dtadr =3D dma_dst; + pdma_desc_set_addr(pdev, &new->desc.dsadr, &new->desc.dsadrh, + dma_src); + pdma_desc_set_addr(pdev, &new->desc.dtadr, &new->desc.dtadrh, + dma_dst); =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdma_desc_set_addr(pdev, &prev->desc.ddadr, + &prev->desc.ddadrh, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -528,6 +648,7 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct s= catterlist *sgl, unsigned long flags, void *context) { struct mmp_pdma_chan *chan =3D to_mmp_pdma_chan(dchan); + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(dchan->device); struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new =3D NULL; size_t len, avail; struct scatterlist *sg; @@ -559,17 +680,23 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct= scatterlist *sgl, =20 new->desc.dcmd =3D chan->dcmd | (DCMD_LENGTH & len); if (dir =3D=3D DMA_MEM_TO_DEV) { - new->desc.dsadr =3D addr; + pdma_desc_set_addr(pdev, &new->desc.dsadr, + &new->desc.dsadrh, + addr); new->desc.dtadr =3D chan->dev_addr; } else { new->desc.dsadr =3D chan->dev_addr; - new->desc.dtadr =3D addr; + pdma_desc_set_addr(pdev, &new->desc.dtadr, + &new->desc.dtadrh, + addr); } =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdma_desc_set_addr(pdev, &prev->desc.ddadr, + &prev->desc.ddadrh, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -609,6 +736,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, unsigned long flags) { struct mmp_pdma_chan *chan; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(dchan->device); struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new; dma_addr_t dma_src, dma_dst; =20 @@ -651,13 +779,17 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, =20 new->desc.dcmd =3D (chan->dcmd | DCMD_ENDIRQEN | (DCMD_LENGTH & period_len)); - new->desc.dsadr =3D dma_src; - new->desc.dtadr =3D dma_dst; + pdma_desc_set_addr(pdev, &new->desc.dsadr, &new->desc.dsadrh, + dma_src); + pdma_desc_set_addr(pdev, &new->desc.dtadr, &new->desc.dtadrh, + dma_dst); =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdma_desc_set_addr(pdev, &prev->desc.ddadr, + &prev->desc.ddadrh, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -678,7 +810,8 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, first->async_tx.cookie =3D -EBUSY; =20 /* make the cyclic link */ - new->desc.ddadr =3D first->async_tx.phys; + pdma_desc_set_addr(pdev, &new->desc.ddadr, &new->desc.ddadrh, + first->async_tx.phys); chan->cyclic_first =3D first; =20 return &first->async_tx; @@ -764,7 +897,9 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_ch= an *chan, dma_cookie_t cookie) { struct mmp_pdma_desc_sw *sw; - u32 curr, residue =3D 0; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(chan->chan.device); + u64 curr; + u32 residue =3D 0; bool passed =3D false; bool cyclic =3D chan->cyclic_first !=3D NULL; =20 @@ -776,17 +911,24 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_= chan *chan, return 0; =20 if (chan->dir =3D=3D DMA_DEV_TO_MEM) - curr =3D readl(chan->phy->base + DTADR(chan->phy->idx)); + curr =3D pdma_read_addr(chan->phy, pdev, + DTADR(chan->phy->idx), + DTADRH(chan->phy->idx)); else - curr =3D readl(chan->phy->base + DSADR(chan->phy->idx)); + curr =3D pdma_read_addr(chan->phy, pdev, + DSADR(chan->phy->idx), + DSADRH(chan->phy->idx)); =20 list_for_each_entry(sw, &chan->chain_running, node) { - u32 start, end, len; + u64 start, end; + u32 len; =20 if (chan->dir =3D=3D DMA_DEV_TO_MEM) - start =3D sw->desc.dtadr; + start =3D pdma_desc_addr(pdev, sw->desc.dtadr, + sw->desc.dtadrh); else - start =3D sw->desc.dsadr; + start =3D pdma_desc_addr(pdev, sw->desc.dsadr, + sw->desc.dsadrh); =20 len =3D sw->desc.dcmd & DCMD_LENGTH; end =3D start + len; @@ -802,7 +944,7 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_ch= an *chan, if (passed) { residue +=3D len; } else if (curr >=3D start && curr <=3D end) { - residue +=3D end - curr; + residue +=3D (u32)(end - curr); passed =3D true; } =20 @@ -996,9 +1138,34 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device = *pdev, int idx, int irq) return 0; } =20 +static const struct mmp_pdma_ops marvell_pdma_v1_config =3D { + .set_desc =3D set_desc_32, + .addr_split =3D addr_split_32, + .addr_join =3D addr_join_32, + .reg_read64 =3D reg_read64_32, + .run_bits =3D (DCSR_RUN), + .dma_mask =3D 0, /* let OF/platform set DMA mask */ +}; + +static const struct mmp_pdma_ops spacemit_k1_pdma_v1_config =3D { + .set_desc =3D set_desc_64, + .addr_split =3D addr_split_64, + .addr_join =3D addr_join_64, + .reg_read64 =3D reg_read64_64, + .run_bits =3D (DCSR_RUN | DCSR_LPAEEN), + .dma_mask =3D DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */ +}; + static const struct of_device_id mmp_pdma_dt_ids[] =3D { - { .compatible =3D "marvell,pdma-1.0", }, - {} + { + .compatible =3D "marvell,pdma-1.0", + .data =3D &marvell_pdma_v1_config + }, { + .compatible =3D "spacemit,pdma-1.0", + .data =3D &spacemit_k1_pdma_v1_config + }, { + /* sentinel */ + } }; MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids); =20 @@ -1050,6 +1217,10 @@ static int mmp_pdma_probe(struct platform_device *op) if (IS_ERR(rst)) return PTR_ERR(rst); =20 + pdev->config =3D of_device_get_match_data(&op->dev); + if (!pdev->config) + return -ENODEV; + if (pdev->dev->of_node) { /* Parse new and deprecated dma-channels properties */ if (of_property_read_u32(pdev->dev->of_node, "dma-channels", @@ -1111,7 +1282,10 @@ static int mmp_pdma_probe(struct platform_device *op) pdev->device.directions =3D BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); pdev->device.residue_granularity =3D DMA_RESIDUE_GRANULARITY_DESCRIPTOR; =20 - if (pdev->dev->coherent_dma_mask) + /* Set DMA mask based on config, or OF/platform */ + if (pdev->config->dma_mask) + dma_set_mask(pdev->dev, pdev->config->dma_mask); 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Wed, 11 Jun 2025 06:00:21 -0700 (PDT) Received: from localhost.localdomain ([2409:8a00:31a4:6520:3d67:ceb1:7c60:9098]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236030925e3sm86984115ad.53.2025.06.11.06.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 06:00:21 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 5/8] riscv: dts: spacemit: Add dma bus and PDMA node for K1 SoC Date: Wed, 11 Jun 2025 20:57:20 +0800 Message-ID: <20250611125723.181711-6-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reorganize the K1 SoC device tree to better reflect the hardware topology by introducing a dedicated dma_bus node that groups devices sharing the same address translation scheme. This change aligns with the actual hardware organization where devices are physically connected to different bus segments with different address translation characteristics. The changes include: - New dma_bus node with: * DMA address translation ranges: - First range: 0x0_00000000 -> 0x0_00000000 (size: 2GB) - Second range: 0x1_00000000 -> 0x1_80000000 (size: 12GB) * All UART devices moved under this bus to reflect their shared address translation domain - New PDMA controller node under dma_bus with: * Base address and interrupt configuration * Clock and reset controls * 16 DMA channels * Required DMA cell properties The PDMA node is marked as disabled by default, allowing board-specific device trees to enable it as needed. Signed-off-by: Guodong Xu --- arch/riscv/boot/dts/spacemit/k1.dtsi | 234 +++++++++++++++------------ 1 file changed, 128 insertions(+), 106 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index dead05a3c816..557feac860de 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -369,112 +369,13 @@ syscon_apbc: system-controller@d4015000 { #reset-cells =3D <1>; }; =20 - uart0: serial@d4017000 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017000 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART0>, - <&syscon_apbc CLK_UART0_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <42>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart2: serial@d4017100 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017100 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART2>, - <&syscon_apbc CLK_UART2_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <44>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart3: serial@d4017200 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017200 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART3>, - <&syscon_apbc CLK_UART3_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <45>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart4: serial@d4017300 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017300 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART4>, - <&syscon_apbc CLK_UART4_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <46>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart5: serial@d4017400 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017400 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART5>, - <&syscon_apbc CLK_UART5_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <47>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart6: serial@d4017500 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017500 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART6>, - <&syscon_apbc CLK_UART6_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <48>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart7: serial@d4017600 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017600 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART7>, - <&syscon_apbc CLK_UART7_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <49>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart8: serial@d4017700 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017700 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART8>, - <&syscon_apbc CLK_UART8_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <50>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; - }; - - uart9: serial@d4017800 { - compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; - reg =3D <0x0 0xd4017800 0x0 0x100>; - clocks =3D <&syscon_apbc CLK_UART9>, - <&syscon_apbc CLK_UART9_BUS>; - clock-names =3D "core", "bus"; - interrupts =3D <51>; - reg-shift =3D <2>; - reg-io-width =3D <4>; - status =3D "disabled"; + dma_bus: bus@4 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; + ranges; }; =20 gpio: gpio@d4019000 { @@ -792,3 +693,124 @@ pwm19: pwm@d4022c00 { }; }; }; + +&dma_bus { + pdma0: dma-controller@d4000000 { + compatible =3D "spacemit,pdma-1.0"; + reg =3D <0x0 0xd4000000 0x0 0x4000>; + interrupts =3D <72>; + clocks =3D <&syscon_apmu CLK_DMA>; + resets =3D <&syscon_apmu RESET_DMA>; + #dma-cells=3D <2>; + #dma-channels =3D <16>; + status =3D "disabled"; + }; + + uart0: serial@d4017000 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017000 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART0>, + <&syscon_apbc CLK_UART0_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <42>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@d4017100 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017100 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART2>, + <&syscon_apbc CLK_UART2_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <44>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@d4017200 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017200 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART3>, + <&syscon_apbc CLK_UART3_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <45>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@d4017300 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017300 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART4>, + <&syscon_apbc CLK_UART4_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <46>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@d4017400 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017400 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART5>, + <&syscon_apbc CLK_UART5_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <47>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart6: serial@d4017500 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017500 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART6>, + <&syscon_apbc CLK_UART6_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <48>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart7: serial@d4017600 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017600 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART7>, + <&syscon_apbc CLK_UART7_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <49>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart8: serial@d4017700 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017700 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART8>, + <&syscon_apbc CLK_UART8_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <50>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart9: serial@d4017800 { + compatible =3D "spacemit,k1-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017800 0x0 0x100>; + clocks =3D <&syscon_apbc CLK_UART9>, + <&syscon_apbc CLK_UART9_BUS>; + clock-names =3D "core", "bus"; + interrupts =3D <51>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; +}; /* &dma_bus */ --=20 2.43.0 From nobody Sat Oct 11 04:11:29 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD3D828314E for ; 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Wed, 11 Jun 2025 06:00:35 -0700 (PDT) Received: from localhost.localdomain ([2409:8a00:31a4:6520:3d67:ceb1:7c60:9098]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236030925e3sm86984115ad.53.2025.06.11.06.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 06:00:34 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 6/8] riscv: dts: spacemit: Enable PDMA0 controller on Banana Pi F3 Date: Wed, 11 Jun 2025 20:57:21 +0800 Message-ID: <20250611125723.181711-7-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Peripheral DMA controller (PDMA0) on the SpacemiT K1-based Banana Pi F3 board by setting its status to "okay". This board-specific configuration activates the PDMA controller defined in the SoC's base device tree. Signed-off-by: Guodong Xu --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 2363f0e65724..115222c065ab 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -45,3 +45,7 @@ &uart0 { pinctrl-0 =3D <&uart0_2_cfg>; status =3D "okay"; }; + +&pdma0 { + status =3D "okay"; +}; --=20 2.43.0 From nobody Sat Oct 11 04:11:29 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C9D0281357 for ; Wed, 11 Jun 2025 13:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 11 Jun 2025 06:00:48 -0700 (PDT) Received: from localhost.localdomain ([2409:8a00:31a4:6520:3d67:ceb1:7c60:9098]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236030925e3sm86984115ad.53.2025.06.11.06.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 06:00:48 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 7/8] dma: Kconfig: MMP_PDMA: Add support for ARCH_SPACEMIT Date: Wed, 11 Jun 2025 20:57:22 +0800 Message-ID: <20250611125723.181711-8-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the MMP_PDMA driver to support the SpacemiT architecture by adding ARCH_SPACEMIT as a dependency in Kconfig. This allows the driver to be built for SpacemiT-based platforms alongside existing ARCH_MMP and ARCH_PXA architectures. Signed-off-by: Guodong Xu --- drivers/dma/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index db87dd2a07f7..fff70f66c773 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -451,7 +451,7 @@ config MILBEAUT_XDMAC =20 config MMP_PDMA tristate "MMP PDMA support" - depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST + depends on ARCH_MMP || ARCH_PXA || ARCH_SPACEMIT || COMPILE_TEST select DMA_ENGINE help Support the MMP PDMA engine for PXA and MMP platform. --=20 2.43.0 From nobody Sat Oct 11 04:11:29 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70D9328136C for ; Wed, 11 Jun 2025 13:01:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; 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Wed, 11 Jun 2025 06:01:02 -0700 (PDT) Received: from localhost.localdomain ([2409:8a00:31a4:6520:3d67:ceb1:7c60:9098]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236030925e3sm86984115ad.53.2025.06.11.06.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 06:01:01 -0700 (PDT) From: Guodong Xu To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dlan@gentoo.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, drew@pdp7.com, emil.renner.berthing@canonical.com, inochiama@gmail.com, geert+renesas@glider.be, tglx@linutronix.de, hal.feng@starfivetech.com, joel@jms.id.au, duje.mihanovic@skole.hr Cc: guodong@riscstar.com, elder@riscstar.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: [PATCH 8/8] riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC Date: Wed, 11 Jun 2025 20:57:23 +0800 Message-ID: <20250611125723.181711-9-guodong@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611125723.181711-1-guodong@riscstar.com> References: <20250611125723.181711-1-guodong@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CONFIG_MMP_PDMA in the riscv defconfig for SpacemiT K1 SoC boards like the BananaPI-F3 (BPI-F3) and the Sipeed LicheePi 3A. According to make savedefconfig, the position of CONFIG_DWMAC_THEAD=3Dm should be in another place. It was updated in this patch. CONFIG_DWMAC_THEAD was initially introduced into riscv defconfig in commit 0207244ea0e7 ("riscv: defconfig: enable pinctrl and dwmac support for TH1520") Signed-off-by: Guodong Xu --- arch/riscv/configs/defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 517cc4c99efc..83d0366194ba 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -134,6 +134,7 @@ CONFIG_MACB=3Dy CONFIG_E1000E=3Dy CONFIG_R8169=3Dy CONFIG_STMMAC_ETH=3Dm +CONFIG_DWMAC_THEAD=3Dm CONFIG_MICREL_PHY=3Dy CONFIG_MICROSEMI_PHY=3Dy CONFIG_MOTORCOMM_PHY=3Dy @@ -240,7 +241,7 @@ CONFIG_RTC_DRV_SUN6I=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy -CONFIG_DWMAC_THEAD=3Dm +CONFIG_MMP_PDMA=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0