From nobody Sat Oct 11 04:13:41 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AAF726A0B3; Wed, 11 Jun 2025 11:43:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749642233; cv=none; b=qt8Z4HCpINXB6VPCjqrgjBISB6alNkoy2RmpS+B36vXF5HwwHbzrthkfDWK5Nc1K4LaCV4tb9iK8HUQ7F0lXH1xNuf6TxZZAvQraG324GHuEHoA1VEvR9a6NZfdipYrF6C4jpiOpqlv1s+UDa8uf4VbtK3DOEXIhZs3XFzsLPDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749642233; c=relaxed/simple; bh=MPR2cNqIzV4zNMkRkjqykLHeeN+/bXK5N6sydvZqJGA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tCbGWi7rqRXhZ5DkZ3JInWKETA+Tw22Jl5dk398WxJaQYuDN6QlXXdPOaOsyQn3onfl98V0MwsPlvtWC8q7y+xErqRaCn3p938Oe+ll/zh83gVNTFGjBpZ+L9cCztWmXlCo0avbt8Nse0K4fpOBYQFOzen+L8qZyt/iBX6+t3B8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=gCB3VUE2; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gCB3VUE2" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55BBhiH62587909; Wed, 11 Jun 2025 06:43:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1749642224; bh=01SkIyYDrdKEhOlWGDqsXApkLwVFyXWIyMF6ULwGqHs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gCB3VUE2UDJk9t2yzhYHSaNuCmqUM6p8AAuZKAYpnIvZzSXLrBmFsFXEuDM4KFhq0 rtyoshPwL8nF+P2ddZuz+Ht+hyReJoLhYqeGcpYRaecnA752CWTXwLccNBI6t3l/vS pKXtauIb4oihrom8uTCtXdBZbus1PUT1q+h4A1DE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55BBhib11108922 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 11 Jun 2025 06:43:44 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 11 Jun 2025 06:43:43 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 11 Jun 2025 06:43:44 -0500 Received: from uda0492258.dhcp.ti.com (dhcp-172-24-227-169.dhcp.ti.com [172.24.227.169]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55BBhavE270460; Wed, 11 Jun 2025 06:43:41 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 1/5] arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board files Date: Wed, 11 Jun 2025 17:13:32 +0530 Message-ID: <20250611114336.2392320-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611114336.2392320-1-s-vadapalli@ti.com> References: <20250611114336.2392320-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "cpsw3g" node in the SoC file "k3-am62-main.dtsi" and enable it in the board files: a) k3-am62-lp-sk.dts b) k3-am625-beagleplay.dts c) k3-am525-sk.dts Signed-off-by: Siddharth Vadapalli --- v1 of this patch was 4 different patches which have currently been squashed: https://lore.kernel.org/r/20250529133443.1252293-2-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-3-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-4-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-5-s-vadapalli@ti.com/ Squashing the patches is the only change since the v1 series, in addition to updating the commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++ arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 1 + 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index aafdb90c0eb7..cec77fba24e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -149,6 +149,10 @@ &sdhci1 { vqmmc-supply =3D <&vddshv_sdio>; }; =20 +&cpsw3g { + status =3D "okay"; +}; + &cpsw_port2 { status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 9e0b6eee9ac7..3d8650e7c80b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -724,6 +724,8 @@ cpsw3g: ethernet@8000000 { dma-names =3D "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 72b09f9c69d8..999f5baaba1a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -585,6 +585,7 @@ &usb1 { }; =20 &cpsw3g { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rgmii1_pins_default>, <&spe_pins_default>, <&gbe_pmx_obsclk>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 2fbfa3719345..9c2258dfd08d 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -201,6 +201,7 @@ &sdhci1 { }; =20 &cpsw3g { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; --=20 2.34.1 From nobody Sat Oct 11 04:13:41 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92CCC26A0B3; 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Wed, 11 Jun 2025 06:43:47 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 11 Jun 2025 06:43:47 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 11 Jun 2025 06:43:47 -0500 Received: from uda0492258.dhcp.ti.com (dhcp-172-24-227-169.dhcp.ti.com [172.24.227.169]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55BBhavF270460; Wed, 11 Jun 2025 06:43:44 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 2/5] arm64: dts: ti: k3-am65: disable "mcu_cpsw" in SoC file and enable in board file Date: Wed, 11 Jun 2025 17:13:33 +0530 Message-ID: <20250611114336.2392320-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611114336.2392320-1-s-vadapalli@ti.com> References: <20250611114336.2392320-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-am65-mcu.dtsi" and enable it in the board file "k3-am654-base-board.dts". Also, now that "mcu_cpsw" is disabled in the SoC file, disabling it in "k3-am65-iot2050-common.dtsi" is no longer required. Hence, remove the section corresponding to this change. Signed-off-by: Siddharth Vadapalli --- v1 of this patch was 3 different patches which have currently been squashed: https://lore.kernel.org/r/20250529133443.1252293-6-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-7-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-8-s-vadapalli@ti.com/ Squashing the patches is the only change since the v1 series, in addition to updating the commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 4 ---- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index e5136ed94765..48e740eb0088 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -475,10 +475,6 @@ &main_i2c3 { #size-cells =3D <0>; }; =20 -&mcu_cpsw { - status =3D "disabled"; -}; - &sdhci1 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7cf1f646500a..cd0b796c5f8f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -354,6 +354,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index c30425960398..d2632d1f8eb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -606,6 +606,7 @@ partition@3fe0000 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; }; --=20 2.34.1 From nobody Sat Oct 11 04:13:41 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9441A26E709; Wed, 11 Jun 2025 11:43:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749642239; cv=none; b=rDhMbSi6vSos/nYKays+ALzLLBiBudBezpYLXNJ14eToD0F2Y5UwPNqxeqbl5t0lWoVaf58DQiqOQUpBWz4JYAc6FEUzZRjICaMRrW515y4W5yZ5drIJHqQOZSRPMwlYrBKD6RZRdjOATg4cWUH988yvoOV2y3qTLNxl3YFyr2g= ARC-Message-Signature: i=1; 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Wed, 11 Jun 2025 06:43:50 -0500 Received: from uda0492258.dhcp.ti.com (dhcp-172-24-227-169.dhcp.ti.com [172.24.227.169]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55BBhavG270460; Wed, 11 Jun 2025 06:43:47 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j7200: disable "mcu_cpsw" in SoC file and enable in board file Date: Wed, 11 Jun 2025 17:13:34 +0530 Message-ID: <20250611114336.2392320-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611114336.2392320-1-s-vadapalli@ti.com> References: <20250611114336.2392320-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j7200-mcu-wakeup.dtsi" and enable it in the board file "k3-j7200-common-proc-board.dts". Signed-off-by: Siddharth Vadapalli --- v1 of this patch was 2 different patches which have currently been squashed: https://lore.kernel.org/r/20250529133443.1252293-9-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-10-s-vadapalli@ti.com/ Squashing the patches is the only change since the v1 series, in addition to updating the commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index f684ce6ad9ad..021cdeb84ad1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -321,6 +321,7 @@ &wkup_gpio0 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..604295092d06 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; 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Wed, 11 Jun 2025 06:43:54 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 11 Jun 2025 06:43:54 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 11 Jun 2025 06:43:53 -0500 Received: from uda0492258.dhcp.ti.com (dhcp-172-24-227-169.dhcp.ti.com [172.24.227.169]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55BBhavH270460; Wed, 11 Jun 2025 06:43:51 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 4/5] arm64: dts: ti: k3-j721e: disable "mcu_cpsw" in SoC file and enable it in board file Date: Wed, 11 Jun 2025 17:13:35 +0530 Message-ID: <20250611114336.2392320-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611114336.2392320-1-s-vadapalli@ti.com> References: <20250611114336.2392320-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j721e-mcu-wakeup.dtsi" and enable it in the board file "k3-j721e-common-proc-board.dts". Signed-off-by: Siddharth Vadapalli --- v1 of this patch was 2 different patches which have currently been squashed: https://lore.kernel.org/r/20250529133443.1252293-11-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-12-s-vadapalli@ti.com/ Squashing the patches is the only change since the v1 series, in addition to updating the commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 45311438315f..eda85dafb794 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -767,6 +767,7 @@ exp5: gpio@20 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..dd923540ca0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -551,6 +551,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; 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Wed, 11 Jun 2025 06:43:54 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 5/5] arm64: dts: ti: k3-j721s2: disable "mcu_cpsw" in SoC file and enable in board files Date: Wed, 11 Jun 2025 17:13:36 +0530 Message-ID: <20250611114336.2392320-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611114336.2392320-1-s-vadapalli@ti.com> References: <20250611114336.2392320-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node in the SoC file "k3-j721s2-mcu-wakeup.dtsi" and enable it in the board files: a) k3-am68-sk-base-board.dts b) k3-j721s2-common-proc-board.dts Signed-off-by: Siddharth Vadapalli --- v1 of this patch was 2 different patches which have currently been squashed: https://lore.kernel.org/r/20250529133443.1252293-13-s-vadapalli@ti.com/ https://lore.kernel.org/r/20250529133443.1252293-14-s-vadapalli@ti.com/ In addition to squashing the patches and updating the commit message, "mcu_cpsw" has been enabled in "k3-am68-sk-base-board.dts" as well, since it uses the SoC file of J721S2. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 5fa70a874d7b..893b730911e8 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -619,6 +619,7 @@ &main_sdhci1 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e2fc1288ed07..a482b3ad5095 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -409,6 +409,7 @@ &main_sdhci1 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..b5fd012d9564 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1