From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B648A2820D8 for ; Wed, 11 Jun 2025 10:49:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638964; cv=none; b=PHdPavHdrfUCZUxvS4YQPEizXRPbQBa34ER5QFtagtcPnPhY9Ahli0qMbhzOfuvEn0PB4LFhTiC4xg3mIL0aGm8JK8nGYtuMdTnsFMeFZMei+i+lgnW4+yttUbgWVJriRkwzhCdYQZk40NDK+hVXJ1ZLDrhCuloWpm7u0xYlA0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638964; c=relaxed/simple; bh=agoGXUs6Jt9hujfMYLYSSir3rt9ddFa9nUHdIfaNGrE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=t2Cdan9wO0BoDYi5jWEOekUpJ6f9J+ApfFlqqstjrxuSv4xyOT5dbW/ekzZa2rFJWbKQy+H5rJSxwiRZRE/lOnqT5svCTEbsmJIApMCZXt/rLw2q0INV3PfSeNYRO8rB+nDrk4xSzmjFO84RwArj+lhGBMqX7WsEmN4MjFlsFC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F4461BC0; Wed, 11 Jun 2025 03:49:02 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5AA8C3F77D; Wed, 11 Jun 2025 03:49:20 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, maz@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH 1/6] arm64: cpufeature: add FEAT_LSUI Date: Wed, 11 Jun 2025 11:49:11 +0100 Message-Id: <20250611104916.10636-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611104916.10636-1-yeoreum.yun@arm.com> References: <20250611104916.10636-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since Armv9.6, FEAT_LSUI supplies load/store instructions for privileged level to access user memory without clearing PSTATE.PAN bit. Add LSUI feature so that the unprevilieged load/store instrcutions could be used when kernel accesses user memory without clearing PSTATE.PAN = bit. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpufeature.c | 8 ++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b34044e20128..d914982c7cee 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -278,6 +278,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = =3D { =20 static const struct arm64_ftr_bits ftr_id_aa64isar3[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FPRCVT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL= 1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -3061,6 +3062,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_pmuv3, }, #endif + { + .desc =3D "Unprivileged Load Store Instructions (LSUI)", + .capability =3D ARM64_HAS_LSUI, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 10effd4cff6b..d625f4987aa7 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -59,6 +59,7 @@ HAS_TLB_RANGE HAS_VA52 HAS_VIRT_HOST_EXTN HAS_WFXT +HAS_LSUI HAFT HW_DBM KVM_HVHE --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 99AC1283CB1 for ; Wed, 11 Jun 2025 10:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638966; cv=none; b=XhEpNGlW94ZJZFmTUhQnw12RztGxbXPrw27yie4nZp1++ISmFzYwjO/qMAgFDBn+XVjJcsI1WuNpJCLwcs/T9vzzxYgy/8Ic6p1Qhrpbzp6eLmLvvC0T9lt0nwTWlFsj7xYFlmNPM+4+PFrSopbTIKMZALHUK8OVbG3y6e/D/f8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638966; c=relaxed/simple; bh=JVP6OfbAmASCiu3vKazYYbs14p39xHpdEiwaR6eOXCU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g6sV1tVfum+6z7jxzMKLIoz1O4T/CdXsWHexR0WVa0IL4o3A3v6gfcOaGwpsnfCDbH3pAXZTuW/ZdvQ31ykKfSX/Rk1yN7zEJ7SeCguX9XtXCdsQJP16ZVdyxsXB1IHaBf9iCBDo0zs23N3z4g7YTqfK+hb3JzChp/Iz8Y9zQtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0C4115A1; Wed, 11 Jun 2025 03:49:04 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 830B23F77D; Wed, 11 Jun 2025 03:49:22 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, maz@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH 2/6] arm64/Kconfig: add LSUI Kconfig Date: Wed, 11 Jun 2025 11:49:12 +0100 Message-Id: <20250611104916.10636-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611104916.10636-1-yeoreum.yun@arm.com> References: <20250611104916.10636-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since Armv9.6, FEAT_LSUI supplies the load/store instructions for previleged level to access to access user memory without clearing PSTATE.PAN bit. It's enough to add CONFIG_AS_HAS_LSUI only because the code for LUSI uses indiviual `.arch_extension` entries. Signed-off-by: Yeoreum Yun --- arch/arm64/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 55fc331af337..20f360eef2ac 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2237,6 +2237,13 @@ config ARM64_GCS =20 endmenu # "v9.4 architectural features" =20 +menu "v9.6 architectural features" + +config AS_HAS_LSUI + def_bool $(as-instr,.arch_extension lsui) + +endmenu # "v9.6 architectural features" + config ARM64_SVE bool "ARM Scalable Vector Extension support" default y @@ -2498,4 +2505,3 @@ endmenu # "CPU Power Management" source "drivers/acpi/Kconfig" =20 source "arch/arm64/kvm/Kconfig" - --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CB7062874E4 for ; Wed, 11 Jun 2025 10:49:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638968; cv=none; b=dFEoLRBMz1yD+GtoYvD6VBP/X3qUJEhbp/2oxI/G8Ar3EL109S8AkSBNGr2qJsLmvam3frlE+CORNMyXenTFU7ImYLC8HLF8UT5Qp1uZtuyFVvQ/NmKKSxJSNmmxWEIsbHfjYKzfb/hF/u9CDrAtjyxXXlHe5icOKI3rt9N+mYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638968; c=relaxed/simple; bh=Xty6o4O/6jE/zrmvBD8pJ9Znos7innQaLeWnUhWql2A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kqpAVla9wdJrquQvSluxXSFVc4gl1dgw3g+gGz3h/VptXU11HHnCZenIKdsEgpvyOPO2EF1Q6w2M86wkyAQvOo1h31SmquFDd3VresR4eGobg728FSWIVTGFV6pOPz72UYRn8B2AvvoSi26Ck1cWhIpNz+ZVRWam9EsYUM40yWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04E0615A1; Wed, 11 Jun 2025 03:49:07 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B47FA3F77D; Wed, 11 Jun 2025 03:49:24 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, maz@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH 3/6] arm64/futex: move futex atomic logic with clearing PAN bit Date: Wed, 11 Jun 2025 11:49:13 +0100 Message-Id: <20250611104916.10636-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611104916.10636-1-yeoreum.yun@arm.com> References: <20250611104916.10636-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move current futex atomic logics which uses ll/sc method with cleraing PSTATE.PAN to separate file (futex_ll_sc_u.h) so that former method will be used only when FEAT_LSUI isn't supported. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/futex_ll_sc_u.h | 115 +++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 arch/arm64/include/asm/futex_ll_sc_u.h diff --git a/arch/arm64/include/asm/futex_ll_sc_u.h b/arch/arm64/include/as= m/futex_ll_sc_u.h new file mode 100644 index 000000000000..6702ba66f1b2 --- /dev/null +++ b/arch/arm64/include/asm/futex_ll_sc_u.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Arm Ltd. + */ +#ifndef __ASM_FUTEX_LL_SC_U_H +#define __ASM_FUTEX_LL_SC_U_H + +#include +#include + +#define FUTEX_ATOMIC_OP(op, asm_op) \ +static __always_inline int \ +__ll_sc_u_futex_atomic_##op(int oparg, u32 __user *uaddr, int *oval) \ +{ \ + unsigned int loops =3D LL_SC_MAX_LOOPS; \ + int ret, val, tmp; \ + \ + uaccess_enable_privileged(); \ + asm volatile("// __ll_sc_u_futex_atomic_" #op "\n" \ + " prfm pstl1strm, %2\n" \ + "1: ldxr %w1, %2\n" \ + " " #asm_op " %w3, %w1, %w5\n" \ + "2: stlxr %w0, %w3, %2\n" \ + " cbz %w0, 3f\n" \ + " sub %w4, %w4, %w0\n" \ + " cbnz %w4, 1b\n" \ + " mov %w0, %w6\n" \ + "3:\n" \ + " dmb ish\n" \ + _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) \ + _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0) \ + : "=3D&r" (ret), "=3D&r" (val), "+Q" (*uaddr), "=3D&r" (tmp), \ + "+r" (loops) \ + : "r" (oparg), "Ir" (-EAGAIN) \ + : "memory"); \ + uaccess_disable_privileged(); \ + \ + if (!ret) \ + *oval =3D val; \ + \ + return ret; \ +} + +FUTEX_ATOMIC_OP(add, add) +FUTEX_ATOMIC_OP(or, orr) +FUTEX_ATOMIC_OP(and, and) +FUTEX_ATOMIC_OP(eor, eor) + +#undef FUTEX_ATOMIC_OP + +static __always_inline int +__ll_sc_u_futex_atomic_set(int oparg, u32 __user *uaddr, int *oval) +{ + unsigned int loops =3D LL_SC_MAX_LOOPS; + int ret, val; + + uaccess_enable_privileged(); + asm volatile("//__ll_sc_u_futex_xchg\n" + " prfm pstl1strm, %2\n" + "1: ldxr %w1, %2\n" + "2: stlxr %w0, %w4, %2\n" + " cbz %w3, 3f\n" + " sub %w3, %w3, %w0\n" + " cbnz %w3, 1b\n" + " mov %w0, %w5\n" + "3:\n" + " dmb ish\n" + _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) + _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0) + : "=3D&r" (ret), "=3D&r" (val), "+Q" (*uaddr), "+r" (loops) + : "r" (oparg), "Ir" (-EAGAIN) + : "memory"); + uaccess_disable_privileged(); + + if (!ret) + *oval =3D val; + + return ret; +} + +static __always_inline int +__ll_sc_u_futex_cmpxchg(u32 __user *uaddr, u32 oldval, u32 newval, u32 *ov= al) +{ + int ret =3D 0; + unsigned int loops =3D LL_SC_MAX_LOOPS; + u32 val, tmp; + + uaccess_enable_privileged(); + asm volatile("//__ll_sc_u_futex_cmpxchg\n" + " prfm pstl1strm, %2\n" + "1: ldxr %w1, %2\n" + " eor %w3, %w1, %w5\n" + " cbnz %w3, 4f\n" + "2: stlxr %w3, %w6, %2\n" + " cbz %w3, 3f\n" + " sub %w4, %w4, %w3\n" + " cbnz %w4, 1b\n" + " mov %w0, %w7\n" + "3:\n" + " dmb ish\n" + "4:\n" + _ASM_EXTABLE_UACCESS_ERR(1b, 4b, %w0) + _ASM_EXTABLE_UACCESS_ERR(2b, 4b, %w0) + : "+r" (ret), "=3D&r" (val), "+Q" (*uaddr), "=3D&r" (tmp), "+r" (loops) + : "r" (oldval), "r" (newval), "Ir" (-EAGAIN) + : "memory"); + uaccess_disable_privileged(); + + if (!ret) + *oval =3D val; + + return ret; +} + +#endif /* __ASM_FUTEX_LL_SC_U_H */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 62553288CA2 for ; Wed, 11 Jun 2025 10:49:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CF3D15A1; Wed, 11 Jun 2025 03:49:09 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DCDF43F77D; Wed, 11 Jun 2025 03:49:26 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, maz@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH 4/6] arm64/futex: add futex atomic operation with FEAT_LSUI Date: Wed, 11 Jun 2025 11:49:14 +0100 Message-Id: <20250611104916.10636-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611104916.10636-1-yeoreum.yun@arm.com> References: <20250611104916.10636-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current futex atomic operations are implemented with ll/sc instructions and clearing PSTATE.PAN. Since Armv9.6, FEAT_LSUI supplies not only load/store instructions but also atomic operation for user memory access in kernel it doesn't need to clear PSTATE.PAN bit anymore. With theses instructions some of futex atomic operations don't need to be implmented with ldxr/stlxr pair instead can be implmented with one atomic operation supplied by FEAT_LSUI. However, some of futex atomic operations still need to use ll/sc way via ldtxr/stltxr supplied by FEAT_LSUI since there is no correspondant atomic instruction or doesn't support word size operation (i.e) eor, cas{mb}t But It's good to work without clearing PSTATE.PAN bit. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/futex_lsui.h | 132 ++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 arch/arm64/include/asm/futex_lsui.h diff --git a/arch/arm64/include/asm/futex_lsui.h b/arch/arm64/include/asm/f= utex_lsui.h new file mode 100644 index 000000000000..0dc7dca91cdb --- /dev/null +++ b/arch/arm64/include/asm/futex_lsui.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Arm Ltd. + */ + +#ifndef __ASM_FUTEX_LSUI_H +#define __ASM_FUTEX_LSUI_H + +#include +#include + +#define FUTEX_ATOMIC_OP(op, asm_op, mb) \ +static __always_inline int \ +__lsui_futex_atomic_##op(int oparg, u32 __user *uaddr, int *oval) \ +{ \ + int ret =3D 0; \ + int val; \ + \ + mte_enable_tco(); \ + uaccess_ttbr0_enable(); \ + \ + asm volatile("// __lsui_futex_atomic_" #op "\n" \ + __LSUI_PREAMBLE \ + "1: " #asm_op #mb " %w3, %w2, %1\n" \ + "2:\n" \ + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \ + : "+r" (ret), "+Q" (*uaddr), "=3Dr" (val) \ + : "r" (oparg) \ + : "memory"); \ + \ + mte_disable_tco(); \ + uaccess_ttbr0_disable(); \ + \ + if (!ret) \ + *oval =3D val; \ + \ + return ret; \ +} + +FUTEX_ATOMIC_OP(add, ldtadd, al) +FUTEX_ATOMIC_OP(or, ldtset, al) +FUTEX_ATOMIC_OP(andnot, ldtclr, al) +FUTEX_ATOMIC_OP(set, swpt, al) + +#undef FUTEX_ATOMIC_OP + +static __always_inline int +__lsui_futex_atomic_and(int oparg, u32 __user *uaddr, int *oval) +{ + return __lsui_futex_atomic_andnot(~oparg, uaddr, oval); +} + +static __always_inline int +__lsui_futex_atomic_eor(int oparg, u32 __user *uaddr, int *oval) +{ + unsigned int loops =3D LL_SC_MAX_LOOPS; + int ret, val, tmp; + + mte_enable_tco(); + uaccess_ttbr0_enable(); + + asm volatile("// __lsui_futex_atomic_eor\n" + __LSUI_PREAMBLE + " prfm pstl1strm, %2\n" + "1: ldtxr %w1, %2\n" + " eor %w3, %w1, %w5\n" + "2: stltxr %w0, %w3, %2\n" + " cbz %w0, 3f\n" + " sub %w4, %w4, %w0\n" + " cbnz %w4, 1b\n" + " mov %w0, %w6\n" + "3:\n" + " dmb ish\n" + _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) + _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0) + : "=3D&r" (ret), "=3D&r" (val), "+Q" (*uaddr), "=3D&r" (tmp), + "+r" (loops) + : "r" (oparg), "Ir" (-EAGAIN) + : "memory"); + + mte_disable_tco(); + uaccess_ttbr0_disable(); + + if (!ret) + *oval =3D val; + + return ret; +} + +static __always_inline int +__lsui_futex_cmpxchg(u32 __user *uaddr, u32 oldval, u32 newval, u32 *oval) +{ + int ret =3D 0; + unsigned int loops =3D LL_SC_MAX_LOOPS; + u32 val, tmp; + + mte_enable_tco(); + uaccess_ttbr0_enable(); + + /* + * cas{al}t doesn't support word size... + */ + asm volatile("//__lsui_futex_cmpxchg\n" + __LSUI_PREAMBLE + " prfm pstl1strm, %2\n" + "1: ldtxr %w1, %2\n" + " eor %w3, %w1, %w5\n" + " cbnz %w3, 4f\n" + "2: stltxr %w3, %w6, %2\n" + " cbz %w3, 3f\n" + " sub %w4, %w4, %w3\n" + " cbnz %w4, 1b\n" + " mov %w0, %w7\n" + "3:\n" + " dmb ish\n" + "4:\n" + _ASM_EXTABLE_UACCESS_ERR(1b, 4b, %w0) + _ASM_EXTABLE_UACCESS_ERR(2b, 4b, %w0) + : "+r" (ret), "=3D&r" (val), "+Q" (*uaddr), "=3D&r" (tmp), "+r" (loops) + : "r" (oldval), "r" (newval), "Ir" (-EAGAIN) + : "memory"); + + mte_disable_tco(); + uaccess_ttbr0_disable(); + + if (!ret) + *oval =3D oldval; + + return ret; +} + +#endif /* __ASM_FUTEX_LSUI_H */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 56FE028A714 for ; Wed, 11 Jun 2025 10:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638973; cv=none; b=fJeFcCdH8rWv+MEcTGHS50M3x/ha/MUCu9NeF1574TVEktgf0q2Z2o6x0T3dnlkXSW2+WEgupGMlHXy01dG7z2X5SFutvK6tsgixwiwBw6KONjARkQWHeXRpkZCFCFyWp2tz1+ezfVQfToBdfnRaKTf19v09mlUG4SlaP4BZJkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638973; c=relaxed/simple; bh=1Pq3fWCbMme7can5L1VXxkKY/ixp6vJKLVRm1fVwo3g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sQscgs0/rlQKGUO1eDKIph0IRMHFF8ywZjbL7oYAust/AY30DeL2MDETQy+Ep5IjdU+oIuBAq0IleLEMH1nctuAN/mY0W1Po7P8VtdLUfUDjkEyLivky0uCaVVSXuvPAlQmOpwZZonaAakMj2ouh99+oNqRplmNRCyTIFIu46mI= ARC-Authentication-Results: i=1; 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charset="utf-8" This patch introduces lsui.h header file for applying runtime patch to use load/store unprevileged instructions when cpu supports FEAT_LSUI otherwise uses method implemented via ll/sc way with clearing PSTATE.PAN bit Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/lsui.h | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 arch/arm64/include/asm/lsui.h diff --git a/arch/arm64/include/asm/lsui.h b/arch/arm64/include/asm/lsui.h new file mode 100644 index 000000000000..39bf232f3eb7 --- /dev/null +++ b/arch/arm64/include/asm/lsui.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Arm Ltd. + */ +#ifndef __ASM_LSUI_H +#define __ASM_LSUI_H + +#define LL_SC_MAX_LOOPS 128 /* What's the largest number you can think of?= */ + +#include + +#ifdef CONFIG_AS_HAS_LSUI + +#define __LSUI_PREAMBLE ".arch_extension lsui\n" + +#include +#include +#include +#include +#include +#include + +#include + +#define __lsui_ll_sc_u_body(op, ...) \ +({ \ + alternative_has_cap_likely(ARM64_HAS_LSUI) ? \ + __lsui_##op(__VA_ARGS__) : \ + __ll_sc_u_##op(__VA_ARGS__); \ +}) + +#else /* CONFIG_AS_HAS_LSUI */ + +#define __lsui_ll_sc_u_body(op, ...) __ll_sc_u_##op(__VA_ARGS__) + +#endif /* CONFIG_AS_HAS_LSUI */ +#endif /* __ASM_LSUI_H */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 11 04:27:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6BCBC2BD59A for ; Wed, 11 Jun 2025 10:49:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638975; cv=none; b=ej96PyMbgzHzYW3z/wwJGQ4i6GmE6gj70wOIpLwfLfj1K15ONfH3loFL99phZ3gNVRx+p6SL68DA9eCMzvVN1xi8CtjiLfrrdVh0Q6BoS7B5sWMFcKgceqlS4fdzhUJMvOTy759S0Vmw/b2DFKp0JGJysVXUG4Al1xDAXZk9ITg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749638975; c=relaxed/simple; bh=CCsMW2Y4vgWxPuHdWABQb40IsOOZLbjksJf8mcF8rtI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eFhaNltWdy9SDeFqcfFaPtWxpQMrOyo/T4NFZmDWr5blKhFHKCiF3Ew+tyD53SqD/lGwXI/ZWisTf7V9djNkfX1Vr1A/LVblNuQWKZP1v8BCg9R3kZL65nXWD8Ek6i32X5M6vhAiEk8wDg4eONinKodSNaYkszVv81pc040kr9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D05E1655; Wed, 11 Jun 2025 03:49:13 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 389FD3F77D; Wed, 11 Jun 2025 03:49:31 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, maz@kernel.org, oliver.upton@linux.dev, ardb@kernel.org, frederic@kernel.org, james.morse@arm.com, joey.gouly@arm.com, scott@os.amperecomputing.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yeoreum Yun Subject: [PATCH 6/6] arm64/futex: support futex with FEAT_LSUI Date: Wed, 11 Jun 2025 11:49:16 +0100 Message-Id: <20250611104916.10636-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250611104916.10636-1-yeoreum.yun@arm.com> References: <20250611104916.10636-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since Armv9.6, FEAT_LSUI supplies load/store unprevileged instructions for kernel to access user memory without clearing PSTATE.PAN. This patch makes futex use futex_atomic operations implemented with these instruction when cpu supports FEAT_LSUI otherwise they work with ldxr/stlxr with clearing PSTATE.PAN bit. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/futex.h | 99 +++++++++++----------------------- 1 file changed, 31 insertions(+), 68 deletions(-) diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h index bc06691d2062..ed4586776655 100644 --- a/arch/arm64/include/asm/futex.h +++ b/arch/arm64/include/asm/futex.h @@ -9,71 +9,60 @@ #include =20 #include +#include =20 -#define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of?= */ - -#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ -do { \ - unsigned int loops =3D FUTEX_MAX_LOOPS; \ - \ - uaccess_enable_privileged(); \ - asm volatile( \ -" prfm pstl1strm, %2\n" \ -"1: ldxr %w1, %2\n" \ - insn "\n" \ -"2: stlxr %w0, %w3, %2\n" \ -" cbz %w0, 3f\n" \ -" sub %w4, %w4, %w0\n" \ -" cbnz %w4, 1b\n" \ -" mov %w0, %w6\n" \ -"3:\n" \ -" dmb ish\n" \ - _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0) \ - _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0) \ - : "=3D&r" (ret), "=3D&r" (oldval), "+Q" (*uaddr), "=3D&r" (tmp), \ - "+r" (loops) \ - : "r" (oparg), "Ir" (-EAGAIN) \ - : "memory"); \ - uaccess_disable_privileged(); \ -} while (0) +#define FUTEX_ATOMIC_OP(op) \ +static __always_inline int \ +__futex_atomic_##op(int oparg, u32 __user *uaddr, int *oval) \ +{ \ + return __lsui_ll_sc_u_body(futex_atomic_##op, oparg, uaddr, oval); \ +} + +FUTEX_ATOMIC_OP(add) +FUTEX_ATOMIC_OP(or) +FUTEX_ATOMIC_OP(and) +FUTEX_ATOMIC_OP(eor) +FUTEX_ATOMIC_OP(set) + +#undef FUTEX_ATOMIC_OP + +static __always_inline int +__futex_cmpxchg(u32 __user *uaddr, u32 oldval, u32 newval, u32 *oval) +{ + return __lsui_ll_sc_u_body(futex_cmpxchg, uaddr, oldval, newval, oval); +} =20 static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uad= dr) { - int oldval =3D 0, ret, tmp; - u32 __user *uaddr =3D __uaccess_mask_ptr(_uaddr); + int ret; + u32 __user *uaddr; =20 if (!access_ok(_uaddr, sizeof(u32))) return -EFAULT; =20 + uaddr =3D __uaccess_mask_ptr(_uaddr); + switch (op) { case FUTEX_OP_SET: - __futex_atomic_op("mov %w3, %w5", - ret, oldval, uaddr, tmp, oparg); + ret =3D __futex_atomic_set(oparg, uaddr, oval); break; case FUTEX_OP_ADD: - __futex_atomic_op("add %w3, %w1, %w5", - ret, oldval, uaddr, tmp, oparg); + ret =3D __futex_atomic_add(oparg, uaddr, oval); break; case FUTEX_OP_OR: - __futex_atomic_op("orr %w3, %w1, %w5", - ret, oldval, uaddr, tmp, oparg); + ret =3D __futex_atomic_or(oparg, uaddr, oval); break; case FUTEX_OP_ANDN: - __futex_atomic_op("and %w3, %w1, %w5", - ret, oldval, uaddr, tmp, ~oparg); + ret =3D __futex_atomic_and(~oparg, uaddr, oval); break; case FUTEX_OP_XOR: - __futex_atomic_op("eor %w3, %w1, %w5", - ret, oldval, uaddr, tmp, oparg); + ret =3D __futex_atomic_eor(oparg, uaddr, oval); break; default: ret =3D -ENOSYS; } =20 - if (!ret) - *oval =3D oldval; - return ret; } =20 @@ -81,40 +70,14 @@ static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, u32 oldval, u32 newval) { - int ret =3D 0; - unsigned int loops =3D FUTEX_MAX_LOOPS; - u32 val, tmp; u32 __user *uaddr; =20 if (!access_ok(_uaddr, sizeof(u32))) return -EFAULT; =20 uaddr =3D __uaccess_mask_ptr(_uaddr); - uaccess_enable_privileged(); - asm volatile("// futex_atomic_cmpxchg_inatomic\n" -" prfm pstl1strm, %2\n" -"1: ldxr %w1, %2\n" -" sub %w3, %w1, %w5\n" -" cbnz %w3, 4f\n" -"2: stlxr %w3, %w6, %2\n" -" cbz %w3, 3f\n" -" sub %w4, %w4, %w3\n" -" cbnz %w4, 1b\n" -" mov %w0, %w7\n" -"3:\n" -" dmb ish\n" -"4:\n" - _ASM_EXTABLE_UACCESS_ERR(1b, 4b, %w0) - _ASM_EXTABLE_UACCESS_ERR(2b, 4b, %w0) - : "+r" (ret), "=3D&r" (val), "+Q" (*uaddr), "=3D&r" (tmp), "+r" (loops) - : "r" (oldval), "r" (newval), "Ir" (-EAGAIN) - : "memory"); - uaccess_disable_privileged(); - - if (!ret) - *uval =3D val; =20 - return ret; + return __futex_cmpxchg(uaddr, oldval, newval, uval); } =20 #endif /* __ASM_FUTEX_H */ --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}