From nobody Sat Oct 11 08:22:08 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 663CB273D65; Wed, 11 Jun 2025 10:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749639057; cv=none; b=ZnFqYk+0po0BBs/L9umzvxydnLWontzs4uqaHJeXBO5PJlYeBpuYK2kj/2MQGxnW38mVoMBs2rUicI+hTlcY6LaUXJ/PYq1nmWhBbdfB5gyTWB34h4vuPtIqqhaqU/MpNoW6wBVxXs0xHxg32mQ4amk/2cjfUM9RbqofrLpc5Zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749639057; c=relaxed/simple; bh=GvzHPZjifE6RXrOilsb54DCMNJgZqtRnA56V6ppNJq8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tAfoh6Iz3GXKeXZUocnjaOEJ3i6sWdxDZqB90Vl10XEcfVts8Bdl4tZe6a9Oi9B4sowNNnVm2zcxKVqPqCQQnlsWJHSeSmrk8JKnq0u/CU6jjXh35r0VQBP7Pgp5CsvVGvAZqsjECIjl7Cbedb4VdcHLWm8sm+TWQpzxxOE11Aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70D9626BA; Wed, 11 Jun 2025 03:50:36 -0700 (PDT) Received: from e122027.arm.com (unknown [10.57.67.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D0BF3F673; Wed, 11 Jun 2025 03:50:52 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki Subject: [PATCH v9 31/43] arm_pmu: Provide a mechanism for disabling the physical IRQ Date: Wed, 11 Jun 2025 11:48:28 +0100 Message-ID: <20250611104844.245235-32-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611104844.245235-1-steven.price@arm.com> References: <20250611104844.245235-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Arm CCA assigns the physical PMU device to the guest running in realm world, however the IRQs are routed via the host. To enter a realm guest while a PMU IRQ is pending it is necessary to block the physical IRQ to prevent an immediate exit. Provide a mechanism in the PMU driver for KVM to control the physical IRQ. Signed-off-by: Steven Price --- v3: Add a dummy function for the !CONFIG_ARM_PMU case. --- drivers/perf/arm_pmu.c | 15 +++++++++++++++ include/linux/perf/arm_pmu.h | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 2f33e69a8caf..ae1234001f79 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -733,6 +733,21 @@ static int arm_perf_teardown_cpu(unsigned int cpu, str= uct hlist_node *node) return 0; } =20 +void arm_pmu_set_phys_irq(bool enable) +{ + int cpu =3D get_cpu(); + struct arm_pmu *pmu =3D per_cpu(cpu_armpmu, cpu); + int irq; + + irq =3D armpmu_get_cpu_irq(pmu, cpu); + if (irq && !enable) + per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq); + else if (irq && enable) + per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq); + + put_cpu(); +} + #ifdef CONFIG_CPU_PM static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) { diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 6dc5e0cd76ca..a209de38a01c 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -177,6 +177,7 @@ void kvm_host_pmu_init(struct arm_pmu *pmu); #endif =20 bool arm_pmu_irq_is_nmi(void); +void arm_pmu_set_phys_irq(bool enable); =20 /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); @@ -187,6 +188,10 @@ void armpmu_free_irq(int irq, int cpu); =20 #define ARMV8_PMU_PDEV_NAME "armv8-pmu" =20 +#else /* CONFIG_ARM_PMU */ + +static inline void arm_pmu_set_phys_irq(bool enable) {} + #endif /* CONFIG_ARM_PMU */ =20 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1" --=20 2.43.0