From nobody Sat Oct 11 08:18:41 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CDEA825BEEF; Wed, 11 Jun 2025 10:50:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749639050; cv=none; b=EhxwQ6hDjMYhB0kdMfURLPQ2mgizMIhwk8ax4LAyFtb96p2DFEzoeVR21J1bXmMCc4orGYyU4PVWgrukHOPN4FfA6/DmjqjCx1MbgaacdLoEMxofpGX3xYr6OkDnXwf2ipx+r5izR2erRKyA33r90P+Yw9TosJFuUncUXR87Q8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749639050; c=relaxed/simple; bh=CI8W7LPJxNUEu4tvmMgrxME10yjHMV7jLYjwMAkiH/4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PesIL8Lsr3GFPNIGUJZqwUVdbMwMwGN80tmXngiwTZABKVeOdo6b+l2vox66U3UrEyPdjbhCjPKxwPtY+/G+pAHC9UkUNpqmnsT1oE4yRkG10mFIwnZu6BfpHMlzkv4GkyIQ077i/Frl+ylhr0yZ7o7e2gQ0rVHTBJ6N6jYsX7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D87AA26AC; Wed, 11 Jun 2025 03:50:28 -0700 (PDT) Received: from e122027.arm.com (unknown [10.57.67.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 372FF3F673; Wed, 11 Jun 2025 03:50:45 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki Subject: [PATCH v9 29/43] arm64: RME: Always use 4k pages for realms Date: Wed, 11 Jun 2025 11:48:26 +0100 Message-ID: <20250611104844.245235-30-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250611104844.245235-1-steven.price@arm.com> References: <20250611104844.245235-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Guest_memfd doesn't yet natively support huge pages, and there are currently difficulties for a VMM to manage huge pages efficiently so for now always split up mappings to PTE (4k). The two issues that need progressing before supporting huge pages for realms are: 1. guest_memfd needs to be able to allocate from an appropriate allocator which can provide huge pages. 2. The VMM needs to be able to repurpose private memory for a shared mapping when the guest VM requests memory is transitioned. Because this can happen at a 4k granularity it isn't possible to free/reallocate while huge pages are in use. Allowing the VMM to mmap() the shared portion of a huge page would allow the huge page to be recreated when the memory is unshared and made protected again. These two issues are not specific to realms and don't affect the realm API, so for now just break everything down to 4k pages in the RMM controlled stage 2. Future work can add huge page support without changing the uAPI. Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- Changes since v7: * Rewritten commit message --- arch/arm64/kvm/mmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 1dc644ea26ce..c84847ff5f4d 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1666,6 +1666,10 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phy= s_addr_t fault_ipa, if (logging_active) { force_pte =3D true; vma_shift =3D PAGE_SHIFT; + } else if (vcpu_is_rec(vcpu)) { + /* Force PTE level mappings for realms */ + force_pte =3D true; + vma_shift =3D PAGE_SHIFT; } else { vma_shift =3D get_vma_page_shift(vma, hva); } --=20 2.43.0