From nobody Sat Oct 11 08:30:55 2025 Received: from mail-qt1-f175.google.com (mail-qt1-f175.google.com [209.85.160.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FDCC2367AE; Wed, 11 Jun 2025 08:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749629477; cv=none; b=o48T//i/68Z6Vle1HoU+1jCQIV/qLkdAhPAFb6hIBsAKk4Y55NmOxtfgsyDMTnKQh5o95XFhMil/gQbgfJGIFqJhH8zF2WP5N85f9wrSzFvSQMVdebo/GkIhTsAGf8iPbaSuzOx47Bjw73oQAIEAOaEp9+WguPzkiMwGRQOjxHQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749629477; c=relaxed/simple; bh=l6XeT3LXyFrlrCtT9xgFGVmCHaNUCX0eKWZGqDdqJ9g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u778lCQIha9sw39XEtnWB05h/t+MDy1usVP2K2QFvP7Afe6CZ73N1ikSEEF9ZIJhfvbpinDILGu/T343jB3E1/jgpUzknB16PR3iLt3BDgWlw3xmZX4l8UXmPxREqE4mrmuo+ficeCOtX7bygf+sPqdIITnxYQ9DBESxs0bm778= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EtGw96Xi; arc=none smtp.client-ip=209.85.160.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EtGw96Xi" Received: by mail-qt1-f175.google.com with SMTP id d75a77b69052e-4a4bb155edeso78643371cf.2; Wed, 11 Jun 2025 01:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1749629473; x=1750234273; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=00Y+C1NgJK+RcRNEHyqDxW/VXT0REGuVvjiQNS/nXxY=; b=EtGw96XivaqkJ1NYkVbUDKFB8a4RZCIj4iq0X9hIZ/ano1/CNt2dIYogc6JSGnrmkV 99ddNwLjzzDyY2Rl1atoypPNILA9SVz9NPbSFNizHSMCUh9+zzIlkE5ZGf0DqdtTaY3h +UQL7mRphJW7pevVu78Sq6vz1gixqu6SR0pKxdvkH4feVsawT/85+x816vAQxxn3K3RY 6ei7n3J+eOqpek74t3dptGoIp0JG89TzYKU6MesuHl3eUmsu/lP8MmY0ZOiAEZcuNjB6 yTLkA3CiH8G9jBsxVGzmE+/9knymctJJlqSRvYU7FmjOWuHIucjxJVT1/6bBtcL6Mme+ An1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749629473; x=1750234273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=00Y+C1NgJK+RcRNEHyqDxW/VXT0REGuVvjiQNS/nXxY=; b=VS7RQ+Aposl9lQR+5TC6PPscb75oE4ps5BvktQTjIz6KL/CopvXX3wf3/mHFinCi2Y N0AvVJJDyRYrOEmatADcFcY5eR8ZeNR4EYmmdBgmnLwAQkYBMr6P+JFj5U9clYf4f08Y LqvT/CJ4RMScXnI6F+dA8fpLGQoJEPCxl0Gg7gSkZBlsWu695iEoS8PmRUdVEBKRdRtl yeB0lKb2VlASPvCITy6V7DRaqZzZnD77dkkvVzIGNa398e58KtYF13hsXoPohcFeI3d8 kwKaU9l1ypScfwXj0Q2ndJn8SPb2J52RWx1sMpmgYkVeA2qfyrELpuEMAcyrkmTdMaVA XBCw== X-Forwarded-Encrypted: i=1; AJvYcCVuMgtAYMXkgiApNNsZspYqXeI3XHQoIsiFLlgRaGpQpc+kEqJMyP0LZlXPykizQjLxnt+WlC24L38M7KVa@vger.kernel.org, AJvYcCWOmacq7zzmQB62Pw+5ctGJ2dCOlz1FrZrm9HrzIDfbAHMb7VDU2esaC9nNTXaJEYFprAmXyyDHUhgr@vger.kernel.org X-Gm-Message-State: AOJu0Yx3rnwKq7Cun3Ydy1o1enzniXMprbBYiQ7XKyWBX6WkxXtOlCB/ NCJl4wBND8raGxsKSjRdgvtyDRp3KEM55IuGliTsNN0C59nt4jlQsD60 X-Gm-Gg: ASbGnct8KRii9gyyzq6SB4ZiM068GdKGef16iPshy5M9z92Btk3GWZ/JgrnFF1vKEwO 9yHaVHrAUBRui53DWK+bS2uqxwDT15HfjLRPz0R6QGPP3C/uV+ROtOeQX5Zm73A2eK6u9Mqq+lx 0T34W+/qAzAlRpOQ4AA5Ob5Q7pCKqGJVGoz7TTJyAWP8uZIv4P035G1q+OVKvJYkJI4LA1MFEIF 1EFb6IzuE3aN3qnujMwnrmgB2MNytzRW4M5Jya8ymA2PbOLG+SUwD5kO4K5h6V58PCIw5vtysO6 0Up4NDU16vUlus8/b5ymrXzSdnru2d4QrLLgCGXQMiHIuS/q X-Google-Smtp-Source: AGHT+IH/A2dN7aEwFSvK+XOGHnNd1Ms/qTqK5FFtVoR1qjX6O4PJ9oh2Gq1zA0E/mBczJM+1ZkNyHQ== X-Received: by 2002:a05:622a:4249:b0:4a5:a96d:6068 with SMTP id d75a77b69052e-4a713c5871dmr48328971cf.37.1749629473419; Wed, 11 Jun 2025 01:11:13 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id d75a77b69052e-4a611150018sm85377551cf.8.2025.06.11.01.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 01:11:13 -0700 (PDT) From: Inochi Amaoto To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li , Conor Dooley Subject: [PATCH v14 1/2] dt-bindings: dmaengine: Add dma multiplexer for CV18XX/SG200X series SoC Date: Wed, 11 Jun 2025 16:09:58 +0800 Message-ID: <20250611081000.1187374-2-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611081000.1187374-1-inochiama@gmail.com> References: <20250611081000.1187374-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DMA IP of Sophgo CV18XX/SG200X is based on a DW AXI CORE, with an additional channel remap register located in the top system control area. The DMA channel is exclusive to each core. In addition, the DMA multiplexer is a subdevice of system controller, so this binding only contains necessary properties for the multiplexer itself. Add the dmamux binding for CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto Reviewed-by: Conor Dooley --- .../bindings/dma/sophgo,cv1800b-dmamux.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sophgo,cv1800b-dm= amux.yaml diff --git a/Documentation/devicetree/bindings/dma/sophgo,cv1800b-dmamux.ya= ml b/Documentation/devicetree/bindings/dma/sophgo,cv1800b-dmamux.yaml new file mode 100644 index 000000000000..011002942235 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/sophgo,cv1800b-dmamux.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/sophgo,cv1800b-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800/SG200 Series DMA multiplexer + +maintainers: + - Inochi Amaoto + +description: + The DMA multiplexer of CV1800 is a subdevice of the system + controller. It support mapping 8 channels, but each channel + can be mapped only once. + +allOf: + - $ref: dma-router.yaml# + +properties: + compatible: + const: sophgo,cv1800b-dmamux + + reg: + items: + - description: DMA channal remapping register + - description: DMA channel interrupt mapping register + + '#dma-cells': + const: 2 + description: + The first cells is device id. The second one is the cpu id. + + dma-masters: + maxItems: 1 + +required: + - reg + - '#dma-cells' + - dma-masters + +additionalProperties: false + +examples: + - | + dma-router@154 { + compatible =3D "sophgo,cv1800b-dmamux"; + reg =3D <0x154 0x8>, <0x298 0x4>; + #dma-cells =3D <2>; + dma-masters =3D <&dmac>; + }; --=20 2.49.0 From nobody Sat Oct 11 08:30:55 2025 Received: from mail-qv1-f42.google.com (mail-qv1-f42.google.com [209.85.219.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF89238140; Wed, 11 Jun 2025 08:11:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749629480; cv=none; b=R8mLtDaCM1JI+fwUSnD3L8HHAiMdo5+H4C2Tt5P1V1MhSoGJOpxkUkTLeYXD7nlqdCJSTPlLdV3NVAFDA9XxzPchVAeuS/bvx3Km21iAu9q35H7HUiZcoI9v2zHOT9C1uujrJ3lYvr2UbRSwPfbVDQ059rQjrYJ6D82j7ASbobY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749629480; c=relaxed/simple; bh=wIra1MWBnEI/KsITvp3fLFz69pdc65cdIKDFZs1NPg8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MmXSV45zg3bZWxOTUM9zMkmV3W7YTnwIajGP2LsPBHwwTqeI8YVYPFBLY+pLkMUF1RMweEvvLfxS706Iq6NUQZeiiwv9Fqk+5U5RRuDnuwzCGGyExKhLHHaeklrYE29DlUrg0lDCreO0vqLTXnTmx76GqtmXfJvBuNvna8dwkkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SB1C+Tik; arc=none smtp.client-ip=209.85.219.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SB1C+Tik" Received: by mail-qv1-f42.google.com with SMTP id 6a1803df08f44-6ecf99dd567so78613076d6.0; Wed, 11 Jun 2025 01:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1749629477; x=1750234277; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gfE0nW/hFb6tBNeavOb+VIi0aPnkDiPh5uKKWZJ8u8M=; b=SB1C+TikRCDPlaGyrRjJ2+0g/QTxKu6vHIHZ6KeTLfMOwFEgajKQNMJif0aEEm3kTU MFLNks6Sf8INi+ZNeOdfYxvfng7jOnob/Lcgs94GHkVH9kBBCmjKFuq0EIVbDXu70f1/ kZFSEYKwkBUMf9hMPfN32rrV8jt1D5qdf1aAKmaQdIVWOUxDxxDo8v/3huXwGbAvvHbj TBnSzbP1MrHar7UvTayRgotfniSSFB2CCrs25YlyE6P7h8BNSLT2GHic/am0e+/BP2Tx 1nJuzG4UTh+mmUz90uA/L9EAlNLHYFWxvLCCdga3fir5a12lYdMFpQzYybbsZc6QBj6v q27g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749629477; x=1750234277; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfE0nW/hFb6tBNeavOb+VIi0aPnkDiPh5uKKWZJ8u8M=; b=UAklTVxZ4faSR/q4ftNmHnG26hVeByaaj/U8a5VeoFMUeenr+pkUilKP6a6Tdth3AM Szpd45Ahch3mJg3/QZhKni8fJ/PyrYSc4iOhCqAW/WldjG4hkAhfq51BoezkmVcTOcTQ G2VAFko2eeWSdowzpTbCktbvULrBYLFjPV3toEe8aQbnCa+w4QBcngWvomeAdiqFo3C7 +tKQ8OrHPy9vbBlc7B9YYx0/n5jzAymlcHci5cjoSHSOFeMNlpvuyRXV0+QJdxQi1Ym9 6tUdaA/A/SDwLDPyBlQri0PoPOabRvklkAZ6n8PKwqH7yvk37i03UmEamVvGxbWRbqiv nlrQ== X-Forwarded-Encrypted: i=1; AJvYcCUXceSDXBjY1CeM4vknItC6pHG0iH7VJNyEnWHxmyTXhPj/lfG0Pa7+eoBSQcNXvg0M/CKPkbAJANaqo3IC@vger.kernel.org, AJvYcCXFZhlPtDCuiEjUwHbA2yFKifGHpo7lUpB9AiiKEDPZFpJ3wDRVzDMD1r4wTN1lzVFCiAoNraEF7BEi@vger.kernel.org X-Gm-Message-State: AOJu0Yz0bDMuVkhB5vToT/g/G+Wo84VimnR2eYSNCkkjjhrSsI5Q6p46 8uha3NnHtCl5q1nQi6s6MjsyAB72w+H8AiI0myCOYmllA5TdM60ohlX7 X-Gm-Gg: ASbGncuHnZZwcm0IGFCAoCfGTFOF2q7h60PegRZEFT/oy82s2F+yc+uHmGxOGHKZSOf 9pwvSLdzV0GGLVen29Xkc9n4fT93VCdiz+FdF2PCApNcB8VkDZaHoBNgo1Pjda7MeazotYnE1l1 guCpfFNU319YW56koWkxKlrgYxaVZVt70CrhYaetaOPQJOA4KEz1MwdnkadHZkboEDkRtIgsecv /1MRwfpFIK/BkfZsvH7jgLrzHW1WyOK07lwbPVa214uuG51cuZ4Rbz9/CFoCR665cZKcE3UGT11 bFNhnDxTNhPNe+vvQUuFjR0DTxY/uj6505PtrQ== X-Google-Smtp-Source: AGHT+IHJOgJ0+i6Fm4WsVk6l97AdazJZq4HORq5uZJ9u5vD7oiYxkJmbd9sBY+uytt5GSpvDEFY+hQ== X-Received: by 2002:a05:6214:2343:b0:6fa:9f9b:8df0 with SMTP id 6a1803df08f44-6fb2c365ccemr41834396d6.20.1749629476688; Wed, 11 Jun 2025 01:11:16 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id 6a1803df08f44-6fb09b1ce2csm78828286d6.56.2025.06.11.01.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 01:11:16 -0700 (PDT) From: Inochi Amaoto To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH v14 2/2] dmaengine: add driver for Sophgo CV18XX/SG200X dmamux Date: Wed, 11 Jun 2025 16:09:59 +0800 Message-ID: <20250611081000.1187374-3-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611081000.1187374-1-inochiama@gmail.com> References: <20250611081000.1187374-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sophgo CV18XX/SG200X use DW AXI CORE with a multiplexer for remapping its request lines. The multiplexer supports at most 8 request lines. Add driver for Sophgo CV18XX/SG200X DMA multiplexer. Signed-off-by: Inochi Amaoto Tested-by: Alexander Sverdlin --- drivers/dma/Kconfig | 9 ++ drivers/dma/Makefile | 1 + drivers/dma/cv1800b-dmamux.c | 259 +++++++++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/dma/cv1800b-dmamux.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index db87dd2a07f7..5d81e34f8e1f 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -572,6 +572,15 @@ config PLX_DMA These are exposed via extra functions on the switch's upstream port. Each function exposes one DMA channel. =20 +config SOPHGO_CV1800B_DMAMUX + tristate "Sophgo CV1800/SG2000 series SoC DMA multiplexer support" + depends on MFD_SYSCON + depends on ARCH_SOPHGO || COMPILE_TEST + help + Support for the DMA multiplexer on Sophgo CV1800/SG2000 + series SoCs. + Say Y here if your board have this soc. + config STE_DMA40 bool "ST-Ericsson DMA40 support" depends on ARCH_U8500 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index ba9732644752..a54d7688392b 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_PPC_BESTCOMM) +=3D bestcomm/ obj-$(CONFIG_PXA_DMA) +=3D pxa_dma.o obj-$(CONFIG_RENESAS_DMA) +=3D sh/ obj-$(CONFIG_SF_PDMA) +=3D sf-pdma/ +obj-$(CONFIG_SOPHGO_CV1800B_DMAMUX) +=3D cv1800b-dmamux.o obj-$(CONFIG_STE_DMA40) +=3D ste_dma40.o ste_dma40_ll.o obj-$(CONFIG_SPRD_DMA) +=3D sprd-dma.o obj-$(CONFIG_TXX9_DMAC) +=3D txx9dmac.o diff --git a/drivers/dma/cv1800b-dmamux.c b/drivers/dma/cv1800b-dmamux.c new file mode 100644 index 000000000000..e900d6595617 --- /dev/null +++ b/drivers/dma/cv1800b-dmamux.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Inochi Amaoto + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_DMA_CHANNEL_REMAP0 0x154 +#define REG_DMA_CHANNEL_REMAP1 0x158 +#define REG_DMA_INT_MUX 0x298 + +#define DMAMUX_NCELLS 2 +#define MAX_DMA_MAPPING_ID 42 +#define MAX_DMA_CPU_ID 2 +#define MAX_DMA_CH_ID 7 + +#define DMAMUX_INTMUX_REGISTER_LEN 4 +#define DMAMUX_NR_CH_PER_REGISTER 4 +#define DMAMUX_BIT_PER_CH 8 +#define DMAMUX_CH_MASk GENMASK(5, 0) +#define DMAMUX_INT_BIT_PER_CPU 10 +#define DMAMUX_CH_UPDATE_BIT BIT(31) + +#define DMAMUX_CH_REGPOS(chid) \ + ((chid) / DMAMUX_NR_CH_PER_REGISTER) +#define DMAMUX_CH_REGOFF(chid) \ + ((chid) % DMAMUX_NR_CH_PER_REGISTER) +#define DMAMUX_CH_REG(chid) \ + ((DMAMUX_CH_REGPOS(chid) * sizeof(u32)) + \ + REG_DMA_CHANNEL_REMAP0) +#define DMAMUX_CH_SET(chid, val) \ + (((val) << (DMAMUX_CH_REGOFF(chid) * DMAMUX_BIT_PER_CH)) | \ + DMAMUX_CH_UPDATE_BIT) +#define DMAMUX_CH_MASK(chid) \ + DMAMUX_CH_SET(chid, DMAMUX_CH_MASk) + +#define DMAMUX_INT_BIT(chid, cpuid) \ + BIT((cpuid) * DMAMUX_INT_BIT_PER_CPU + (chid)) +#define DMAMUX_INTEN_BIT(cpuid) \ + DMAMUX_INT_BIT(8, cpuid) +#define DMAMUX_INT_CH_BIT(chid, cpuid) \ + (DMAMUX_INT_BIT(chid, cpuid) | DMAMUX_INTEN_BIT(cpuid)) +#define DMAMUX_INT_MASK(chid) \ + (DMAMUX_INT_BIT(chid, 0) | \ + DMAMUX_INT_BIT(chid, 1) | \ + DMAMUX_INT_BIT(chid, 2)) +#define DMAMUX_INT_CH_MASK(chid, cpuid) \ + (DMAMUX_INT_MASK(chid) | DMAMUX_INTEN_BIT(cpuid)) + +struct cv1800_dmamux_data { + struct dma_router dmarouter; + struct regmap *regmap; + spinlock_t lock; + struct llist_head free_maps; + struct llist_head reserve_maps; + DECLARE_BITMAP(mapped_peripherals, MAX_DMA_MAPPING_ID); +}; + +struct cv1800_dmamux_map { + struct llist_node node; + unsigned int channel; + unsigned int peripheral; + unsigned int cpu; +}; + +static void cv1800_dmamux_free(struct device *dev, void *route_data) +{ + struct cv1800_dmamux_data *dmamux =3D dev_get_drvdata(dev); + struct cv1800_dmamux_map *map =3D route_data; + + guard(spinlock_irqsave)(&dmamux->lock); + + regmap_update_bits(dmamux->regmap, + DMAMUX_CH_REG(map->channel), + DMAMUX_CH_MASK(map->channel), + DMAMUX_CH_UPDATE_BIT); + + regmap_update_bits(dmamux->regmap, REG_DMA_INT_MUX, + DMAMUX_INT_CH_MASK(map->channel, map->cpu), + DMAMUX_INTEN_BIT(map->cpu)); + + dev_dbg(dev, "free channel %u for req %u (cpu %u)\n", + map->channel, map->peripheral, map->cpu); +} + +static void *cv1800_dmamux_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct platform_device *pdev =3D of_find_device_by_node(ofdma->of_node); + struct cv1800_dmamux_data *dmamux =3D platform_get_drvdata(pdev); + struct cv1800_dmamux_map *map; + struct llist_node *node; + unsigned long flags; + unsigned int chid, devid, cpuid; + int ret; + + if (dma_spec->args_count !=3D DMAMUX_NCELLS) { + dev_err(&pdev->dev, "invalid number of dma mux args\n"); + return ERR_PTR(-EINVAL); + } + + devid =3D dma_spec->args[0]; + cpuid =3D dma_spec->args[1]; + dma_spec->args_count =3D 1; + + if (devid > MAX_DMA_MAPPING_ID) { + dev_err(&pdev->dev, "invalid device id: %u\n", devid); + return ERR_PTR(-EINVAL); + } + + if (cpuid > MAX_DMA_CPU_ID) { + dev_err(&pdev->dev, "invalid cpu id: %u\n", cpuid); + return ERR_PTR(-EINVAL); + } + + dma_spec->np =3D of_parse_phandle(ofdma->of_node, "dma-masters", 0); + if (!dma_spec->np) { + dev_err(&pdev->dev, "can't get dma master\n"); + return ERR_PTR(-EINVAL); + } + + spin_lock_irqsave(&dmamux->lock, flags); + + if (test_bit(devid, dmamux->mapped_peripherals)) { + llist_for_each_entry(map, dmamux->reserve_maps.first, node) { + if (map->peripheral =3D=3D devid && map->cpu =3D=3D cpuid) + goto found; + } + + ret =3D -EINVAL; + goto failed; + } else { + node =3D llist_del_first(&dmamux->free_maps); + if (!node) { + ret =3D -ENODEV; + goto failed; + } + + map =3D llist_entry(node, struct cv1800_dmamux_map, node); + llist_add(&map->node, &dmamux->reserve_maps); + set_bit(devid, dmamux->mapped_peripherals); + } + +found: + chid =3D map->channel; + map->peripheral =3D devid; + map->cpu =3D cpuid; + + regmap_set_bits(dmamux->regmap, + DMAMUX_CH_REG(chid), + DMAMUX_CH_SET(chid, devid)); + + regmap_update_bits(dmamux->regmap, REG_DMA_INT_MUX, + DMAMUX_INT_CH_MASK(chid, cpuid), + DMAMUX_INT_CH_BIT(chid, cpuid)); + + spin_unlock_irqrestore(&dmamux->lock, flags); + + dma_spec->args[0] =3D chid; + + dev_dbg(&pdev->dev, "register channel %u for req %u (cpu %u)\n", + chid, devid, cpuid); + + return map; + +failed: + spin_unlock_irqrestore(&dmamux->lock, flags); + of_node_put(dma_spec->np); + dev_err(&pdev->dev, "errno %d\n", ret); + return ERR_PTR(ret); +} + +static int cv1800_dmamux_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *mux_node =3D dev->of_node; + struct cv1800_dmamux_data *data; + struct cv1800_dmamux_map *tmp; + struct device *parent =3D dev->parent; + struct regmap *regmap =3D NULL; + unsigned int i; + + if (!parent) + return -ENODEV; + + regmap =3D device_node_to_regmap(parent->of_node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + spin_lock_init(&data->lock); + init_llist_head(&data->free_maps); + init_llist_head(&data->reserve_maps); + + for (i =3D 0; i <=3D MAX_DMA_CH_ID; i++) { + tmp =3D devm_kmalloc(dev, sizeof(*tmp), GFP_KERNEL); + if (!tmp) { + /* It is OK for not allocating all channel */ + dev_warn(dev, "can not allocate channel %u\n", i); + continue; + } + + init_llist_node(&tmp->node); + tmp->channel =3D i; + llist_add(&tmp->node, &data->free_maps); + } + + /* if no channel is allocated, the probe must fail */ + if (llist_empty(&data->free_maps)) + return -ENOMEM; + + data->regmap =3D regmap; + data->dmarouter.dev =3D dev; + data->dmarouter.route_free =3D cv1800_dmamux_free; + + platform_set_drvdata(pdev, data); + + return of_dma_router_register(mux_node, + cv1800_dmamux_route_allocate, + &data->dmarouter); +} + +static void cv1800_dmamux_remove(struct platform_device *pdev) +{ + of_dma_controller_free(pdev->dev.of_node); +} + +static const struct of_device_id cv1800_dmamux_ids[] =3D { + { .compatible =3D "sophgo,cv1800b-dmamux", }, + { } +}; +MODULE_DEVICE_TABLE(of, cv1800_dmamux_ids); + +static struct platform_driver cv1800_dmamux_driver =3D { + .probe =3D cv1800_dmamux_probe, + .remove =3D cv1800_dmamux_remove, + .driver =3D { + .name =3D "cv1800-dmamux", + .of_match_table =3D cv1800_dmamux_ids, + }, +}; +module_platform_driver(cv1800_dmamux_driver); + +MODULE_AUTHOR("Inochi Amaoto "); +MODULE_DESCRIPTION("Sophgo CV1800/SG2000 Series SoC DMAMUX driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0