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Wed, 11 Jun 2025 00:54:44 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id af79cd13be357-7d25a60a1dbsm822918885a.56.2025.06.11.00.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 00:54:44 -0700 (PDT) From: Inochi Amaoto To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vinod Koul , Alexander Sverdlin , Yu Yuan , Ze Huang , Thomas Bonnefille Cc: Junhui Liu , devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dmaengine@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v3 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC Date: Wed, 11 Jun 2025 15:53:18 +0800 Message-ID: <20250611075321.1160973-5-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250611075321.1160973-1-inochiama@gmail.com> References: <20250611075321.1160973-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add known reset configuration for existed device. Signed-off-by: Inochi Amaoto Reviewed-by: Alexander Sverdlin --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv180x.dtsi index 4c3d16764131..e91bb512b099 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -36,6 +36,7 @@ gpio0: gpio@3020000 { reg =3D <0x3020000 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + resets =3D <&rst RST_GPIO0>; =20 porta: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -54,6 +55,7 @@ gpio1: gpio@3021000 { reg =3D <0x3021000 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + resets =3D <&rst RST_GPIO1>; =20 portb: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -72,6 +74,7 @@ gpio2: gpio@3022000 { reg =3D <0x3022000 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + resets =3D <&rst RST_GPIO2>; =20 portc: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -90,6 +93,7 @@ gpio3: gpio@3023000 { reg =3D <0x3023000 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; + resets =3D <&rst RST_GPIO3>; =20 portd: gpio-controller@0 { compatible =3D "snps,dw-apb-gpio-port"; @@ -133,6 +137,7 @@ i2c0: i2c@4000000 { clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names =3D "ref", "pclk"; interrupts =3D ; + resets =3D <&rst RST_I2C0>; status =3D "disabled"; }; =20 @@ -144,6 +149,7 @@ i2c1: i2c@4010000 { clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names =3D "ref", "pclk"; interrupts =3D ; + resets =3D <&rst RST_I2C1>; status =3D "disabled"; }; =20 @@ -155,6 +161,7 @@ i2c2: i2c@4020000 { clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names =3D "ref", "pclk"; interrupts =3D ; + resets =3D <&rst RST_I2C2>; status =3D "disabled"; }; =20 @@ -166,6 +173,7 @@ i2c3: i2c@4030000 { clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names =3D "ref", "pclk"; interrupts =3D ; + resets =3D <&rst RST_I2C3>; status =3D "disabled"; }; =20 @@ -177,6 +185,7 @@ i2c4: i2c@4040000 { clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names =3D "ref", "pclk"; interrupts =3D ; + resets =3D <&rst RST_I2C4>; status =3D "disabled"; }; =20 @@ -188,6 +197,7 @@ uart0: serial@4140000 { clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; + resets =3D <&rst RST_UART0>; status =3D "disabled"; }; =20 @@ -199,6 +209,7 @@ uart1: serial@4150000 { clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; + resets =3D <&rst RST_UART1>; status =3D "disabled"; }; =20 @@ -210,6 +221,7 @@ uart2: serial@4160000 { clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; + resets =3D <&rst RST_UART2>; status =3D "disabled"; }; =20 @@ -221,6 +233,7 @@ uart3: serial@4170000 { clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; + resets =3D <&rst RST_UART3>; status =3D "disabled"; }; =20 @@ -232,6 +245,7 @@ spi0: spi@4180000 { clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names =3D "ssi_clk", "pclk"; interrupts =3D ; + resets =3D <&rst RST_SPI0>; status =3D "disabled"; }; =20 @@ -243,6 +257,7 @@ spi1: spi@4190000 { clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names =3D "ssi_clk", "pclk"; interrupts =3D ; + resets =3D <&rst RST_SPI1>; status =3D "disabled"; }; =20 @@ -254,6 +269,7 @@ spi2: spi@41a0000 { clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names =3D "ssi_clk", "pclk"; interrupts =3D ; + resets =3D <&rst RST_SPI2>; status =3D "disabled"; }; =20 @@ -265,6 +281,7 @@ spi3: spi@41b0000 { clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names =3D "ssi_clk", "pclk"; interrupts =3D ; + resets =3D <&rst RST_SPI3>; status =3D "disabled"; }; =20 @@ -276,6 +293,7 @@ uart4: serial@41c0000 { clock-names =3D "baudclk", "apb_pclk"; reg-shift =3D <2>; reg-io-width =3D <4>; + resets =3D <&rst RST_UART4>; status =3D "disabled"; }; =20 --=20 2.49.0