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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2025 18:01:25.6280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e88511e-0d48-4443-4205-08dda848d129 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9146 Content-Type: text/plain; charset="utf-8" Use 'regs' as a contiguous linear bitmap in apic_{set| clear|test}_vector() while doing bitwise operations. This makes the code simpler by eliminating the need to determine the offset of the 32-bit register and the vector bit location within that register prior to performing bitwise operations. This change results in slight increase in generated code size for gcc-14.2. - Without change apic_set_vector: 89 f8 mov %edi,%eax 83 e7 1f and $0x1f,%edi c1 e8 05 shr $0x5,%eax c1 e0 04 shl $0x4,%eax 48 01 c6 add %rax,%rsi f0 48 0f ab 3e lock bts %rdi,(%rsi) c3 ret - With change apic_set_vector: 89 f8 mov %edi,%eax c1 e8 05 shr $0x5,%eax 8d 04 40 lea (%rax,%rax,2),%eax c1 e0 05 shl $0x5,%eax 01 f8 add %edi,%eax 89 c0 mov %eax,%eax f0 48 0f ab 3e lock bts %rax,(%rsi) c3 ret But, lapic.o text size (bytes) decreases with this change: Obj Old-size New-size lapic.o 28832 28768 Signed-off-by: Neeraj Upadhyay --- Changes since v6: - Converted assmebly to AT&T format. - Added information about overall kvm.ko text size change. arch/x86/include/asm/apic.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index b7cbe9ba363e..f91d23757375 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -564,19 +564,28 @@ static __always_inline void apic_set_reg64(void *regs= , int reg, u64 val) ap->regs64[reg / 8] =3D val; } =20 +static inline unsigned int get_vec_bit(unsigned int vec) +{ + /* + * The registers are 32-bit wide and 16-byte aligned. + * Compensate for the resulting bit number spacing. + */ + return vec + 96 * (vec / 32); +} + static inline void apic_clear_vector(int vec, void *bitmap) { - clear_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFF= SET(vec)); + clear_bit(get_vec_bit(vec), bitmap); } =20 static inline void apic_set_vector(int vec, void *bitmap) { - set_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSE= T(vec)); + set_bit(get_vec_bit(vec), bitmap); } =20 static inline int apic_test_vector(int vec, void *bitmap) { - return test_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_R= EG_OFFSET(vec)); + return test_bit(get_vec_bit(vec), bitmap); } =20 /* --=20 2.34.1