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Tue, 10 Jun 2025 10:22:04 -0700 Received: from fedora.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 10 Jun 2025 10:22:00 -0700 From: Carolina Jubran To: Richard Cochran , Andrew Lunn , "David S. Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni CC: Gal Pressman , Tariq Toukan , "Bar Shapira" , Maciek Machnikowski , Wojtek Wasko , Vinicius Costa Gomes , Vadim Fedorenko , Mahesh Bandewar , , , Carolina Jubran Subject: [RFC PATCH] ptp: extend offset ioctls to expose raw free-running cycles Date: Tue, 10 Jun 2025 20:19:05 +0300 Message-ID: <20250610171905.4042496-1-cjubran@nvidia.com> X-Mailer: git-send-email 2.38.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|BN7PPF8FCE094C0:EE_ X-MS-Office365-Filtering-Correlation-Id: 41656c01-6c3f-400a-28ff-08dda8435f58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?eEdvMTdmTUVxZFF0RElGbUtVMjJwKzladEhZVXdUMTFBWmYyd1NwRzdEYTIy?= =?utf-8?B?WHRXb0tkUkR0WDBZTzA1RmdKQTJVR0FDdS85TktYVXBXSDV4SkxzaWUrQTJG?= =?utf-8?B?N0NmWFJCais3RGpCVnE4YVFweUVTUkh1NndpZnNqTGNPZER3RmRSamlUZlU3?= =?utf-8?B?cFdQTklkcUtUaUU3NEIyVUt4UllkZzBRZ1BVUVhZTk95dGF1SVFkL3Z4azZ2?= =?utf-8?B?UEFiVS8wQzFkUTRPSDB4YUVETDBzdmpIZEJxL0hEdURDU3h6YlFNOVRUNGtN?= =?utf-8?B?R0IyNWZDc0tPNkQ5ZnJ6WUlhcG5EMEdQYWJRNDJpbWhTRnhTbGhNNmJLVDBm?= =?utf-8?B?U2ZSb1JVZ3ZTRG5FRUxqMTJhcFdKdlhGVk9PQzdZZnZweVI2L3NRNWcrS3hj?= =?utf-8?B?d0REd2NHUXMvd3phZ0ZNdStMZFF0bFBCS2ZSanFmTGRMOHdJUzhQQ2x0VGwr?= =?utf-8?B?aUo0UUZIY1kxVHlycnd2Uko5cmt3S0ZDaHZJbWJGSmU4d1pRdG1QOXYzMEJr?= =?utf-8?B?MzNwbXJqMU1DNU96ZnBURlVnOGdoc3ZaaXl1eDNudHo3YlhuaWVYNjdxNkJU?= =?utf-8?B?NSt5cDJSVGk1SzEvdVE3UU5XOVVrVXdZdjVNN2paWGlpdjRoTzJUWXh2NHBE?= =?utf-8?B?MXN4YzBoazQ0OFpmQTlxcjg1cFZJUHBOSWZicXllNVpYMjAxb0kzMXBPQjJD?= =?utf-8?B?NUhVSmxsTHlrYVllS0pobTRmeVluTlBXMXk3QzFaOWtLazRDZWQxNXhaUEF4?= =?utf-8?B?YWk0enFqLzRzVlZrT0RITzFFSENHeDV3bzk1L2pNcTkveWV6OE95VCsvcENE?= =?utf-8?B?MWJ5bVNIWFY2VExacHFwNXpBVmQ0VnE3elFNRzliZ0lobmhmK05CeVYwNi9o?= =?utf-8?B?MXJIbVJYbEdwY1NXMjFKK2xvaTNwYXBhK1NQUDJvbFFKMXBJS2ZtZGx4eHJt?= =?utf-8?B?ZmkxaUlQNVFnOEh6WXBKWnN0Z01kVUZ6ZzRmS2pqUTlmNlplN2twQmFsR0FI?= =?utf-8?B?VFQyS1N2Y1J6ZjhUczVxQko3a3U5cUpOMytkV0gxNXVKcG9iUWQ0UUdKN1Vv?= =?utf-8?B?SmZ0dHJXNTc1TFhHbnVhLzZDdkZjMHdWamUzRlorQytmT2FldlVxd295T1FF?= =?utf-8?B?VVNuSjVmOWxqVFRJWHRORnBMTE9tVEh0UmJIVDVrZlMzZllyTEQvamw1NUhT?= =?utf-8?B?U2N2RTBhRGJIUVdQbWI3UDhocXNnSDdSQytNWm82d0liU1BGM1BnZTdqUXJ0?= =?utf-8?B?Si90SjBhUjFHZmQ3cDVVTE9YajZrUG1MdFNaRVhJVktRMFptVnNIaHlWSU81?= =?utf-8?B?WC9LbFdWMnA5VkdBYzRwRUxnbVZ1STVKcWMva0tGVVU0NlBPSjZKOHgybE1l?= =?utf-8?B?VEZPNnZMMktPNVJlcGRhTW5BcXNTb1g0d0k5cVc1OEMyZWRzVmFKRXF0eUdv?= =?utf-8?B?OWRJajJMRGVlazRQWDBvYURNbkdmVXUveVlRYWFSS2VISjdzMkp3VnRSSDBH?= =?utf-8?B?UVhLSjJsRUNBRmlEZldBUjVMQkRWb20ybHEzYW5kU3Y5OUZFOGJjUHJTQU5p?= =?utf-8?B?OXFQT3VmNUd1MldrSDFDdFZGVUk1dXJzSFcxZjF5S2hxMnUzcjJYbnlTMHIv?= =?utf-8?B?aG9BdGRzT3VLVWRuVFdRVEJ2RGJQVFBjbS9FL2tOVkY1UkdkYVhBWnZpV0FO?= =?utf-8?B?cHpLZFdXMUZia0YzeW5UbjV1RUFFa2Y5d2hndUVIeXk4TlBwYUdEVXRLNWpn?= =?utf-8?B?N1VSVVdyMnlKSnFpaW9GVXlrTC92bXpoOXJZblF2RFhXSmErM1pISnU5bElQ?= =?utf-8?B?OHZqYXgxb3NiMnAwVGtPZlBRVEZkbE03a3RGMFdqY2lMRDByRUl0RTZodnhQ?= =?utf-8?B?K3YweVdTZWc4U2o2eVNvUk1sM0o2dEVEK241Y2Q0Z2lkMUUzWWljTXlDRjJE?= =?utf-8?B?WFZyZjlUNTdnWEJOWU1mZXZkL0w1ck41Z2pZcG8wd09FZm15eDlrTGc0Q29i?= =?utf-8?B?Z05HNmNvNCswUVhUZ0FMcnJoTVJiSklYLzFUSXBHLzZzSjFqUXFiQ1V1NE43?= =?utf-8?Q?JFssE6?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2025 17:22:27.0325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41656c01-6c3f-400a-28ff-08dda8435f58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF8FCE094C0 Some telemetry and low-level event logging applications use hardware timestamps reported in raw cycle counter units. There is currently no generic way in user space to correlate such raw cycle values with system time. This patch adds support for returning the raw free-running counter value from the device, alongside system timestamps. It introduces a new flag, PTP_OFFSET_CYCLES, which can be set in PTP_SYS_OFFSET_EXTENDED2 or PTP_SYS_OFFSET_PRECISE2 ioctl calls. When this flag is set, the driver is expected to return a raw cycle counter value rather than a nanosecond timestamp. This is useful for offline correlation and debugging. This can also be useful in XDP. Some drivers already insert timestamps into XDP metadata. If we allow them to insert the raw cycle counter instead of converting it to nanoseconds, this could reduce overhead in the fast path. The raw value can then be translated in user space using this ioctl when needed. While reviewing the current usage of getcyclesx64(), I noticed that ptp_vclock expects it to return a timestamp as a timespec64 that represents a nanosecond-based value. This is then passed through timespec64_to_ns() before being used with timecounter_cyc2time(). However, in the Intel igc driver (igc_ptp_getcyclesx64()), the timestamp is read directly from hardware registers into tv_sec and tv_nsec. Is this value already formatted as a proper nanosecond-based timestamp, or is it a raw hardware format? Just wondering if this is expected behavior, or if it might be a bug? We=E2=80=99ll appreciate any feedback. Signed-off-by: Carolina Jubran --- drivers/ptp/ptp_chardev.c | 41 +++++++++++++++++++++++++++++----- include/uapi/linux/ptp_clock.h | 41 +++++++++++++++++++++++++++++----- 2 files changed, 72 insertions(+), 10 deletions(-) diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index 4bf421765d03..c810b694de11 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -176,6 +176,7 @@ long ptp_ioctl(struct posix_clock_context *pccontext, u= nsigned int cmd, struct ptp_pin_desc pd; struct timespec64 ts; int enable, err =3D 0; + bool cycles; =20 if (in_compat_syscall() && cmd !=3D PTP_ENABLE_PPS && cmd !=3D PTP_ENABLE= _PPS2) arg =3D (unsigned long)compat_ptr(arg); @@ -354,11 +355,30 @@ long ptp_ioctl(struct posix_clock_context *pccontext,= unsigned int cmd, =20 case PTP_SYS_OFFSET_PRECISE: case PTP_SYS_OFFSET_PRECISE2: - if (!ptp->info->getcrosststamp) { + if (!ptp->info->getcrosststamp || !ptp->info->getcrosscycles) { err =3D -EOPNOTSUPP; break; } - err =3D ptp->info->getcrosststamp(ptp->info, &xtstamp); + if (copy_from_user(&precise_offset, (void __user *)arg, + sizeof(precise_offset))) { + err =3D -EFAULT; + break; + } + + if ((cmd =3D=3D PTP_SYS_OFFSET_PRECISE2 && + (precise_offset.rsv[0] & ~PTP_OFFSET_PRECISE_VALID_FLAGS)) || + (cmd =3D=3D PTP_SYS_OFFSET_PRECISE && + (precise_offset.rsv[0] & ~PTP_OFFSET_PRECISE_V1_VALID_FLAGS)) || + precise_offset.rsv[1]) { + err =3D -EINVAL; + break; + } + + cycles =3D !!(precise_offset.rsv[0] & PTP_OFFSET_CYCLES); + if (cycles) + err =3D ptp->info->getcrosscycles(ptp->info, &xtstamp); + else + err =3D ptp->info->getcrosststamp(ptp->info, &xtstamp); if (err) break; =20 @@ -379,7 +399,7 @@ long ptp_ioctl(struct posix_clock_context *pccontext, u= nsigned int cmd, =20 case PTP_SYS_OFFSET_EXTENDED: case PTP_SYS_OFFSET_EXTENDED2: - if (!ptp->info->gettimex64) { + if (!ptp->info->gettimex64 || !ptp->info->getcyclesx64) { err =3D -EOPNOTSUPP; break; } @@ -389,8 +409,13 @@ long ptp_ioctl(struct posix_clock_context *pccontext, = unsigned int cmd, extoff =3D NULL; break; } + if (extoff->n_samples > PTP_MAX_SAMPLES || - extoff->rsv[0] || extoff->rsv[1] || + (cmd =3D=3D PTP_SYS_OFFSET_EXTENDED2 && + (extoff->rsv[0] & ~PTP_OFFSET_EXTENDED_VALID_FLAGS)) || + (cmd =3D=3D PTP_SYS_OFFSET_EXTENDED && + (extoff->rsv[0] & ~PTP_OFFSET_EXTENDED_V1_VALID_FLAGS)) || + extoff->rsv[1] || (extoff->clockid !=3D CLOCK_REALTIME && extoff->clockid !=3D CLOCK_MONOTONIC && extoff->clockid !=3D CLOCK_MONOTONIC_RAW)) { @@ -398,8 +423,14 @@ long ptp_ioctl(struct posix_clock_context *pccontext, = unsigned int cmd, break; } sts.clockid =3D extoff->clockid; + cycles =3D !!(extoff->rsv[0] & PTP_OFFSET_CYCLES); for (i =3D 0; i < extoff->n_samples; i++) { - err =3D ptp->info->gettimex64(ptp->info, &ts, &sts); + if (cycles) + err =3D ptp->info->getcyclesx64(ptp->info, &ts, + &sts); + else + err =3D ptp->info->gettimex64(ptp->info, &ts, + &sts); if (err) goto out; extoff->ts[i][0].sec =3D sts.pre_ts.tv_sec; diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h index 18eefa6d93d6..eaf58e17fdb4 100644 --- a/include/uapi/linux/ptp_clock.h +++ b/include/uapi/linux/ptp_clock.h @@ -25,6 +25,31 @@ #include #include =20 +/* + * Bits of the ptp_sys_offset.flags field: + */ +#define PTP_OFFSET_CYCLES (1<<0) /* Use cycles instead of timestamps */ + +/* + * flag fields valid for the PTP_SYS_OFFSET_EXTENDED2 ioctl. + */ +#define PTP_OFFSET_EXTENDED_VALID_FLAGS (PTP_OFFSET_CYCLES) + +/* + * No flags are valid for the original PTP_SYS_OFFSET_EXTENDED ioctl + */ +#define PTP_OFFSET_EXTENDED_V1_VALID_FLAGS (0) + +/* + * flag fields valid for the PTP_SYS_OFFSET_PRECISE2 ioctl. + */ +#define PTP_OFFSET_PRECISE_VALID_FLAGS (PTP_OFFSET_CYCLES) + +/* + * No flags are valid for the original PTP_SYS_OFFSET_PRECISE ioctl + */ +#define PTP_OFFSET_PRECISE_V1_VALID_FLAGS (0) + /* * Bits of the ptp_extts_request.flags field: */ @@ -86,9 +111,15 @@ * */ struct ptp_clock_time { - __s64 sec; /* seconds */ - __u32 nsec; /* nanoseconds */ - __u32 reserved; + union { + struct { + __s64 sec; /* seconds */ + __u32 nsec; /* nanoseconds */ + __u32 reserved; + }; + __u64 cycles; + }; + }; =20 struct ptp_clock_caps { @@ -173,7 +204,7 @@ struct ptp_sys_offset { struct ptp_sys_offset_extended { unsigned int n_samples; __kernel_clockid_t clockid; - unsigned int rsv[2]; + unsigned int rsv[2]; /* rsv[0] is used for PTP_OFFSET_FLAG_CYCLES */ struct ptp_clock_time ts[PTP_MAX_SAMPLES][3]; }; =20 @@ -181,7 +212,7 @@ struct ptp_sys_offset_precise { struct ptp_clock_time device; struct ptp_clock_time sys_realtime; struct ptp_clock_time sys_monoraw; - unsigned int rsv[4]; /* Reserved for future use. */ + unsigned int rsv[4]; /* rsv[0] is used for PTP_OFFSET_FLAG_CYCLES */ }; =20 enum ptp_pin_function { --=20 2.38.1