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Tue, 10 Jun 2025 09:02:22 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Frank Li , Marco Felsch , Marc Kleine-Budde , Alexander Stein Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/6] dt-bindings: bus: document the IMX AIPSTZ bridge Date: Tue, 10 Jun 2025 12:01:47 -0400 Message-Id: <20250610160152.1113930-2-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> References: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Add documentation for IMX AIPSTZ bridge. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Rob Herring (Arm) --- .../bindings/bus/fsl,imx8mp-aipstz.yaml | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz= .yaml diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml b= /Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml new file mode 100644 index 000000000000..993293ebc4d3 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Secure AHB to IP Slave bus (AIPSTZ) bridge + +description: + The secure AIPS bridge (AIPSTZ) acts as a bridge for AHB masters issuing + transactions to IP Slave peripherals. Additionally, this module offers a= ccess + control configurations meant to restrict which peripherals a master can + access. + +maintainers: + - Laurentiu Mihalcea + +properties: + compatible: + const: fsl,imx8mp-aipstz + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#access-controller-cells": + const: 3 + description: + First cell - consumer ID + Second cell - consumer type (master or peripheral) + Third cell - configuration value + + ranges: true + +# borrowed from simple-bus.yaml, no additional requirements for children +patternProperties: + "@(0|[1-9a-f][0-9a-f]*)$": + type: object + additionalProperties: true + properties: + reg: + items: + minItems: 2 + maxItems: 4 + minItems: 1 + maxItems: 1024 + ranges: + oneOf: + - items: + minItems: 3 + maxItems: 7 + minItems: 1 + maxItems: 1024 + - $ref: /schemas/types.yaml#/definitions/flag + anyOf: + - required: + - reg + - required: + - ranges + +required: + - compatible + - reg + - power-domains + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + + bus@30df0000 { + compatible =3D "fsl,imx8mp-aipstz"; + reg =3D <0x30df0000 0x10000>; + ranges =3D <0x30c00000 0x30c00000 0x400000>; + power-domains =3D <&pgc_audio>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #access-controller-cells =3D <3>; + + dma-controller@30e00000 { + compatible =3D "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg =3D <0x30e00000 0x10000>; + #dma-cells =3D <3>; + clocks =3D <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names =3D "ipg", "ahb"; + interrupts =3D ; + fsl,sdma-ram-script-name =3D "imx/sdma/sdma-imx7d.bin"; + }; + }; --=20 2.34.1 From nobody Sat Oct 11 12:08:50 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C713023BCFD; Tue, 10 Jun 2025 16:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; 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Tue, 10 Jun 2025 09:02:24 -0700 (PDT) Received: from playground.localdomain ([82.79.237.69]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53229e009sm13017806f8f.16.2025.06.10.09.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 09:02:24 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Frank Li , Marco Felsch , Marc Kleine-Budde , Alexander Stein Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/6] dt-bindings: dsp: fsl,dsp: document 'access-controllers' property Date: Tue, 10 Jun 2025 12:01:48 -0400 Message-Id: <20250610160152.1113930-3-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> References: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Some DSP instances may have their access to certain peripherals conditioned by a bus access controller such as the one from the AIPSTZ bridge. Add the optional 'access-controllers' property, which may be used in such cases. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/dsp/fsl,dsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documenta= tion/devicetree/bindings/dsp/fsl,dsp.yaml index b8693e4b4b0d..e610b7636a08 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -91,6 +91,9 @@ properties: - const: runstall - const: softreset =20 + access-controllers: + maxItems: 1 + required: - compatible - reg --=20 2.34.1 From nobody Sat Oct 11 12:08:50 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74E4923D281; Tue, 10 Jun 2025 16:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; 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charset="utf-8" From: Laurentiu Mihalcea The secure AHB to IP Slave (AIPSTZ) bus bridge provides access control configurations meant to restrict access to certain peripherals. Some of the configurations include: 1) Marking masters as trusted for R/W. Based on this (and the configuration of the accessed peripheral), the bridge may choose to abort the R/W transactions issued by certain masters. 2) Allowing/disallowing write accesses to peripherals. Add driver for this IP. Since there's currently no framework for access controllers (and since there's currently no need for having flexibility w.r.t the configurations) all this driver does is it applies a relaxed, "default" configuration, in which all masters are trusted for R/W. Note that some instances of this IP (e.g: AIPSTZ5 on i.MX8MP) may be tied to a power domain and may lose their configuration when the domain is powered off. This is why the configuration has to be restored when the domain is powered on. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- drivers/bus/Kconfig | 6 +++ drivers/bus/Makefile | 1 + drivers/bus/imx-aipstz.c | 96 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 drivers/bus/imx-aipstz.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index ff669a8ccad9..fe7600283e70 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -87,6 +87,12 @@ config HISILICON_LPC Driver to enable I/O access to devices attached to the Low Pin Count bus on the HiSilicon Hip06/7 SoC. =20 +config IMX_AIPSTZ + tristate "Support for IMX Secure AHB to IP Slave bus (AIPSTZ) bridge" + depends on ARCH_MXC + help + Enable support for IMX AIPSTZ bridge. + config IMX_WEIM bool "Freescale EIM DRIVER" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index cddd4984d6af..8e693fe8a03a 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_FSL_MC_BUS) +=3D fsl-mc/ =20 obj-$(CONFIG_BT1_APB) +=3D bt1-apb.o obj-$(CONFIG_BT1_AXI) +=3D bt1-axi.o +obj-$(CONFIG_IMX_AIPSTZ) +=3D imx-aipstz.o obj-$(CONFIG_IMX_WEIM) +=3D imx-weim.o obj-$(CONFIG_INTEL_IXP4XX_EB) +=3D intel-ixp4xx-eb.o obj-$(CONFIG_MIPS_CDMM) +=3D mips_cdmm.o diff --git a/drivers/bus/imx-aipstz.c b/drivers/bus/imx-aipstz.c new file mode 100644 index 000000000000..6610251f41c7 --- /dev/null +++ b/drivers/bus/imx-aipstz.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include + +#define IMX_AIPSTZ_MPR0 0x0 + +struct imx_aipstz_config { + u32 mpr0; +}; + +struct imx_aipstz_data { + void __iomem *base; + const struct imx_aipstz_config *default_cfg; +}; + +static void imx_aipstz_apply_default(struct imx_aipstz_data *data) +{ + writel(data->default_cfg->mpr0, data->base + IMX_AIPSTZ_MPR0); +} + +static int imx_aipstz_probe(struct platform_device *pdev) +{ + struct imx_aipstz_data *data; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return dev_err_probe(&pdev->dev, -ENOMEM, + "failed to allocate data memory\n"); + + data->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(data->base)) + return dev_err_probe(&pdev->dev, -ENOMEM, + "failed to get/ioremap AC memory\n"); + + data->default_cfg =3D of_device_get_match_data(&pdev->dev); + + imx_aipstz_apply_default(data); + + dev_set_drvdata(&pdev->dev, data); + + pm_runtime_set_active(&pdev->dev); + devm_pm_runtime_enable(&pdev->dev); + + return devm_of_platform_populate(&pdev->dev); +} + +static int imx_aipstz_runtime_resume(struct device *dev) +{ + struct imx_aipstz_data *data =3D dev_get_drvdata(dev); + + /* restore potentially lost configuration during domain power-off */ + imx_aipstz_apply_default(data); + + return 0; +} + +static const struct dev_pm_ops imx_aipstz_pm_ops =3D { + RUNTIME_PM_OPS(NULL, imx_aipstz_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +/* + * following configuration is equivalent to: + * masters 0-7 =3D> trusted for R/W + use AHB's HPROT[1] to det. privilege + */ +static const struct imx_aipstz_config imx8mp_aipstz_default_cfg =3D { + .mpr0 =3D 0x77777777, +}; + +static const struct of_device_id imx_aipstz_of_ids[] =3D { + { .compatible =3D "fsl,imx8mp-aipstz", .data =3D &imx8mp_aipstz_default_c= fg }, + { } +}; +MODULE_DEVICE_TABLE(of, imx_aipstz_of_ids); + +static struct platform_driver imx_aipstz_of_driver =3D { + .probe =3D imx_aipstz_probe, + .driver =3D { + .name =3D "imx-aipstz", + .of_match_table =3D imx_aipstz_of_ids, + .pm =3D pm_ptr(&imx_aipstz_pm_ops), + }, +}; +module_platform_driver(imx_aipstz_of_driver); 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Tue, 10 Jun 2025 09:02:27 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Frank Li , Marco Felsch , Marc Kleine-Budde , Alexander Stein Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 4/6] arm64: dts: imx8mp: convert 'aips5' to 'aipstz5' Date: Tue, 10 Jun 2025 12:01:50 -0400 Message-Id: <20250610160152.1113930-5-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> References: <20250610160152.1113930-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea AIPS5 is actually AIPSTZ5 as it offers some security-related configurations. Since these configurations need to be applied before accessing any of the peripherals on the bus, it's better to make AIPSTZ5 be their parent instead of keeping AIPS5 and adding a child node for AIPSTZ5. Also, because of the security configurations, the address space of the bus has to be changed to that of the configuration registers. Finally, since AIPSTZ5 belongs to the AUDIOMIX power domain, add the missing 'power-domains' property. The domain needs to be powered on before attempting to configure the security-related registers. The DT node name is not changed to avoid potential issues with DTs in which this node is referenced. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 948b88cf5e9d..307e1671eccf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1397,12 +1397,14 @@ eqos: ethernet@30bf0000 { }; }; =20 - aips5: bus@30c00000 { - compatible =3D "fsl,aips-bus", "simple-bus"; - reg =3D <0x30c00000 0x400000>; + aips5: bus@30df0000 { + compatible =3D "fsl,imx8mp-aipstz"; + reg =3D <0x30df0000 0x10000>; + power-domains =3D <&pgc_audio>; #address-cells =3D <1>; #size-cells =3D <1>; - ranges; + #access-controller-cells =3D <3>; + ranges =3D <0x30c00000 0x30c00000 0x400000>; =20 spba-bus@30c00000 { compatible =3D "fsl,spba-bus", "simple-bus"; --=20 2.34.1 From nobody Sat Oct 11 12:08:50 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35295238C10; 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charset="utf-8" From: Laurentiu Mihalcea Add header file with AIPSTZ-related definitions: consumer types, master/peripheral configuration bits, and master ID definitions. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8mp-aipstz.h | 33 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 2 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aipstz.h diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h b/arch/arm64/boo= t/dts/freescale/imx8mp-aipstz.h new file mode 100644 index 000000000000..6481c484ca37 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX8MP_AIPSTZ_H +#define __IMX8MP_AIPSTZ_H + +/* consumer type - master or peripheral */ +#define IMX8MP_AIPSTZ_MASTER 0x0 +#define IMX8MP_AIPSTZ_PERIPH 0x1 + +/* master configuration options */ +#define IMX8MP_AIPSTZ_MPL (1 << 0) +#define IMX8MP_AIPSTZ_MTW (1 << 1) +#define IMX8MP_AIPSTZ_MTR (1 << 2) +#define IMX8MP_AIPSTZ_MBW (1 << 3) + +/* peripheral configuration options */ +#define IMX8MP_AIPSTZ_TP (1 << 0) +#define IMX8MP_AIPSTZ_WP (1 << 1) +#define IMX8MP_AIPSTZ_SP (1 << 2) +#define IMX8MP_AIPSTZ_BW (1 << 3) + +/* master ID definitions */ +#define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */ +#define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */ +#define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */ +#define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */ +#define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */ +#define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */ + +#endif /* __IMX8MP_AIPSTZ_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 307e1671eccf..9b550f225856 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -13,6 +13,7 @@ #include #include =20 +#include "imx8mp-aipstz.h" #include "imx8mp-pinfunc.h" =20 / { --=20 2.34.1 From nobody Sat Oct 11 12:08:50 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CD3C242913; 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charset="utf-8" From: Laurentiu Mihalcea The DSP needs to access peripherals on AIPSTZ5 (to communicate with the AP using AUDIOMIX MU, for instance). To do so, the security-related registers of the bridge have to be configured before the DSP is started. Enforce a dependency on AIPSTZ5 by adding the 'access-controllers' property to the 'dsp' node. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 9b550f225856..26efea15f6b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2435,6 +2435,11 @@ dsp: dsp@3b6e8000 { firmware-name =3D "imx/dsp/hifi4.bin"; resets =3D <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; reset-names =3D "runstall"; + access-controllers =3D <&aips5 + IMX8MP_AIPSTZ_HIFI4 + IMX8MP_AIPSTZ_MASTER + (IMX8MP_AIPSTZ_MPL | IMX8MP_AIPSTZ_MTW | IMX8MP_AIPSTZ_MTR) + >; status =3D "disabled"; }; }; --=20 2.34.1