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Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi Date: Tue, 10 Jun 2025 13:05:36 +0300 Message-ID: <20250610100540.2834044-4-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACLINT-SSWI variant for the MIPS P8700. This CPU has SSWI device compliant with the RISC-V draft spec (see [1]) CPU indexes on this platform are not contiguous, instead it uses bit-fields to encode hart,core,cluster numbers, thus property "riscv,hart-indexes" is mandatory Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev --- .../thead,c900-aclint-sswi.yaml | 64 ++++++++++++++++--- 1 file changed, 55 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-sswi.yaml index 8d330906bbbd..c1ab865fcd64 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml @@ -4,23 +4,32 @@ $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-= sswi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device +title: ACLINT Supervisor-level Software Interrupt Device =20 maintainers: - Inochi Amaoto =20 description: - The SSWI device is a part of the THEAD ACLINT device. It provides - supervisor-level IPI functionality for a set of HARTs on a THEAD - platform. It provides a register to set an IPI (SETSSIP) for each - HART connected to the SSWI device. + The SSWI device is a part of the ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a supported + platforms. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. See draft specification + https://github.com/riscvarchive/riscv-aclint + + Following variants of the SSWI ACLINT supported, using dedicated + compatible string + - THEAD C900 + - MIPS P8700 =20 properties: compatible: - items: - - enum: - - sophgo,sg2044-aclint-sswi - - const: thead,c900-aclint-sswi + oneOf: + - items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + - items: + - const: mips,p8700-aclint-sswi =20 reg: maxItems: 1 @@ -34,6 +43,14 @@ properties: minItems: 1 maxItems: 4095 =20 + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4095 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + additionalProperties: false =20 required: @@ -43,8 +60,22 @@ required: - interrupt-controller - interrupts-extended =20 +allOf: + - if: + properties: + compatible: + contains: + const: mips,p8700-aclint-sswi + then: + required: + - riscv,hart-indexes + else: + properties: + riscv,hart-indexes: false + examples: - | + //Example 1 interrupt-controller@94000000 { compatible =3D "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; reg =3D <0x94000000 0x00004000>; @@ -55,4 +86,19 @@ examples: <&cpu3intc 1>, <&cpu4intc 1>; }; + + - | + //Example 2 + interrupt-controller@94000000 { + compatible =3D "mips,p8700-aclint-sswi"; + reg =3D <0x94000000 0x00004000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + riscv,hart-indexes =3D <0x0 0x1 0x10 0x11>; + }; + ... --=20 2.43.0