From nobody Sat Oct 11 12:10:14 2025 Received: from esa2.hc555-34.eu.iphmx.com (esa2.hc555-34.eu.iphmx.com [23.90.104.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09BEF27F4ED; Tue, 10 Jun 2025 10:06:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.90.104.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550003; cv=none; b=lcqdYqRl+JWQTTZ2rNWxukxMYNOXqMN0A1F/hvDSgM/Dj3Rg/wc/KkWuhZtbmFhVoI+vVMyoB0gxryf6GzvcwGFz8azj/irKxbez6wgK0MOQKtw9g5Yed+JaSZJrkCGlaiLP7F9lU/oh6MbqAEymkWJZkhTg1oi84RzaGJQbcEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550003; c=relaxed/simple; bh=nQG56wm8YiJ3e1/np7PeCCf0UWl4uscXzw3s2/Xik6w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lxTk5+MGbOhU2y3768araNXixCl1v9cvvWggoIvstbWRajfv1FZME+YC0ljlkZvcs5GGzpEe+MwqUYADTTBx5+T3XCImez4ZutTYoVF+8hREeAm2CjigQpRUQq6nNu/TphaUOV9+Sj9N+Q1cjq5/t9DAlgGc1H53fHfwR0iva5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com; spf=pass smtp.mailfrom=mobileye.com; dkim=fail (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b=mc4PocD2 reason="key not found in DNS"; arc=none smtp.client-ip=23.90.104.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mobileye.com Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b="mc4PocD2" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1749550000; x=1781086000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nQG56wm8YiJ3e1/np7PeCCf0UWl4uscXzw3s2/Xik6w=; b=mc4PocD23OtCwXb3iY27zZq7uT0K8oTlxhXONcsMM3iyNBEcEINx4IeM PrEfRi53kneecW+nXrWXw9xmhNjfOHJOgCSXQ4zkJw2yE55GXAcl4Tqcj fiJd7I78WPEeGWUrsooPV+EnOAgX1FNDKXwHrkrHyybxYYuyoetuEhpm+ 01nuRIMg+1gIpwV1+TgwcsSkNfvmc+LnGFxwCX+O1n5LS1xpMINPUdBUG 8pg0Bu2CPRg/TrT6vksqzDrmiQEyxGtKaVJMyxBfdXNA4VesZlB+V0s2l OVDyrcLhOPNfcTS20zACAGOQUTj5bz7Rn79kz0sNFzdLR6DgVKR7GZG9w w==; X-CSE-ConnectionGUID: 44TnxZt3SyeoYmRFmM3UJw== X-CSE-MsgGUID: 2TrjhAufSvCuiwNJNHstQA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces01_data.me-corp.lan) ([146.255.191.134]) by esa2.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2025 13:06:36 +0300 X-CSE-ConnectionGUID: 0GPXmb+TQzWYfAeyG3ls5w== X-CSE-MsgGUID: 9eismvwbSH2hYhs555fp5A== Received: from unknown (HELO epgd071.me-corp.lan) ([10.154.54.1]) by ces01_data.me-corp.lan with SMTP; 10 Jun 2025 13:06:34 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:35 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 1/7] riscv: helper to parse hart index Date: Tue, 10 Jun 2025 13:05:34 +0300 Message-ID: <20250610100540.2834044-2-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable RISC-V APLIC specification defines "hart index" in [1] And similar definitions found for ACLINT in [2] Quote from [1]: Within a given interrupt domain, each of the domain=E2=80=99s harts has a u= nique index number in the range 0 to 2^14 =E2=88=92 1 (=3D 16,383). The index num= ber a domain associates with a hart may or may not have any relationship to the unique hart identifier (=E2=80=9Chart ID=E2=80=9D) that the RISC-V Privileg= ed Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, [1] says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indices specified in an optional property "riscv,hart-indexes" which is specified as an array of u32 elements, one per interrupt target, listing hart indexes in the same order as in "interrupts-extended". If this property is not specified, fallback to use logical hart indices within the domain. If property not exist, fall back to logical hart indexes Link: https://github.com/riscv/riscv-aia [1] Link: https://github.com/riscvarchive/riscv-aclint [2] Signed-off-by: Vladimir Kondratiev --- arch/riscv/include/asm/irq.h | 2 ++ arch/riscv/kernel/irq.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 7b038f3b7cb0..59c975f750c9 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -22,6 +22,8 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask= , int exclude_cpu); void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); +int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index, + u32 *hart_index); =20 #ifdef CONFIG_ACPI =20 diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 9ceda02507ca..efdf505bb776 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -32,6 +32,40 @@ struct fwnode_handle *riscv_get_intc_hwnode(void) } EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); =20 +/** + * riscv_get_hart_index() - get hart index for interrupt delivery + * @fwnode: interrupt controller node + * @logical_index: index within the "interrupts-extended" property + * @hart_index: filled with the hart index to use + * + * RISC-V uses term "hart index" for its interrupt controllers, for the + * purpose of the interrupt routing to destination harts. + * It may be arbitrary numbers assigned to each destination hart in context + * of the particular interrupt domain. + * + * These numbers encoded in the optional property "riscv,hart-indexes" + * that should contain hart index for each interrupt destination in the sa= me + * order as in the "interrupts-extended" property. If this property + * not exist, it assumed equal to the logical index, i.e. index within the + * "interrupts-extended" property. + * + * Return: error code + */ +int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index, + u32 *hart_index) +{ + static const char *prop_hart_index =3D "riscv,hart-indexes"; + struct device_node *np =3D to_of_node(fwnode); + + if (!np || !of_property_present(np, prop_hart_index)) { + *hart_index =3D logical_index; + return 0; + } + + return of_property_read_u32_index(np, prop_hart_index, + logical_index, hart_index); +} + #ifdef CONFIG_IRQ_STACKS #include =20 --=20 2.43.0 From nobody Sat Oct 11 12:10:14 2025 Received: from esa2.hc555-34.eu.iphmx.com (esa2.hc555-34.eu.iphmx.com [23.90.104.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D5BB28A708; Tue, 10 Jun 2025 10:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.90.104.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550005; cv=none; b=H3CgGHs9BYqylt1LmJ5eRu5MW8bbExmnbec8fwjdd/P0cmhEDYYNrqj2dS9irQnDrxcJHRhlVK5Bb1ygeDmmLodSIe7yhCzXHZZUCkPstCQ/culeKiERoHNMMBGMGgoMxqlzfw+sGQ+dy2kjxxsw38sugx4WZ8ebwejMfLf1G4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550005; c=relaxed/simple; bh=S4SlciKZEDkvxxA53sOZjgI7BGGyzxMFgS4kqW029qc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dd4mEFUWouzDPV7f3kT19/+4VUA8pyZvUQGFsLCdCLyaPPxZuM0JSUV0X6MszS5aR3MOur71tYwVJwgzffucjvvinOvi8+OmOh0uRwMG0ky6Eq9goPGoaY9lNq23TqjOM7Yt0z9JNX5HgcxZRhMDlu0JDm+UoOFo8TFV6M7/bIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com; spf=pass smtp.mailfrom=mobileye.com; dkim=fail (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b=D471VFPk reason="key not found in DNS"; arc=none smtp.client-ip=23.90.104.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mobileye.com Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b="D471VFPk" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1749550004; x=1781086004; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S4SlciKZEDkvxxA53sOZjgI7BGGyzxMFgS4kqW029qc=; b=D471VFPkZYynsRqheUyi5ZZqVSoP7KEtDrkvegQb+71XaAyZcFjWLP2U /NfxnD+zGJ/b0iiAZM7ZwFALbmW7JwVPbDsChHo3GWrFuLSrL7KDcjoQk +VISJeeFvnsAITut2V79zY5amd5BgY242TYPWfmh/6lG9dQWn4S6mV+9O 6gtwqIsvGk6mg9q5sNeapWADHFRKHdSPe1rvklL19sKJnJm0W9ZhU0ZsY 6neGoATnZY6eVkmI9CC3PiuBLYmIPR3W3KWP9ZUvclnQczoWpLwpFDC3u 9h5gzsTnHiBYO3jWYQXUUF8L9rB8tNUd6dN2NdLobR5q8qv8PmSitdcXE A==; X-CSE-ConnectionGUID: 44TnxZt3SyeoYmRFmM3UJw== X-CSE-MsgGUID: he1bGLnJRzqdVEyeLeDcnA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces01_data.me-corp.lan) ([146.255.191.134]) by esa2.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2025 13:06:37 +0300 X-CSE-ConnectionGUID: L/mYHuCUT9qp4TiIzR8Dlw== X-CSE-MsgGUID: hvG3VRHtSp+PyC8qsVTeAA== Received: from unknown (HELO epgd071.me-corp.lan) ([10.154.54.1]) by ces01_data.me-corp.lan with SMTP; 10 Jun 2025 13:06:35 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:36 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 2/7] irqchip: riscv aplic: use riscv_get_hart_index() Date: Tue, 10 Jun 2025 13:05:35 +0300 Message-ID: <20250610100540.2834044-3-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use global helper function instead of the local implementation Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/irq-riscv-aplic-direct.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq= -riscv-aplic-direct.c index 205ad61d15e4..c2a75bf3d20c 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -219,20 +219,6 @@ static int aplic_direct_parse_parent_hwirq(struct devi= ce *dev, u32 index, return 0; } =20 -static int aplic_direct_get_hart_index(struct device *dev, u32 logical_ind= ex, - u32 *hart_index) -{ - const char *prop_hart_index =3D "riscv,hart-indexes"; - struct device_node *np =3D to_of_node(dev->fwnode); - - if (!np || !of_property_present(np, prop_hart_index)) { - *hart_index =3D logical_index; - return 0; - } - - return of_property_read_u32_index(np, prop_hart_index, logical_index, har= t_index); -} - int aplic_direct_setup(struct device *dev, void __iomem *regs) { int i, j, rc, cpu, current_cpu, setup_count =3D 0; @@ -279,7 +265,7 @@ int aplic_direct_setup(struct device *dev, void __iomem= *regs) cpumask_set_cpu(cpu, &direct->lmask); =20 idc =3D per_cpu_ptr(&aplic_idcs, cpu); - rc =3D aplic_direct_get_hart_index(dev, i, &idc->hart_index); + rc =3D riscv_get_hart_index(dev->fwnode, i, &idc->hart_index); if (rc) { dev_warn(dev, "hart index not found for IDC%d\n", i); continue; --=20 2.43.0 From nobody Sat Oct 11 12:10:14 2025 Received: from esa3.hc555-34.eu.iphmx.com (esa3.hc555-34.eu.iphmx.com [207.54.77.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0061280319; 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Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi Date: Tue, 10 Jun 2025 13:05:36 +0300 Message-ID: <20250610100540.2834044-4-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ACLINT-SSWI variant for the MIPS P8700. This CPU has SSWI device compliant with the RISC-V draft spec (see [1]) CPU indexes on this platform are not contiguous, instead it uses bit-fields to encode hart,core,cluster numbers, thus property "riscv,hart-indexes" is mandatory Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev --- .../thead,c900-aclint-sswi.yaml | 64 ++++++++++++++++--- 1 file changed, 55 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-sswi.yaml index 8d330906bbbd..c1ab865fcd64 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml @@ -4,23 +4,32 @@ $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-= sswi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device +title: ACLINT Supervisor-level Software Interrupt Device =20 maintainers: - Inochi Amaoto =20 description: - The SSWI device is a part of the THEAD ACLINT device. It provides - supervisor-level IPI functionality for a set of HARTs on a THEAD - platform. It provides a register to set an IPI (SETSSIP) for each - HART connected to the SSWI device. + The SSWI device is a part of the ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a supported + platforms. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. See draft specification + https://github.com/riscvarchive/riscv-aclint + + Following variants of the SSWI ACLINT supported, using dedicated + compatible string + - THEAD C900 + - MIPS P8700 =20 properties: compatible: - items: - - enum: - - sophgo,sg2044-aclint-sswi - - const: thead,c900-aclint-sswi + oneOf: + - items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + - items: + - const: mips,p8700-aclint-sswi =20 reg: maxItems: 1 @@ -34,6 +43,14 @@ properties: minItems: 1 maxItems: 4095 =20 + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4095 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + additionalProperties: false =20 required: @@ -43,8 +60,22 @@ required: - interrupt-controller - interrupts-extended =20 +allOf: + - if: + properties: + compatible: + contains: + const: mips,p8700-aclint-sswi + then: + required: + - riscv,hart-indexes + else: + properties: + riscv,hart-indexes: false + examples: - | + //Example 1 interrupt-controller@94000000 { compatible =3D "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; reg =3D <0x94000000 0x00004000>; @@ -55,4 +86,19 @@ examples: <&cpu3intc 1>, <&cpu4intc 1>; }; + + - | + //Example 2 + interrupt-controller@94000000 { + compatible =3D "mips,p8700-aclint-sswi"; + reg =3D <0x94000000 0x00004000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + riscv,hart-indexes =3D <0x0 0x1 0x10 0x11>; + }; + ... --=20 2.43.0 From nobody Sat Oct 11 12:10:14 2025 Received: from esa3.hc555-34.eu.iphmx.com (esa3.hc555-34.eu.iphmx.com [207.54.77.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8624B28BAA1; Tue, 10 Jun 2025 10:06:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.54.77.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550004; cv=none; b=PuOoGScZjeG3OaPu7a205sK0EYGRFpJyXY+T1NT+1OKaAmWQdbEPWsKrVzjBnTmYQ9t9V/A5eqkSEUA+iMxyI98vDsEGDzlX0NqLFub34Q561I259VDURWxQzn3ArP1Y19Rb2GYrJjAQXFDnRy9s5vSQ2NAnQ+otazDCFZWFe9Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550004; c=relaxed/simple; bh=ZkonT5XOETViMq2W8Vg4OLZt5WEYIKYmN1JdAPfoIck=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jK/HwK7HWZd5syP6cTBTA7e1bF2hqYl7SQyH5ZqvuRlWdT5VtbQDmSyIsFSMenyzA0uJSanHYN0DxWWaSHhrnIylch8vABhxMD0D6WVFcn2ziZ4o5lNlc+bjCxghfmJDFXdhwFlAqtoMUei+/PgC1hSiD7JTwhUtPqrin9gB3Lw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com; spf=pass smtp.mailfrom=mobileye.com; dkim=fail (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b=BtlutIj2 reason="key not found in DNS"; arc=none smtp.client-ip=207.54.77.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mobileye.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mobileye.com Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mobileye.com header.i=@mobileye.com header.b="BtlutIj2" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1749550002; x=1781086002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZkonT5XOETViMq2W8Vg4OLZt5WEYIKYmN1JdAPfoIck=; b=BtlutIj2cc+SW0kXNalMLEobAl5YvrNKZoDvYxizLdRJj+S6ih0aY6ne ALBL5QsxE+GsV616wfORdDTcR4ZCp4cF7Fz6PEBe7b9YzvcKUhLOIy7wK 5Rd5ujfqVvsvaQ/cfH4SzTB0vpwYb4uABjlAPpNHLMRBd1M2OUsOZTqAR 62CJZr2pgokseVtrpAhZRXRic0WIke0tI5U+XGzhI75BQ/GavgeVqGFui 2GgxF8x+/Ua72Hs54QLORo7xQDcDqNlv2eXBcTTNI2ufkjR45DLRcy0V9 uUi0RBiZ/cbuNz+S5DFuqpJXjFmw305xv283Kqx67Hcylu5Kf6Xg37pgP Q==; X-CSE-ConnectionGUID: TSqU/aK9R1y2qCI6ux7EpA== X-CSE-MsgGUID: 4BHU+QqyTVW2LmBnbHwQvg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces03_data.me-corp.lan) ([146.255.191.134]) by esa3.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2025 13:06:39 +0300 X-CSE-ConnectionGUID: 2clGyAAhREiAocQAIdOL4Q== X-CSE-MsgGUID: QC3bqOW8Sh66YowUez2SSQ== Received: from unknown (HELO epgd071.me-corp.lan) ([10.154.54.1]) by ces03_data.me-corp.lan with SMTP; 10 Jun 2025 13:06:38 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:38 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 4/7] irqchip: MIPS P800 variant of aclint-sswi Date: Tue, 10 Jun 2025 13:05:37 +0300 Message-ID: <20250610100540.2834044-5-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor Thead specific implementation of the ACLINT-SSWI irqchip. Factor out generic code that serves both Thead and MIPS variants. This generic part is according to the RISC-V draft spec [1]. Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/Kconfig | 16 ++++ drivers/irqchip/Makefile | 2 +- ...d-c900-aclint-sswi.c =3D> irq-aclint-sswi.c} | 93 +++++++++++++------ 3 files changed, 82 insertions(+), 29 deletions(-) rename drivers/irqchip/{irq-thead-c900-aclint-sswi.c =3D> irq-aclint-sswi.= c} (67%) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0d196e447142..be9b54900482 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -634,12 +634,28 @@ config STARFIVE_JH8100_INTC =20 If you don't know what to do here, say Y. =20 +config ACLINT_SSWI + bool + +config MIPS_P8700_ACLINT_SSWI + bool "MIPS P8700 ACLINT S-mode IPI Interrupt Controller" + depends on RISCV + depends on SMP + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_IPI_MUX + select ACLINT_SSWI + help + This enables support for MIPS P8700 specific ACLINT SSWI device + + If you don't know what to do here, say Y. + config THEAD_C900_ACLINT_SSWI bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" depends on RISCV depends on SMP select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_IPI_MUX + select ACLINT_SSWI help This enables support for T-HEAD specific ACLINT SSWI device support. diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 23ca4959e6ce..0458d6c5d161 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -105,7 +105,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o -obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o +obj-$(CONFIG_ACLINT_SSWI) +=3D irq-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o obj-$(CONFIG_IMX_MU_MSI) +=3D irq-imx-mu-msi.o diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip= /irq-aclint-sswi.c similarity index 67% rename from drivers/irqchip/irq-thead-c900-aclint-sswi.c rename to drivers/irqchip/irq-aclint-sswi.c index 8ff6e7a1363b..ec21785df518 100644 --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -3,7 +3,7 @@ * Copyright (C) 2024 Inochi Amaoto */ =20 -#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt +#define pr_fmt(fmt) "aclint-sswi: " fmt #include #include #include @@ -21,56 +21,51 @@ #include #include =20 -#define THEAD_ACLINT_xSWI_REGISTER_SIZE 4 - -#define THEAD_C9XX_CSR_SXSTATUS 0x5c0 -#define THEAD_C9XX_SXSTATUS_CLINTEE BIT(17) - static int sswi_ipi_virq __ro_after_init; static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); =20 -static void thead_aclint_sswi_ipi_send(unsigned int cpu) +static void aclint_sswi_ipi_send(unsigned int cpu) { writel(0x1, per_cpu(sswi_cpu_regs, cpu)); } =20 -static void thead_aclint_sswi_ipi_clear(void) +static void aclint_sswi_ipi_clear(void) { writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs)); } =20 -static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc) +static void aclint_sswi_ipi_handle(struct irq_desc *desc) { struct irq_chip *chip =3D irq_desc_get_chip(desc); =20 chained_irq_enter(chip, desc); =20 csr_clear(CSR_IP, IE_SIE); - thead_aclint_sswi_ipi_clear(); + aclint_sswi_ipi_clear(); =20 ipi_mux_process(); =20 chained_irq_exit(chip, desc); } =20 -static int thead_aclint_sswi_starting_cpu(unsigned int cpu) +static int aclint_sswi_starting_cpu(unsigned int cpu) { enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq)); =20 return 0; } =20 -static int thead_aclint_sswi_dying_cpu(unsigned int cpu) +static int aclint_sswi_dying_cpu(unsigned int cpu) { - thead_aclint_sswi_ipi_clear(); + aclint_sswi_ipi_clear(); =20 disable_percpu_irq(sswi_ipi_virq); =20 return 0; } =20 -static int __init thead_aclint_sswi_parse_irq(struct fwnode_handle *fwnode, - void __iomem *reg) +static int __init aclint_sswi_parse_irq(struct fwnode_handle *fwnode, + void __iomem *reg) { struct of_phandle_args parent; unsigned long hartid; @@ -97,7 +92,7 @@ static int __init thead_aclint_sswi_parse_irq(struct fwno= de_handle *fwnode, =20 cpu =3D riscv_hartid_to_cpuid(hartid); =20 - per_cpu(sswi_cpu_regs, cpu) =3D reg + i * THEAD_ACLINT_xSWI_REGISTER_SIZ= E; + per_cpu(sswi_cpu_regs, cpu) =3D reg + hart_index * 4; } =20 pr_info("%pfwP: register %u CPU%s\n", fwnode, contexts, str_plural(contex= ts)); @@ -105,17 +100,12 @@ static int __init thead_aclint_sswi_parse_irq(struct = fwnode_handle *fwnode, return 0; } =20 -static int __init thead_aclint_sswi_probe(struct fwnode_handle *fwnode) +static int __init aclint_sswi_probe(struct fwnode_handle *fwnode) { struct irq_domain *domain; void __iomem *reg; int virq, rc; =20 - /* If it is T-HEAD CPU, check whether SSWI is enabled */ - if (riscv_cached_mvendorid(0) =3D=3D THEAD_VENDOR_ID && - !(csr_read(THEAD_C9XX_CSR_SXSTATUS) & THEAD_C9XX_SXSTATUS_CLINTEE)) - return -ENOTSUPP; - if (!is_of_node(fwnode)) return -EINVAL; =20 @@ -124,7 +114,7 @@ static int __init thead_aclint_sswi_probe(struct fwnode= _handle *fwnode) return -ENOMEM; =20 /* Parse SSWI setting */ - rc =3D thead_aclint_sswi_parse_irq(fwnode, reg); + rc =3D aclint_sswi_parse_irq(fwnode, reg); if (rc < 0) return rc; =20 @@ -146,22 +136,68 @@ static int __init thead_aclint_sswi_probe(struct fwno= de_handle *fwnode) } =20 /* Register SSWI irq and handler */ - virq =3D ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send); + virq =3D ipi_mux_create(BITS_PER_BYTE, aclint_sswi_ipi_send); if (virq <=3D 0) { pr_err("unable to create muxed IPIs\n"); irq_dispose_mapping(sswi_ipi_virq); return virq < 0 ? virq : -ENOMEM; } =20 - irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle); + irq_set_chained_handler(sswi_ipi_virq, aclint_sswi_ipi_handle); =20 cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, - "irqchip/thead-aclint-sswi:starting", - thead_aclint_sswi_starting_cpu, - thead_aclint_sswi_dying_cpu); + "irqchip/aclint-sswi:starting", + aclint_sswi_starting_cpu, + aclint_sswi_dying_cpu); =20 riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); =20 + return 0; +} + +#if defined(CONFIG_MIPS_P8700_ACLINT_SSWI) +/* generic/MIPS variant */ +static int __init generic_aclint_sswi_probe(struct fwnode_handle *fwnode) +{ + int rc; + + rc =3D aclint_sswi_probe(fwnode); + if (rc) + return rc; + + /* Announce that SSWI is providing IPIs */ + pr_info("providing IPIs using ACLINT SSWI\n"); + + return 0; +} + +static int __init generic_aclint_sswi_early_probe(struct device_node *node, + struct device_node *parent) +{ + return generic_aclint_sswi_probe(&node->fwnode); +} +IRQCHIP_DECLARE(generic_aclint_sswi, "mips,p8700-aclint-sswi", generic_acl= int_sswi_early_probe); +#endif /* CONFIG_MIPS_P8700_ACLINT_SSWI */ + +#if defined(CONFIG_THEAD_C900_ACLINT_SSWI) + +#define THEAD_C9XX_CSR_SXSTATUS 0x5c0 +#define THEAD_C9XX_SXSTATUS_CLINTEE BIT(17) + +/* THEAD variant */ +static int __init thead_aclint_sswi_probe(struct fwnode_handle *fwnode) +{ + int rc; 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10 Jun 2025 13:06:40 +0300 X-CSE-ConnectionGUID: kf7t9c2kS5OjhTjsVC/tJQ== X-CSE-MsgGUID: m1n8WQB0R5K04I6yn90eAw== Received: from unknown (HELO epgd071.me-corp.lan) ([10.154.54.1]) by ces04_data.me-crop.lan with SMTP; 10 Jun 2025 13:06:39 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:39 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 5/7] irqchip: aslint-sswi: resolve hart index Date: Tue, 10 Jun 2025 13:05:38 +0300 Message-ID: <20250610100540.2834044-6-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Resolve hart index according to assignment in the "riscv,hart-indexes" property as defined in [1] Link: https://github.com/riscvarchive/riscv-aclint [1] Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/irq-aclint-sswi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint= -sswi.c index ec21785df518..186a021beaef 100644 --- a/drivers/irqchip/irq-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -71,6 +71,7 @@ static int __init aclint_sswi_parse_irq(struct fwnode_han= dle *fwnode, unsigned long hartid; u32 contexts, i; int rc, cpu; + u32 hart_index; =20 contexts =3D of_irq_count(to_of_node(fwnode)); if (!(contexts)) { @@ -92,6 +93,11 @@ static int __init aclint_sswi_parse_irq(struct fwnode_ha= ndle *fwnode, =20 cpu =3D riscv_hartid_to_cpuid(hartid); =20 + rc =3D riscv_get_hart_index(fwnode, i, &hart_index); + if (rc) { + pr_warn("%pfwP: hart index [%d] not found\n", fwnode, i); + return -EINVAL; + } per_cpu(sswi_cpu_regs, cpu) =3D reg + hart_index * 4; } =20 --=20 2.43.0 From nobody Sat Oct 11 12:10:14 2025 Received: from esa2.hc555-34.eu.iphmx.com (esa2.hc555-34.eu.iphmx.com [23.90.104.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6774828C2D3; Tue, 10 Jun 2025 10:06:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.90.104.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749550006; cv=none; b=OhEHmFWrWdshoF+uypJh/YHCtvyQcySidPh6MgMl14WZCfdsA6zDlRHwSnfL4lZqLqqhgeL7O25pU2b6MzGI3Pd0ykNONvqcM/MSTfHQwTQ8XmkwhteQfRcBnemoBTL1nRzNG4nC4odD5JObxa7ye0B3A/6JjBXngNTn7G5iqas= ARC-Message-Signature: i=1; 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10 Jun 2025 13:06:39 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:40 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 6/7] irqchip: aclint-sswi: reduce data scope Date: Tue, 10 Jun 2025 13:05:39 +0300 Message-ID: <20250610100540.2834044-7-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move variables to the innermost scope where it is used Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/irq-aclint-sswi.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint= -sswi.c index 186a021beaef..3aa074004dca 100644 --- a/drivers/irqchip/irq-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -67,11 +67,7 @@ static int aclint_sswi_dying_cpu(unsigned int cpu) static int __init aclint_sswi_parse_irq(struct fwnode_handle *fwnode, void __iomem *reg) { - struct of_phandle_args parent; - unsigned long hartid; - u32 contexts, i; - int rc, cpu; - u32 hart_index; + u32 contexts; =20 contexts =3D of_irq_count(to_of_node(fwnode)); if (!(contexts)) { @@ -79,7 +75,12 @@ static int __init aclint_sswi_parse_irq(struct fwnode_ha= ndle *fwnode, return -EINVAL; } =20 - for (i =3D 0; i < contexts; i++) { + for (u32 i =3D 0; i < contexts; i++) { + struct of_phandle_args parent; + unsigned long hartid; + int rc, cpu; + u32 hart_index; + rc =3D of_irq_parse_one(to_of_node(fwnode), i, &parent); if (rc) return rc; --=20 2.43.0 From nobody Sat Oct 11 12:10:14 2025 Received: from esa3.hc555-34.eu.iphmx.com (esa3.hc555-34.eu.iphmx.com [207.54.77.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A58F828C2B2; Tue, 10 Jun 2025 10:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.54.77.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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10 Jun 2025 13:06:43 +0300 X-CSE-ConnectionGUID: ax2a7oOURvuO1SiclmLw5w== X-CSE-MsgGUID: VpswVmopSHSN8kdMQv7iGg== Received: from unknown (HELO epgd071.me-corp.lan) ([10.154.54.6]) by ces03_data.me-corp.lan with SMTP; 10 Jun 2025 13:06:41 +0300 Received: by epgd071.me-corp.lan (sSMTP sendmail emulation); Tue, 10 Jun 2025 13:06:41 +0300 From: Vladimir Kondratiev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Chen Wang , Inochi Amaoto , Sunil V L , "Rafael J . Wysocki" , Ryo Takakura Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, Vladimir Kondratiev Subject: [PATCH v2 7/7] irqchip: aclint-sswi: remove extra includes Date: Tue, 10 Jun 2025 13:05:40 +0300 Message-ID: <20250610100540.2834044-8-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> References: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com> <20250610100540.2834044-1-vladimir.kondratiev@mobileye.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/irq-aclint-sswi.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint= -sswi.c index 3aa074004dca..dc437a4f82db 100644 --- a/drivers/irqchip/irq-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -6,15 +6,9 @@ #define pr_fmt(fmt) "aclint-sswi: " fmt #include #include -#include -#include #include #include -#include -#include #include -#include -#include #include #include #include --=20 2.43.0