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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:45 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v3 01/10] dt-bindings: arm: fsl: support Engicam MicroGEA BMM board Date: Tue, 10 Jun 2025 12:00:14 +0200 Message-ID: <20250610100139.2476555-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA BMM board based on the Engicam MicroGEA SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index d3b5e6923e41..5feb62611e53 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -769,6 +769,13 @@ properties: - const: dh,imx6ull-dhcor-som - const: fsl,imx6ull =20 + - description: i.MX6ULL Engicam MicroGEA SoM based boards + items: + - enum: + - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B30A28C024 for ; Tue, 10 Jun 2025 10:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549712; cv=none; b=A1DMAQ3pSCA05A/maihWAWEdexwWWkND2WquIzVJMHb09iQIvzpFgr/llJH77GEUO88pboYQD90/IpkkFne3Sky8/EzATnp0Y+tyymJjPe3SRyRMu+0NKB03hmCEKboyiOPtMMc4WTbkAwSRFZ3XxWv/2fy7MDxHXodtiUuS08w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549712; c=relaxed/simple; bh=UjMrT+cOHjik+PV0uTOts89DkEbH8i+V1efiehctKmY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uj4JYlkzSXobvFFVPBj1TZyIKHNiWOqkVRyWMlSRxv2crbnNxQ4WCfpoNiUHEmSJVUPWrNKJbzWW5D2hLnmrPOSX3wp5o3JUTQ5MY/IbnvgglSOFc8TNTkuLCVU2PQ1SPQ7G6tDCzOJ+6cylz1Fgq0GHiNadSR/Rif4xb3rIvfE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=D96RXOkb; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="D96RXOkb" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-607fbc13725so2528337a12.0 for ; Tue, 10 Jun 2025 03:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749549708; x=1750154508; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fVpRsOav3dc0RZBgP6jRNm+pqWPgbw4b4uSBb4dfuLs=; b=D96RXOkb6ciVbYpg7WnuVRePePW8mbqAn77CIj0xX1sgfegitp0URp1SwFV0uhXEQp BgafPiUsjFS7fYdJVO9dwXEgMcYF/qg9iYMy2Dz9IjUzu35gn5nvWgFQE5RlzQGfH5wY R3C99AIFm2Oud+QqgENOc7S4ZvbPem5OwBj8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749549708; x=1750154508; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fVpRsOav3dc0RZBgP6jRNm+pqWPgbw4b4uSBb4dfuLs=; b=L10e43I+2QBuoy+EN+gJjoGndQsSYbTGesVVSwgp1IQNwwLJq9i+uDrBLvgkYId8T+ zfmywum66AdsFBz/wJqNbXFkiJA7hazmpgtyGPN5h0Ki8bBgVM5rjQyOh8U1n9ANnqa1 utnsP6fQIgHeUDe+FgNR6fdlr0A1Jl09RFinXT2HOARFqBI43/n6NK5NV1U7zjYXSo0n aSrlE5TIGh0A27oK35jnm+thVtdKh9ryYjdOC0G2D56Sy0vfweU5TvPLet/creR0H/V7 bWU3pD9xS+YEHDYJUhomT4cIBxOZF6hsZrxSTakVzG1s2w/GOiXvuJPuKIT4m7bk+awD trFg== X-Gm-Message-State: AOJu0YxRa5c4kbN6cDXhq50YtzpHG99pi+B6DBqfYPpc5MtWuwybMz+A I9bz7VrQlLHgIjefGRV5AXYWgbBj3g/fUpyjhWXWQc4EWQ2cI7It964+C9qpfvxsaZrjVenRGnc SW9b8 X-Gm-Gg: ASbGncvoRvshCbsTfxkyQbBG4PCQk+Ah88XN/nYnoh/GtDcpsxNX50KP/FUEFs8Bpk8 5ne/KKMHt92qoibNV2dAAkj52B0CdddIDCeV/Qf3TwDBAHv25pqvbnpm0WRnE5qSLbq4FuvjPK1 VEbVqkLPjB4xAeYEl9IcB8MsDTCHOT1RvveSfMh58U8RnEmWIt+T+v9agPCi60VtzOM/YjxjFjb pjGssLt8XuYaP4CblL6fZx2P9JN4aJMqIfD7dD1fMDMiJeSHt9qBvTS7Uy+TOtoqtY9veNjuI+S WVixb21PH10X5T9XEdzDtWtZxcfbYNpwx9l1vbMPFxEpER/OPKzih5dOgGMeSFIcYLHJYgWMZU8 1+lC+B9m+h0RcGzcBLMDadlPyN1c= X-Google-Smtp-Source: AGHT+IEdzv89/n4ZpuVZrDYAFUC80+0NYiuFuEDwH6TaCdynJi5ZwnYhSmYFBATEcTH98tBhKddrrQ== X-Received: by 2002:a05:6402:348c:b0:607:edbb:4bbb with SMTP id 4fb4d7f45d1cf-607edbb4f69mr6751957a12.28.1749549707676; Tue, 10 Jun 2025 03:01:47 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 02/10] ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoM Date: Tue, 10 Jun 2025 12:00:15 +0200 Message-ID: <20250610100139.2476555-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v3: - Drop an extra blank line from the iomuxc node. Changes in v2: - Change local-mac-address to 00 00 00 00 00 00. The actual value will be set by the bootloader. The previous one was assigned to Freescale Semiconductor. .../dts/nxp/imx/imx6ull-engicam-microgea.dtsi | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch= /arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi new file mode 100644 index 000000000000..43518bf07602 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + + #include "imx6ull.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull", "fsl,imx6ull"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x20000000>; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_phy_reset>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + local-mac-address =3D [00 00 00 00 00 00]; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <4000>; + reset-deassert-us =3D <4000>; + }; + }; +}; + +/* NAND */ +&gpmi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpmi_nand>; + nand-ecc-mode =3D "hw"; + nand-ecc-strength =3D <0>; + nand-ecc-step-size =3D <0>; + nand-on-flash-bbt; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins =3D < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_phy_reset: phy-resetgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CBB328C5B2 for ; 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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:48 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 03/10] ARM: dts: imx6ul: support Engicam MicroGEA BMM board Date: Tue, 10 Jun 2025 12:00:16 +0200 Message-ID: <20250610100139.2476555-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA BMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan Reviewed-by: Frank Li --- Changes in v3: - Rename sgtl5000 node to audio-codec. - Move the reg property of the audio-codec node right after the compatible property. - Drop an extra blank line from iomuxc and iomuxc_snvs nodes. Changes in v2: - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. - Add Reviewed-by tag of Peng Fan. arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-bmm.dts | 303 ++++++++++++++++++ 2 files changed, 304 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 8b3abe817e12..57f185198217 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -356,6 +356,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-pdk2.dtb \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ + imx6ull-engicam-microgea-bmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts new file mode 100644 index 000000000000..279d46c22cd7 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-bmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-bmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + #sound-dai-cells =3D <0>; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&tsc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tsc>; + measure-delay-time =3D <0x9ffff>; + pre-charge-time =3D <0xfff>; + xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb1_vbus>; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb2_vbus>; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x11008 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x000b0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x000b0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x000b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; 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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:50 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 04/10] ARM: imx_v6_v7_defconfig: cleanup mxs_defconfig Date: Tue, 10 Jun 2025 12:00:17 +0200 Message-ID: <20250610100139.2476555-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generate imx_v6_v7_defconfig by doing: make imx_v6_v7_defconfig make savedefconfig cp defconfig arch/arm/configs/imx_v6_v7_defconfig No functional change. The goal here is to cleanup imx_v6_v7_defconfig file to make easier and cleaner the addition of new entries. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/configs/imx_v6_v7_defconfig | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 062c1eb8dd60..d40ca9edd264 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_RELAY=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy CONFIG_PERF_EVENTS=3Dy +CONFIG_KEXEC=3Dy CONFIG_ARCH_MULTI_V6=3Dy CONFIG_ARCH_MXC=3Dy CONFIG_SOC_IMX31=3Dy @@ -32,7 +33,6 @@ CONFIG_ARM_PSCI=3Dy CONFIG_HIGHMEM=3Dy CONFIG_ARCH_FORCE_MAX_ORDER=3D13 CONFIG_CMDLINE=3D"noinitrd console=3Dttymxc0,115200" -CONFIG_KEXEC=3Dy CONFIG_CPU_FREQ=3Dy CONFIG_CPU_FREQ_STAT=3Dy CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=3Dy @@ -129,7 +129,6 @@ CONFIG_CS89x0_PLATFORM=3Dy CONFIG_QCA7000_SPI=3Dm # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=3Dy -CONFIG_SMC911X=3Dy CONFIG_SMSC911X=3Dy # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_MICREL_PHY=3Dy @@ -153,9 +152,7 @@ CONFIG_MWIFIEX_PCIE=3Dm CONFIG_WL12XX=3Dm CONFIG_WL18XX=3Dm CONFIG_WLCORE_SDIO=3Dm -# CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_INPUT_EVDEV=3Dy -CONFIG_INPUT_EVBUG=3Dm CONFIG_KEYBOARD_GPIO=3Dy CONFIG_KEYBOARD_SNVS_PWRKEY=3Dy CONFIG_KEYBOARD_IMX=3Dy @@ -190,9 +187,7 @@ CONFIG_SERIAL_IMX_CONSOLE=3Dy CONFIG_SERIAL_FSL_LPUART=3Dy CONFIG_SERIAL_FSL_LPUART_CONSOLE=3Dy CONFIG_SERIAL_DEV_BUS=3Dy -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=3Dy -CONFIG_I2C_MUX=3Dy CONFIG_I2C_MUX_GPIO=3Dy # CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_ALGOPCF=3Dm @@ -204,14 +199,9 @@ CONFIG_SPI_FSL_QUADSPI=3Dy CONFIG_SPI_GPIO=3Dy CONFIG_SPI_IMX=3Dy CONFIG_SPI_FSL_DSPI=3Dy -CONFIG_PINCTRL_IMX8MM=3Dy -CONFIG_PINCTRL_IMX8MN=3Dy -CONFIG_PINCTRL_IMX8MP=3Dy -CONFIG_PINCTRL_IMX8MQ=3Dy CONFIG_GPIO_SYSFS=3Dy CONFIG_GPIO_MXC=3Dy CONFIG_GPIO_SIOX=3Dm -CONFIG_GPIO_VF610=3Dy CONFIG_GPIO_MAX732X=3Dy CONFIG_GPIO_PCA953X=3Dy CONFIG_GPIO_PCA953X_IRQ=3Dy @@ -225,7 +215,6 @@ CONFIG_W1_SLAVE_THERM=3Dm CONFIG_POWER_RESET=3Dy CONFIG_POWER_RESET_SYSCON=3Dy CONFIG_POWER_RESET_SYSCON_POWEROFF=3Dy -CONFIG_POWER_SUPPLY=3Dy CONFIG_RN5T618_POWER=3Dm CONFIG_SENSORS_MC13783_ADC=3Dy CONFIG_SENSORS_GPIO_FAN=3Dy @@ -283,13 +272,13 @@ CONFIG_VIDEO_OV5645=3Dm CONFIG_VIDEO_ADV7180=3Dm CONFIG_IMX_IPUV3_CORE=3Dy CONFIG_DRM=3Dy -CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_MSM=3Dy CONFIG_DRM_PANEL_LVDS=3Dy -CONFIG_DRM_PANEL_SIMPLE=3Dy -CONFIG_DRM_PANEL_EDP=3Dy CONFIG_DRM_PANEL_SEIKO_43WVF1G=3Dy +CONFIG_DRM_PANEL_EDP=3Dy +CONFIG_DRM_PANEL_SIMPLE=3Dy CONFIG_DRM_DISPLAY_CONNECTOR=3Dy +CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_LVDS_CODEC=3Dm CONFIG_DRM_SII902X=3Dy CONFIG_DRM_TI_TFP410=3Dy @@ -310,7 +299,6 @@ CONFIG_LCD_PLATFORM=3Dy CONFIG_BACKLIGHT_CLASS_DEVICE=3Dy CONFIG_BACKLIGHT_PWM=3Dy CONFIG_BACKLIGHT_GPIO=3Dy -CONFIG_FRAMEBUFFER_CONSOLE=3Dy CONFIG_LOGO=3Dy CONFIG_SOUND=3Dy CONFIG_SND=3Dy @@ -380,11 +368,8 @@ CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy -CONFIG_NEW_LEDS=3Dy -CONFIG_LEDS_CLASS=3Dy CONFIG_LEDS_GPIO=3Dy CONFIG_LEDS_PWM=3Dy -CONFIG_LEDS_TRIGGERS=3Dy CONFIG_LEDS_TRIGGER_TIMER=3Dy CONFIG_LEDS_TRIGGER_ONESHOT=3Dy CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy @@ -453,7 +438,6 @@ CONFIG_EXT3_FS_POSIX_ACL=3Dy CONFIG_EXT3_FS_SECURITY=3Dy CONFIG_QUOTA=3Dy CONFIG_QUOTA_NETLINK_INTERFACE=3Dy -# CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_AUTOFS_FS=3Dy CONFIG_FUSE_FS=3Dy CONFIG_ISO9660_FS=3Dm @@ -490,5 +474,4 @@ CONFIG_PRINTK_TIME=3Dy CONFIG_MAGIC_SYSRQ=3Dy CONFIG_DEBUG_FS=3Dy # CONFIG_SLUB_DEBUG is not set -# CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAAB328C86A for ; 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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:52 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , "Martin K. Petersen" , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 05/10] ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER Date: Tue, 10 Jun 2025 12:00:18 +0200 Message-ID: <20250610100139.2476555-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA BMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index d40ca9edd264..917bc8a27794 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -180,6 +180,7 @@ CONFIG_TOUCHSCREEN_COLIBRI_VF50=3Dy CONFIG_INPUT_MISC=3Dy CONFIG_INPUT_MMA8450=3Dy CONFIG_INPUT_GPIO_BEEPER=3Dm +CONFIG_INPUT_PWM_BEEPER=3Dy CONFIG_SERIO_SERPORT=3Dm # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=3Dy --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFCD528CF51 for ; Tue, 10 Jun 2025 10:01:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549718; cv=none; b=iYw3HP99Am5WqyLOtkjxHVPu1WTO2kStYZHxum6ct4tndR5tvlbvGzbs5w+ez2FpwF21zWMyHF6PJp/JmBIgT9CguLXK9J4Jq5UPysi5olbHwlA67GcBrOTJ+FGLqvZWddwFprP3ukITBInljxkUkaLiHCD4Xh/67XvEZ3dcj08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549718; c=relaxed/simple; bh=Wu0oggdHIMl21yHRrD1q1OTM30QUCT5J7qOjRFSBCVU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WhqUlOhIuo0hTf3bsECWMQp1NBqWst/jfUNzYv6hS/qiSxTh7zfsM4cNhU57Vgrst9XIRJ8/ZfAe+0RXefXKuH0CmWEgIOnkJg5r1ORfQZdSkMf+VIseJFih5X4IC/hE31rVEst9huNp5S8H0YDqBmGBbVqPJ1r90hRNtnnnnPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=hN3XBndy; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="hN3XBndy" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-6077dea37easo6197299a12.3 for ; Tue, 10 Jun 2025 03:01:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749549715; x=1750154515; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g+CuR2t2agnTd143XnFYj6BBOX9cjwJ9yRR8SSRtGwA=; b=hN3XBndyLKreH1iDzNkb1aOuniPYZ7VoJ43FKEU51W99ac683tIeo8I4ZQ5CsVTRvs etlBEocfg0APdg+6gVgWKLLkhBIzE928aMlkFz4eezwaAwt8i9V+GbJxbO93IM010n6m 7HFrhY2ovLP2wP+LXJ1dMHHn8C6zeMiTDh0oY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749549715; x=1750154515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g+CuR2t2agnTd143XnFYj6BBOX9cjwJ9yRR8SSRtGwA=; b=ROxpqGMZ+nV/3OnkwwvhP+ZuEUHMFzjzfqpc9fbQwofRzX2wjHekHrpV5GD/lac1Hv 0uJeTbmBlU9ksHniA4Ngo/7OyHdr9hmzFYb9KBg5WQRMKzwImJ2ftkUg6ijFCAgnoDUv z+lX7lfPxdavXqi7hlxIlluoVIb5iCLVbtr/k+VAn5hgu2OnQlC2P2ZwJDVlGtEc6k3k Cu5QYqpr4M9Vds+mx82dWQEb8vz9+y45fT7PQ6pY/+0lARJn9jq4Rz2QBJ2ooDdAx05x +B/qt9a/XBB/BBUzwYrMVecweqdLOuqhFQi2Tq/Y9WkPifjXPxT3TQpuRRdWFxL+qfGW sRLA== X-Gm-Message-State: AOJu0YzS2BKWtXgbE7MqJX53T+V7gcHj7ppsgBqwSWU4czeCwnm8CYBK D5BXgrDMdCiMOz9Q02BloBq2HEw4MHREZ5vC9BcrWibXn05AvPpAm9WRHoHeoVVs2Tvg9vYM7Rn jJHCk X-Gm-Gg: ASbGncvFddTzp7ZthgCx81wxmEFsojDCGWC/DSHz9Kd/71x+zqQJaLBsCb9oO3Q/hKq +1/q/ZyhD05QneCqgII1p5o047JEAtR8m7JalZzvOUBU0Lq5JWpf6JfuaE0bPMz1oXfJDljASy/ VxB1d9A5a9NbchuJDrc5KIjfCr3TAt290a6w7j9mVdZFDiUHM8LE5Rdz8jG+WvwCEd2oLVI24+p K2BTidC1Pgl6SxS5IuAI5kN2wczPbYxVaJsW3nNyrVfBtEUL6tYAVXgzoZE7TqNq5SSnHAjUBM1 IqiQsRCfOyAKNJcc0reiGiwaI+nmFW5r1MViglSnU/XFjX3N5Hil3JlOsxI1TEYYB0HQ+TSTuyt l/GYgJ2GxEy3iHLIb3rYRVUDjSVE= X-Google-Smtp-Source: AGHT+IE3bgkWoQ9nO8aNuMn9ZSpoWZlBdl446ax7t76j4zMgmTGWKmlQCyK3iwCOhkvKgG6kJdBnbw== X-Received: by 2002:a05:6402:2755:b0:608:330a:9f67 with SMTP id 4fb4d7f45d1cf-608330a9fe8mr1072507a12.32.1749549714754; Tue, 10 Jun 2025 03:01:54 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:54 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v3 06/10] dt-bindings: arm: fsl: support Engicam MicroGEA RMM board Date: Tue, 10 Jun 2025 12:00:19 +0200 Message-ID: <20250610100139.2476555-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA RMM board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5feb62611e53..58492b1cd468 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull =20 --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38F2528D830 for ; Tue, 10 Jun 2025 10:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549720; cv=none; b=jaf3mf7lpiVc2YU0tKZ8JU+C/DH22iCxIbgYXs1Ofk/6gDzvDzVh9gkM9qnP/OH8xCsOgGq77VWqiwiOdoO2zmeXY5wpA0xOhF+KXo1jzqr2vnOV9MA+q/0OCVMgQVY737Rdqw1P5dUkK0x7ftnRwPQHGGZvvEA4c1vtKWWPGK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549720; c=relaxed/simple; bh=9tM9Dcyi+/k4fnr1E37c6ioXXs1rnsf9r8aVxyuQTBo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R6BEeM5ekGlvokuPCsy330USNybiYTqWQWN0Xm2FnwbRIcs2adKN/7n2CAFzunIpckGDeKT05hmAgAleF++t/bI2HbuxdOa/JyGNM3FohqiPrWmcGdnIdb+Hrye9/WevlPRqqJXRVRvp6I7h3Q8A6QinE0kPbAFnH0WjxxGr0L4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=QAUSBeJ5; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="QAUSBeJ5" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-605b9488c28so8388686a12.2 for ; Tue, 10 Jun 2025 03:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749549716; x=1750154516; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NzU44oFIncgqylxLFeMRxY+MTav72CKFZJoQGUQ1xP0=; b=QAUSBeJ5slpsg6OQDgs/NSo4r+OeNKuh57YREXiP5kudSjG/64SfeSMRWdToRvojgV KwxJCQp7EqDk/ABPYLXWFMp0H/1MI59Naab12R+ikDhyMP/00NF/kWSOYGKrWVRAaxN9 6Gyp2gsiy50EHxoqmtPb2aj6tz2jAPADcdIEo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749549716; x=1750154516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NzU44oFIncgqylxLFeMRxY+MTav72CKFZJoQGUQ1xP0=; b=FTuk4JVHlst/pozW3BGI2H6OXbQiEEk1tX56PR9GAPLKNkMQmQ2w5tm6h01aZZzyHt BBsFz2ol2PvJLQxt5f0rREei0kE6AWbZSZP8vO7CcROgvk2oei5J0QrUvZy5FbXuSeoi 3tZgHTaNFMFV03t7vEqXqXdBF/2XfKdSMta+KkZdw2D+FXYMR/a05Z1RgFamE9V0fHlY LuKWDjfIZVkoHaQzjNeG7fm9INIxbJBDEM+7k49PX7JFM9hcXVpaaQSBR133QbrjSp+h TlBuXTVJw1d7eTEN61JL8ndysIJmsAM4yTm4IxXTLd3Guzng0cxDc4zul3iMwLzK6+bA lxzA== X-Gm-Message-State: AOJu0YzPiKZ6ApIImfIrOct4X8ftdJaLUeVZb0IROREePP6zzcybPdv1 UhXxxAnEY4473PzGm6lQF02uO5Te/6bEyNFHp2Te1A+UDyTnWGaY7touROBgn22lu4uJc0mK3WR WElr4 X-Gm-Gg: ASbGnctlDJL+1yhcU5xEVmaDlhzJJ7crwGMZa5jhpfrPxABBLWs4dPzEgQeEXEzY2Py 7fvCf3MllJZp3MWVWIxSfdzfRxqbOvdozoMivXxbxYEHeEvau3Xv3+ZMB4x3bxHryVb+myqUnkS 75mpxa3UM2aiiuj8nibWZesXAYWl4JQL5dEy7Xm9gLRfgeOFejqGX0wc5iegsNyBdqm+Hp0Um03 xHUjEwGaYI8vtiG9EwFDfT9i7u5rWNd9aTjYsUgcL83hGVJRMTlKyf8Ek44skqHvMON5d8PPkgQ bbGC8UHIS4cfeNE66kg2viKerp662/MrVUkqlsZjUCNMezFSCiVFqBO4N0r2bvXeVoP9bnmCamr Ix0Zp+tLeR40fYha7DM4LY6S+p00= X-Google-Smtp-Source: AGHT+IGj5tqaAC+AXyXAC77UlosqSG2qp+9m6AliZ5zM9dOzOWNV/SXg1hFlSjfq8usYzavcdi+F/g== X-Received: by 2002:a05:6402:50d2:b0:605:2da5:8483 with SMTP id 4fb4d7f45d1cf-60773ec9198mr14596141a12.13.1749549716378; Tue, 10 Jun 2025 03:01:56 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:56 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 07/10] ARM: dts: imx6ul: support Engicam MicroGEA RMM board Date: Tue, 10 Jun 2025 12:00:20 +0200 Message-ID: <20250610100139.2476555-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan Reviewed-by: Frank Li --- Changes in v3: - Rename sgtl5000 node to audio-codec. - Move the reg property of the audio-codec node right after the compatible property. - Drop an extra blank line from iomuxc and iomuxc_snvs nodes. Changes in v2: - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. - Add Reviewed-by tag of Peng Fan arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-rmm.dts | 360 ++++++++++++++++++ 2 files changed, 361 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 57f185198217..32dfd69b8d8b 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..5d1cc8a1f555 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-rmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-rmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>; + + led-0 { + gpios =3D <&gpio2 10 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpio2 11 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <100000>; + status =3D "okay"; + + touchscreen: touchscreen@38 { + compatible =3D"edt,edt-ft5306"; + reg =3D <0x38>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_touchscreen>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <8 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio2 14 GPIO_ACTIVE_LOW>; + report-rate-hz =3D <6>; + /* settings valid only for Hycon touchscreen */ + touchscreen-size-x =3D <1280>; + touchscreen-size-y =3D <800>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: audio-codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + #sound-dai-cells =3D <0>; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb1_vbus>; + disable-over-current; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + vbus-supply =3D <®_usb2_vbus>; + disable-over-current; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x130b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_touchscreen: touchgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x17059 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_reg_usb1: regusb1grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_reg_ext_pwr: reg-ext-pwrgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x17059 + >; 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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:57 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH v3 08/10] dt-bindings: arm: fsl: support Engicam MicroGEA GTW board Date: Tue, 10 Jun 2025 12:00:21 +0200 Message-ID: <20250610100139.2476555-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA GTW board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Changes in v3: - Add Acked-by tag of Conor Dooley. Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 58492b1cd468..99ff7c78544b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-gtw # i.MX6ULL Engicam Micr= oGEA GTW Board - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull --=20 2.43.0 From nobody Sun Feb 8 09:09:31 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12B8A28D8EC for ; Tue, 10 Jun 2025 10:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549723; cv=none; b=JrrEAWTOvdKcNQU64Y/AvCqA40spw2vRJeAbtKv99iv4C6N0Zc1x56TFLP2Re+ifRKwqcfzawfGb9KUe7xpF8sqFvihiyH5CWNufSRLFHIIZXxohbXPO/0ZzQ+hZH+DvKaYCknugfArN3NtfrnTXLKGSqEJd/VjY0SGCeJPT2yA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749549723; c=relaxed/simple; bh=sUY8Qm2rT225RsjUKHgiJWexr6mDGTPhcZ8PJQwOxr8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IoV6BbLe3zDm0627aebo+9u+Qzy+PX4jtUpkQq3x1XchH6ez5cO6YQX09nomiZU3C+0xSMdtj9fuui88ugThG9HZtaagJAAYgAfF5dIV2EeUnLSS5kwtKNfcW5nwVBT7Q60g6hkE0h6Jz9inytWUHO3Z2yg9mQ23V4zMZTwEFH8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=XvS1PXEL; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="XvS1PXEL" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-607c5715ef2so4132134a12.0 for ; Tue, 10 Jun 2025 03:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749549720; x=1750154520; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KzzLaojZq6S39goZRBGJmPMmLZK8oRVTymDDUaNmjK8=; b=XvS1PXELdevvRvgQ0BR6TEOkKlf78dIQ3wIm6DlShYUBTNpRy486lD2EQs/GadY4jo yViqdi/lJrymduJoWXgrl5yqAU5PkNELarht9aaenffLKj5kTYM01C9A0DBP1VvEVjQd wfQeKVx6EwZx17UD9oK7LdVxFkyne4v7zW7O0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749549720; x=1750154520; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KzzLaojZq6S39goZRBGJmPMmLZK8oRVTymDDUaNmjK8=; b=D5JO7cgBt+EepfBhqa4iR0gbrNiTUQ7cBwfOAUL8kjOB0jS1GV4+IsO/kAkzjgCvp2 4rSb653VMGgpagtqg52KXrPdIrpfJ5xcug8rVjcmNhiGY16m3yk/84t4+rmSnUiQycx4 lZS8lloVogVLDP+mkHsFxoqfPCcfNU3E6vFc4Iqg8Km1cHqni7WexzFM9cVqQqIXKflK 4LxnxeIhc0u7g8vw6xYeHzWaPOAepR6qWKo03E1U4zuKAxPstR578LZACzVyITulFFML yltNNs6Ko682vuyfJUxI+GfuactRvOwwabincx2p7taQY7BWQ/8t2+i7AvtJuHGLjFxR ByLQ== X-Gm-Message-State: AOJu0Yw1fLs28iSmrVMJSzmLgM4OgJzWiV4ugtx4SVZ1C+XBZoFwbLmD PqdvAN1LxM8592s1OxAMzlCZPSo/2fv1iw1CUO7lQCtKFnFaAbEOLBRXeVBijG12zbPQvSrqOzx xMpwM X-Gm-Gg: ASbGncs5OEjQE28X27TEwS1wlnzezfUTtdYJpLa5XqxsM2cUi4C8pJGKOXtWHBz2nZw J5jK8A+7UkCKMYtNVgqxZSyiKEAFSPW9sb6g5SGMapMIMHjAFnmN2E7IiXFzf0Up9LJKHQFH9eW d2rpiXIhQlateV6sGlhpnhOGbLqakUjsSES3pVDwNewhdAZ8a4YKo+dakdCxlefUbVG3Ll7HxtR Do9ur7Ju9ls6BB2DUtti4FG8YGrkOMYQWFHNHILTtkCoDqjwV5WqYaTD5ukriwDEqGOgPr4o/M2 UDu1iumJNV9NWKqrTe8KLOLeYA4RHdSjuTio/Jh09oRiXYKsnsnasGz+eSO4nY2FNQyIpJVfTPD yZulxdJV5y2qZiXeN7SgqH1ycCIE= X-Google-Smtp-Source: AGHT+IH2dLOiWE95kMS36GEMfR3+nsxWqc34N4l1VIXOOEfkgDPGuvDfAP3EITz6N3UYOwZQN8jeag== X-Received: by 2002:a05:6402:350e:b0:5e6:17e6:9510 with SMTP id 4fb4d7f45d1cf-6077341892cmr13964073a12.6.1749549720073; Tue, 10 Jun 2025 03:02:00 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:01:59 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 09/10] ARM: dts: imx6ul: support Engicam MicroGEA GTW board Date: Tue, 10 Jun 2025 12:00:22 +0200 Message-ID: <20250610100139.2476555-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi --- Changes in v3: - Drop an extra blank line from the iomuxc node. Changes in v2: - Drop an extra blank line - Move iomuxc and iomuxc_snvs nodes to the end of the DTS file. arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-gtw.dts | 162 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 32dfd69b8d8b..de4142e8f3ce 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-gtw.dtb \ imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts new file mode 100644 index 000000000000..d500f8839102 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-gtw", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL GTW Board"; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_keys>; + + user-button { + label =3D "User button"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>, <&pinctrl_pwrled>; + + led-0 { + gpios =3D <&gpio5 7 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + led-1 { + gpios =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + gpios =3D <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios =3D <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_hub: usb-hub { + compatible =3D "smsc,usb3503a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_hub>; + reset-gpios =3D <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x130b0 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x130b0 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_pwrled: ledsgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x130b0 + >; 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([2.196.40.179]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6077837ed0bsm5953438a12.36.2025.06.10.03.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 03:02:01 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 10/10] ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503 Date: Tue, 10 Jun 2025 12:00:23 +0200 Message-ID: <20250610100139.2476555-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> References: <20250610100139.2476555-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA GTW board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 917bc8a27794..3181775a214d 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -335,6 +335,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=3Dm CONFIG_USB_SERIAL_OPTION=3Dm CONFIG_USB_TEST=3Dm CONFIG_USB_EHSET_TEST_FIXTURE=3Dm +CONFIG_USB_HSIC_USB3503=3Dy CONFIG_USB_ONBOARD_DEV=3Dy CONFIG_NOP_USB_XCEIV=3Dy CONFIG_USB_MXS_PHY=3Dy --=20 2.43.0