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Tue, 10 Jun 2025 02:22:27 -0700 (PDT) From: Yunhui Cui To: arnd@arndb.de, andriy.shevchenko@linux.intel.com, benjamin.larsson@genexis.eu, cuiyunhui@bytedance.com, gregkh@linuxfoundation.org, heikki.krogerus@linux.intel.com, ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org, jkeeping@inmusicbrands.com, john.ogness@linutronix.de, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, markus.mayer@linaro.org, matt.porter@linaro.org, namcao@linutronix.de, paulmck@kernel.org, pmladek@suse.com, schnelle@linux.ibm.com, sunilvl@ventanamicro.com, tim.kryger@linaro.org Cc: stable@vger.kernel.org Subject: [PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR Date: Tue, 10 Jun 2025 17:21:32 +0800 Message-Id: <20250610092135.28738-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250610092135.28738-1-cuiyunhui@bytedance.com> References: <20250610092135.28738-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the PSLVERR_RESP_EN parameter is set to 1, the device generates an error response if an attempt is made to read an empty RBR (Receive Buffer Register) while the FIFO is enabled. In serial8250_do_startup(), calling serial_port_out(port, UART_LCR, UART_LCR_WLEN8) triggers dw8250_check_lcr(), which invokes dw8250_force_idle() and serial8250_clear_and_reinit_fifos(). The latter function enables the FIFO via serial_out(p, UART_FCR, p->fcr). Execution proceeds to the serial_port_in(port, UART_RX). This satisfies the PSLVERR trigger condition. When another CPU (e.g., using printk()) is accessing the UART (UART is busy), the current CPU fails the check (value & ~UART_LCR_SPAR) =3D=3D (lcr & ~UART_LCR_SPAR) in dw8250_check_lcr(), causing it to enter dw8250_force_idle(). Put serial_port_out(port, UART_LCR, UART_LCR_WLEN8) under the port->lock to fix this issue. Panic backtrace: [ 0.442336] Oops - unknown exception [#1] [ 0.442343] epc : dw8250_serial_in32+0x1e/0x4a [ 0.442351] ra : serial8250_do_startup+0x2c8/0x88e ... [ 0.442416] console_on_rootfs+0x26/0x70 Fixes: c49436b657d0 ("serial: 8250_dw: Improve unwritable LCR workaround") Link: https://lore.kernel.org/all/84cydt5peu.fsf@jogness.linutronix.de/T/ Signed-off-by: Yunhui Cui Cc: stable@vger.kernel.org Reviewed-by: John Ogness --- drivers/tty/serial/8250/8250_port.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/= 8250_port.c index 6d7b8c4667c9c..07fe818dffa34 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -2376,9 +2376,10 @@ int serial8250_do_startup(struct uart_port *port) /* * Now, initialize the UART */ - serial_port_out(port, UART_LCR, UART_LCR_WLEN8); =20 uart_port_lock_irqsave(port, &flags); + serial_port_out(port, UART_LCR, UART_LCR_WLEN8); + if (up->port.flags & UPF_FOURPORT) { if (!up->port.irq) up->port.mctrl |=3D TIOCM_OUT1; --=20 2.39.5 From nobody Sun Feb 8 23:13:38 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE42D28B41D for ; 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Tue, 10 Jun 2025 02:22:34 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236032fc9ebsm66968605ad.106.2025.06.10.02.22.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jun 2025 02:22:34 -0700 (PDT) From: Yunhui Cui To: arnd@arndb.de, andriy.shevchenko@linux.intel.com, benjamin.larsson@genexis.eu, cuiyunhui@bytedance.com, gregkh@linuxfoundation.org, heikki.krogerus@linux.intel.com, ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org, jkeeping@inmusicbrands.com, john.ogness@linutronix.de, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, markus.mayer@linaro.org, matt.porter@linaro.org, namcao@linutronix.de, paulmck@kernel.org, pmladek@suse.com, schnelle@linux.ibm.com, sunilvl@ventanamicro.com, tim.kryger@linaro.org Cc: stable@vger.kernel.org Subject: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT Date: Tue, 10 Jun 2025 17:21:33 +0800 Message-Id: <20250610092135.28738-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250610092135.28738-1-cuiyunhui@bytedance.com> References: <20250610092135.28738-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DW UART may trigger the RX_TIMEOUT interrupt without data present and remain stuck in this state indefinitely. The dw8250_handle_irq() function detects this condition by checking if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When detected, it performs a "dummy read" to recover the DW UART from this state. When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX while the FIFO is enabled and UART_LSR_DR is not set will generate a PSLVERR error, which may lead to a system panic. There are two methods to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading UART_RX when the FIFO is enabled, and the other is to read UART_RX when the FIFO is disabled. Given these two scenarios, the FIFO must be disabled before the "dummy read" operation and re-enabled afterward to maintain normal UART functionality. Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx = timeout interrupt") Signed-off-by: Yunhui Cui Cc: stable@vger.kernel.org --- drivers/tty/serial/8250/8250_dw.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index 1902f29444a1c..082b7fcf251db 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p) uart_port_lock_irqsave(p, &flags); status =3D serial_lsr_in(up); =20 - if (!(status & (UART_LSR_DR | UART_LSR_BI))) + if (!(status & (UART_LSR_DR | UART_LSR_BI))) { + /* To avoid PSLVERR, disable the FIFO first. */ + if (up->fcr & UART_FCR_ENABLE_FIFO) + serial_out(up, UART_FCR, 0); + serial_port_in(p, UART_RX); =20 + if (up->fcr & UART_FCR_ENABLE_FIFO) + serial_out(up, UART_FCR, up->fcr); + } + uart_port_unlock_irqrestore(p, flags); } =20 --=20 2.39.5 From nobody Sun Feb 8 23:13:38 2026 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7925428B41D for ; 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Tue, 10 Jun 2025 02:22:41 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236032fc9ebsm66968605ad.106.2025.06.10.02.22.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jun 2025 02:22:41 -0700 (PDT) From: Yunhui Cui To: arnd@arndb.de, andriy.shevchenko@linux.intel.com, benjamin.larsson@genexis.eu, cuiyunhui@bytedance.com, gregkh@linuxfoundation.org, heikki.krogerus@linux.intel.com, ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org, jkeeping@inmusicbrands.com, john.ogness@linutronix.de, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, markus.mayer@linaro.org, matt.porter@linaro.org, namcao@linutronix.de, paulmck@kernel.org, pmladek@suse.com, schnelle@linux.ibm.com, sunilvl@ventanamicro.com, tim.kryger@linaro.org Subject: [PATCH v9 3/4] serial: 8250: avoid potential PSLVERR issue Date: Tue, 10 Jun 2025 17:21:34 +0800 Message-Id: <20250610092135.28738-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250610092135.28738-1-cuiyunhui@bytedance.com> References: <20250610092135.28738-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the PSLVERR_RESP_EN parameter is set to 1, reading UART_RX while the FIFO is enabled and UART_LSR_DR is not set will generate a PSLVERR error. Failure to check the UART_LSR_DR before reading UART_RX, or the non- atomic nature of clearing the FIFO and reading UART_RX, poses potential risks that could lead to PSLVERR. PSLVERR is addressed through two methods. One is to introduce serial8250_discard_data() to check whether UART_LSR_DR is set before reading UART_RX, thus solving the PSLVERR issue when the FIFO is enabled. The other is to place FIFO clearing and reading of UART_RX under port->lock. Signed-off-by: Yunhui Cui Reviewed-by: John Ogness --- drivers/tty/serial/8250/8250.h | 13 +++++++++++++ drivers/tty/serial/8250/8250_port.c | 26 +++++++++++++++----------- 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 18530c31a5981..b3fb8a550db35 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -162,6 +162,19 @@ static inline u16 serial_lsr_in(struct uart_8250_port = *up) return lsr; } =20 +/* + * To avoid PSLVERR, check UART_LSR_DR in UART_LSR before + * reading UART_RX. + */ +static inline void serial8250_discard_data(struct uart_8250_port *up) +{ + u16 lsr; + + lsr =3D serial_in(up, UART_LSR); + if (lsr & UART_LSR_DR) + serial_in(up, UART_RX); +} + /* * For the 16C950 */ diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/= 8250_port.c index 07fe818dffa34..0560df9b064f9 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -764,8 +764,6 @@ static void disable_rsa(struct uart_8250_port *up) =20 if (up->port.type =3D=3D PORT_RSA && up->port.uartclk =3D=3D SERIAL_RSA_BAUD_BASE * 16) { - uart_port_lock_irq(&up->port); - mode =3D serial_in(up, UART_RSA_MSR); result =3D !(mode & UART_RSA_MSR_FIFO); =20 @@ -777,7 +775,6 @@ static void disable_rsa(struct uart_8250_port *up) =20 if (result) up->port.uartclk =3D SERIAL_RSA_BAUD_BASE_LO * 16; - uart_port_unlock_irq(&up->port); } } #endif /* CONFIG_SERIAL_8250_RSA */ @@ -1353,9 +1350,8 @@ static void autoconfig_irq(struct uart_8250_port *up) /* Synchronize UART_IER access against the console. */ uart_port_lock_irq(port); serial_out(up, UART_IER, UART_IER_ALL_INTR); + serial8250_discard_data(up); uart_port_unlock_irq(port); - serial_in(up, UART_LSR); - serial_in(up, UART_RX); serial_in(up, UART_IIR); serial_in(up, UART_MSR); serial_out(up, UART_TX, 0xFF); @@ -2260,13 +2256,20 @@ int serial8250_do_startup(struct uart_port *port) * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ + uart_port_lock_irqsave(port, &flags); serial8250_clear_fifos(up); =20 /* - * Clear the interrupt registers. + * Read UART_RX to clear interrupts (e.g., Character Timeout). + * To prevent PSLVERR, we can either disable the FIFO before reading + * UART_RX or read UART_RX only when UART_LSR_DR is set while the FIFO + * remains enabled. If using the latter approach to avoid PSLVERR, it + * creates a contradiction with the interrupt-clearing (see the + * rx_timeout handling in dw8250_handle_irq()). */ serial_port_in(port, UART_LSR); serial_port_in(port, UART_RX); + uart_port_unlock_irqrestore(port, flags); serial_port_in(port, UART_IIR); serial_port_in(port, UART_MSR); =20 @@ -2423,15 +2426,13 @@ int serial8250_do_startup(struct uart_port *port) } } =20 - uart_port_unlock_irqrestore(port, flags); - /* * Clear the interrupt registers again for luck, and clear the * saved flags to avoid getting false values from polling * routines or the previous session. */ - serial_port_in(port, UART_LSR); - serial_port_in(port, UART_RX); + serial8250_discard_data(up); + uart_port_unlock_irqrestore(port, flags); serial_port_in(port, UART_IIR); serial_port_in(port, UART_MSR); up->lsr_saved_flags =3D 0; @@ -2513,7 +2514,6 @@ void serial8250_do_shutdown(struct uart_port *port) port->mctrl &=3D ~TIOCM_OUT2; =20 serial8250_set_mctrl(port, port->mctrl); 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Tue, 10 Jun 2025 02:22:47 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-236032fc9ebsm66968605ad.106.2025.06.10.02.22.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jun 2025 02:22:47 -0700 (PDT) From: Yunhui Cui To: arnd@arndb.de, andriy.shevchenko@linux.intel.com, benjamin.larsson@genexis.eu, cuiyunhui@bytedance.com, gregkh@linuxfoundation.org, heikki.krogerus@linux.intel.com, ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org, jkeeping@inmusicbrands.com, john.ogness@linutronix.de, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, markus.mayer@linaro.org, matt.porter@linaro.org, namcao@linutronix.de, paulmck@kernel.org, pmladek@suse.com, schnelle@linux.ibm.com, sunilvl@ventanamicro.com, tim.kryger@linaro.org Subject: [PATCH v9 4/4] serial: 8250_dw: assert port->lock is held in dw8250_force_idle() Date: Tue, 10 Jun 2025 17:21:35 +0800 Message-Id: <20250610092135.28738-5-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250610092135.28738-1-cuiyunhui@bytedance.com> References: <20250610092135.28738-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reading UART_RX and checking whether UART_LSR_DR is set should be atomic. Ensure the caller of dw8250_force_idle() holds port->lock. Signed-off-by: Yunhui Cui --- drivers/tty/serial/8250/8250_dw.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index 082b7fcf251db..686f9117a3339 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -117,6 +118,9 @@ static void dw8250_force_idle(struct uart_port *p) struct uart_8250_port *up =3D up_to_u8250p(p); unsigned int lsr; =20 + /* Reading UART_LSR and UART_RX should be atomic. */ + lockdep_assert_held_once(&p->lock); + /* * The following call currently performs serial_out() * against the FCR register. Because it differs to LCR --=20 2.39.5