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charset="utf-8" On MT8186 and MT8188 one of the NVMEM cells contains the GPU speed bin value. In combination with the GPU OPP bindings, on these two platforms there is an implied scheme of converting the cell value to what the GPU OPP "opp-supported-hw" property matches. This does not apply to the base mediatek,efuse hardware, nor does it apply to any of the other platforms that do not have the GPU speed bin cell. The platform maintainer argues that this makes the compatibles incompatible with the base "mediatek,efuse" compatible, as shown in the link given. Deprecate the MT8186/MT8188 + "mediatek,efuse" combination, and add new entries with MT8186 being the base model and MT8188 falling back to MT8186. Link: https://lore.kernel.org/all/11028242-afe4-474a-9d76-cd1bd9208987@coll= abora.com/ Fixes: ff1df1886f43 ("dt-bindings: nvmem: mediatek: efuse: Add support for = MT8188") Cc: Johnson Wang Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/nvmem/mediatek,efuse.yaml | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 32b8c1eb4e80..4dc0d42df3e6 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -24,6 +24,21 @@ properties: =20 compatible: oneOf: + - items: + - const: mediatek,mt8188-efuse + - const: mediatek,mt8186-efuse + - const: mediatek,mt8186-efuse + + - items: + - enum: + - mediatek,mt8186-efuse + - mediatek,mt8188-efuse + - const: mediatek,efuse + deprecated: true + description: Some compatibles also imply a decoding scheme for the + "gpu-speedbin" cell, and thus are not backward compatible to the + generic "mediatek,efuse" compatible. + - items: - enum: - mediatek,mt7622-efuse @@ -33,8 +48,6 @@ properties: - mediatek,mt7988-efuse - mediatek,mt8173-efuse - mediatek,mt8183-efuse - - mediatek,mt8186-efuse - - mediatek,mt8188-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse --=20 2.50.0.rc0.604.gd4ff7b7c86-goog From nobody Mon Feb 9 14:36:30 2026 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31898278E53 for ; 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charset="utf-8" The efuse block in the MT8188 contains the GPU speed bin cell, and like the MT8186 one, has the same conversion scheme to work with the GPU OPP binding. This was reflected in a corresponding change to the efuse DT binding. Change the fallback compatible of the MT8188's efuse block from the generic one to the MT8186 one. This also makes GPU DVFS work properly. Fixes: d39aacd1021a ("arm64: dts: mediatek: mt8188: add lvts definitions") Fixes: 50e7592cb696 ("arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM= cells") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 202478407727..90c388f1890f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,7 +2183,7 @@ imp_iic_wrap_en: clock-controller@11ec2000 { }; =20 efuse: efuse@11f20000 { - compatible =3D "mediatek,mt8188-efuse", "mediatek,efuse"; + compatible =3D "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg =3D <0 0x11f20000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.50.0.rc0.604.gd4ff7b7c86-goog