From nobody Thu Dec 18 17:57:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D8B925DD01; Tue, 10 Jun 2025 04:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749528639; cv=none; b=ec1m9mO8FjVpiGQElxoRBy6cAgMPGdGxF+fI6cUR4P532hmcKx/UimthTxvnPZ4E8eoJ9uGie+O2S19CntUAGcMG0YF2tg1lzoSY3CrAByV3vUYJWJlAnDlVtrfcQseT9oyHEXpzIUvDsCRlf/LkrgYjaG2EOzbljSx29/qCLN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749528639; c=relaxed/simple; bh=i5XtsnR2wPfheA7SPloU6EYrhD8dBiD5/7VcQ0yyE+c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IHUbUaTu5v2r1RhmlmXfVEfMHHnFqU1SbyHwPJRqWeUa5hCBNI0QKMG8kOub8HXjk1ylK34FjHaq2lGyGLEjo5YojqR6FNT8oaWNYP9SPSxJKb1ROvc/fDGmsUbVWU+smoCf6xfrrQ9o3pkctj0yly6TrvVOvHvChARvXKF9hmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Mlxx/nQY; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Mlxx/nQY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1749528637; x=1781064637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i5XtsnR2wPfheA7SPloU6EYrhD8dBiD5/7VcQ0yyE+c=; b=Mlxx/nQY33aQJ/AxA64gmre5sZeeQjQSgHtcpQNa2yhwtIvGaeyDnS67 V05o1U3H2aZc7Au0L1ZpSGF+lpT/Q5naaIbisr0SmWpIO41raFImj9JRq nuRRGSEIvLeDCbayrJkLw1xr6/JQZiDtu7ONMC6YP1MeqHqHq8UMCYDI3 rz4gHacni8HCLboGk/3az3hrgno0RJaJsKIVCHq0uHG2y16CHDaEid8G6 XaURwaXoT2l+EUFID+VUD3xc9Wzv0I5jVikIQilKHb9/71iw5zCKMgpZZ SHw2UKpLwXp1bu0BuIFvpelG4cpIctqOq4Przvhor9nGHH3ectEJFC1LH A==; X-CSE-ConnectionGUID: OS7m6HxzQSmnc7/JkTL/3w== X-CSE-MsgGUID: jzjCxRlASFWOs4v7c5ETKQ== X-IronPort-AV: E=McAfee;i="6800,10657,11459"; a="51613165" X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="51613165" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 21:10:37 -0700 X-CSE-ConnectionGUID: EwnFYOEiT9malKOoNeKkGA== X-CSE-MsgGUID: WIgNssLbQqqdsFhricKzqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="177646721" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by orviesa002.jf.intel.com with ESMTP; 09 Jun 2025 21:10:33 -0700 From: Arkadiusz Kubalewski To: donald.hunter@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, jiri@resnulli.us, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, andrew+netdev@lunn.ch, aleksandr.loktionov@intel.com, corbet@lwn.net Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-rdma@vger.kernel.org, linux-doc@vger.kernel.org, Arkadiusz Kubalewski , Milena Olech , Jiri Pirko Subject: [PATCH net-next v5 1/3] dpll: add reference-sync netlink attribute Date: Tue, 10 Jun 2025 06:04:34 +0200 Message-Id: <20250610040436.1669826-2-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> References: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add new netlink attribute to allow user space configuration of reference sync pin pairs, where both pins are used to provide one clock signal consisting of both: base frequency and sync signal. Reviewed-by: Przemek Kitszel Reviewed-by: Milena Olech Reviewed-by: Jiri Pirko Signed-off-by: Arkadiusz Kubalewski --- v5: - rephrease dpll docs, make clear a Reference SYNC doesn't require a pair of Reference SYNC signals. - rebase. --- Documentation/driver-api/dpll.rst | 25 +++++++++++++++++++++++++ Documentation/netlink/specs/dpll.yaml | 19 +++++++++++++++++++ drivers/dpll/dpll_nl.c | 10 ++++++++-- drivers/dpll/dpll_nl.h | 1 + include/uapi/linux/dpll.h | 1 + 5 files changed, 54 insertions(+), 2 deletions(-) diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/d= pll.rst index e6855cd37e85..71755ab8ef6d 100644 --- a/Documentation/driver-api/dpll.rst +++ b/Documentation/driver-api/dpll.rst @@ -235,6 +235,31 @@ the pin. ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 +Reference SYNC +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The device may support the Reference SYNC feature, which allows the combin= ation +of two inputs into a input pair. In this configuration, clock signals +from both inputs are used to synchronize the dpll device. The higher frequ= ency +signal is utilized for the loop bandwidth of the DPLL, while the lower fre= quency +signal is used to syntonize the output signal of the DPLL device. This fea= ture +enables the provision of a high-quality loop bandwidth signal from an exte= rnal +source. + +A capable input provides a list of inputs that can be bound with to create +Reference SYNC. To control this feature, the user must request a desired +state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or +``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be +bound to only one other pin at any given time. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or + requesting configuration of the Reference + SYNC feature + ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature + ``DPLL_A_PIN_STATE`` state of Reference SYNC connection + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Configuration commands group =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =20 diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/= specs/dpll.yaml index 8feefeae5376..333b4596b36f 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -406,6 +406,15 @@ attribute-sets: doc: | A ratio of high to low state of a SYNC signal pulse embedded into base clock frequency. Value is in percents. + - + name: reference-sync + type: nest + multi-attr: true + nested-attributes: reference-sync + doc: | + Capable pin provides list of pins that can be bound to create a + reference-sync pin pair. + - name: pin-parent-device subset-of: pin @@ -436,6 +445,14 @@ attribute-sets: name: frequency-min - name: frequency-max + - + name: reference-sync + subset-of: pin + attributes: + - + name: id + - + name: state =20 operations: enum-name: dpll_cmd @@ -574,6 +591,7 @@ operations: - esync-frequency - esync-frequency-supported - esync-pulse + - reference-sync =20 dump: request: @@ -601,6 +619,7 @@ operations: - parent-pin - phase-adjust - esync-frequency + - reference-sync - name: pin-create-ntf doc: Notification about pin appearing diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c index fe9b6893d261..d709a8dc304f 100644 --- a/drivers/dpll/dpll_nl.c +++ b/drivers/dpll/dpll_nl.c @@ -24,6 +24,11 @@ const struct nla_policy dpll_pin_parent_pin_nl_policy[DP= LL_A_PIN_STATE + 1] =3D { [DPLL_A_PIN_STATE] =3D NLA_POLICY_RANGE(NLA_U32, 1, 3), }; =20 +const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1= ] =3D { + [DPLL_A_PIN_ID] =3D { .type =3D NLA_U32, }, + [DPLL_A_PIN_STATE] =3D NLA_POLICY_RANGE(NLA_U32, 1, 3), +}; + /* DPLL_CMD_DEVICE_ID_GET - do */ static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + = 1] =3D { [DPLL_A_MODULE_NAME] =3D { .type =3D NLA_NUL_STRING, }, @@ -62,7 +67,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_polic= y[DPLL_A_PIN_ID + 1] =3D }; =20 /* DPLL_CMD_PIN_SET - do */ -static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FRE= QUENCY + 1] =3D { +static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_REFERENCE= _SYNC + 1] =3D { [DPLL_A_PIN_ID] =3D { .type =3D NLA_U32, }, [DPLL_A_PIN_FREQUENCY] =3D { .type =3D NLA_U64, }, [DPLL_A_PIN_DIRECTION] =3D NLA_POLICY_RANGE(NLA_U32, 1, 2), @@ -72,6 +77,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPL= L_A_PIN_ESYNC_FREQUENCY [DPLL_A_PIN_PARENT_PIN] =3D NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_poli= cy), [DPLL_A_PIN_PHASE_ADJUST] =3D { .type =3D NLA_S32, }, [DPLL_A_PIN_ESYNC_FREQUENCY] =3D { .type =3D NLA_U64, }, + [DPLL_A_PIN_REFERENCE_SYNC] =3D NLA_POLICY_NESTED(dpll_reference_sync_nl_= policy), }; =20 /* Ops table for dpll */ @@ -139,7 +145,7 @@ static const struct genl_split_ops dpll_nl_ops[] =3D { .doit =3D dpll_nl_pin_set_doit, .post_doit =3D dpll_pin_post_doit, .policy =3D dpll_pin_set_nl_policy, - .maxattr =3D DPLL_A_PIN_ESYNC_FREQUENCY, + .maxattr =3D DPLL_A_PIN_REFERENCE_SYNC, .flags =3D GENL_ADMIN_PERM | GENL_CMD_CAP_DO, }, }; diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h index f491262bee4f..3da10cfe9a6e 100644 --- a/drivers/dpll/dpll_nl.h +++ b/drivers/dpll/dpll_nl.h @@ -14,6 +14,7 @@ /* Common nested types */ extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN= _PHASE_OFFSET + 1]; extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_ST= ATE + 1]; +extern const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_ST= ATE + 1]; =20 int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h index bf97d4b6d51f..f6cb6209566c 100644 --- a/include/uapi/linux/dpll.h +++ b/include/uapi/linux/dpll.h @@ -237,6 +237,7 @@ enum dpll_a_pin { DPLL_A_PIN_ESYNC_FREQUENCY, DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, DPLL_A_PIN_ESYNC_PULSE, + DPLL_A_PIN_REFERENCE_SYNC, =20 __DPLL_A_PIN_MAX, DPLL_A_PIN_MAX =3D (__DPLL_A_PIN_MAX - 1) --=20 2.38.1 From nobody Thu Dec 18 17:57:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 837FA25EF90; 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a="51613192" X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="51613192" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 21:10:42 -0700 X-CSE-ConnectionGUID: LX0aL7B6QI2UdmrNIjGY+A== X-CSE-MsgGUID: yFU2wVr4QQCsk8Jmrmh5qA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="177646760" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by orviesa002.jf.intel.com with ESMTP; 09 Jun 2025 21:10:37 -0700 From: Arkadiusz Kubalewski To: donald.hunter@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, jiri@resnulli.us, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, andrew+netdev@lunn.ch, aleksandr.loktionov@intel.com, corbet@lwn.net Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-rdma@vger.kernel.org, linux-doc@vger.kernel.org, Arkadiusz Kubalewski , Milena Olech , Jiri Pirko Subject: [PATCH net-next v5 2/3] dpll: add reference sync get/set Date: Tue, 10 Jun 2025 06:04:35 +0200 Message-Id: <20250610040436.1669826-3-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> References: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define function for reference sync pin registration and callback ops to set/get current feature state. Implement netlink handler to fill netlink messages with reference sync pin configuration of capable pins (pin-get). Implement netlink handler to call proper ops and configure reference sync pin state (pin-set). Reviewed-by: Przemek Kitszel Reviewed-by: Milena Olech Reviewed-by: Jiri Pirko Signed-off-by: Arkadiusz Kubalewski --- v5: - rebase. --- drivers/dpll/dpll_core.c | 45 +++++++++ drivers/dpll/dpll_core.h | 2 + drivers/dpll/dpll_netlink.c | 190 ++++++++++++++++++++++++++++++++---- drivers/dpll/dpll_netlink.h | 2 + include/linux/dpll.h | 13 +++ 5 files changed, 233 insertions(+), 19 deletions(-) diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c index 20bdc52f63a5..1f698f521ea3 100644 --- a/drivers/dpll/dpll_core.c +++ b/drivers/dpll/dpll_core.c @@ -506,6 +506,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, refcount_set(&pin->refcount, 1); xa_init_flags(&pin->dpll_refs, XA_FLAGS_ALLOC); xa_init_flags(&pin->parent_refs, XA_FLAGS_ALLOC); + xa_init_flags(&pin->ref_sync_pins, XA_FLAGS_ALLOC); ret =3D xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b, &dpll_pin_xa_id, GFP_KERNEL); if (ret < 0) @@ -514,6 +515,7 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module= *module, err_xa_alloc: xa_destroy(&pin->dpll_refs); xa_destroy(&pin->parent_refs); + xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); err_pin_prop: kfree(pin); @@ -595,6 +597,7 @@ void dpll_pin_put(struct dpll_pin *pin) xa_erase(&dpll_pin_xa, pin->id); xa_destroy(&pin->dpll_refs); xa_destroy(&pin->parent_refs); + xa_destroy(&pin->ref_sync_pins); dpll_pin_prop_free(&pin->prop); kfree_rcu(pin, rcu); } @@ -659,11 +662,26 @@ dpll_pin_register(struct dpll_device *dpll, struct dp= ll_pin *pin, } EXPORT_SYMBOL_GPL(dpll_pin_register); =20 +static void dpll_pin_ref_sync_pair_del(u32 ref_sync_pin_id) +{ + struct dpll_pin *pin, *ref_sync_pin; + unsigned long i; + + xa_for_each(&dpll_pin_xa, i, pin) { + ref_sync_pin =3D xa_load(&pin->ref_sync_pins, ref_sync_pin_id); + if (ref_sync_pin) { + xa_erase(&pin->ref_sync_pins, ref_sync_pin_id); + __dpll_pin_change_ntf(pin); + } + } +} + static void __dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, const struct dpll_pin_ops *ops, void *priv, void *cookie) { ASSERT_DPLL_PIN_REGISTERED(pin); + dpll_pin_ref_sync_pair_del(pin->id); dpll_xa_ref_pin_del(&dpll->pin_refs, pin, ops, priv, cookie); dpll_xa_ref_dpll_del(&pin->dpll_refs, dpll, ops, priv, cookie); if (xa_empty(&pin->dpll_refs)) @@ -783,6 +801,33 @@ void dpll_pin_on_pin_unregister(struct dpll_pin *paren= t, struct dpll_pin *pin, } EXPORT_SYMBOL_GPL(dpll_pin_on_pin_unregister); =20 +/** + * dpll_pin_ref_sync_pair_add - create a reference sync signal pin pair + * @pin: pin which produces the base frequency + * @ref_sync_pin: pin which produces the sync signal + * + * Once pins are paired, the user-space configuration of reference sync pa= ir + * is possible. + * Context: Acquires a lock (dpll_lock) + * Return: + * * 0 on success + * * negative - error value + */ +int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin, + struct dpll_pin *ref_sync_pin) +{ + int ret; + + mutex_lock(&dpll_lock); + ret =3D xa_insert(&pin->ref_sync_pins, ref_sync_pin->pin_idx, + ref_sync_pin, GFP_KERNEL); + __dpll_pin_change_ntf(pin); + mutex_unlock(&dpll_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dpll_pin_ref_sync_pair_add); + static struct dpll_device_registration * dpll_device_registration_first(struct dpll_device *dpll) { diff --git a/drivers/dpll/dpll_core.h b/drivers/dpll/dpll_core.h index 2b6d8ef1cdf3..93c68e78b351 100644 --- a/drivers/dpll/dpll_core.h +++ b/drivers/dpll/dpll_core.h @@ -44,6 +44,7 @@ struct dpll_device { * @module: module of creator * @dpll_refs: hold referencees to dplls pin was registered with * @parent_refs: hold references to parent pins pin was registered with + * @ref_sync_pins: hold references to pins for Reference SYNC feature * @prop: pin properties copied from the registerer * @rclk_dev_name: holds name of device when pin can recover clock from it * @refcount: refcount @@ -56,6 +57,7 @@ struct dpll_pin { struct module *module; struct xarray dpll_refs; struct xarray parent_refs; + struct xarray ref_sync_pins; struct dpll_pin_properties prop; refcount_t refcount; struct rcu_head rcu; diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index c130f87147fa..7c46bac7bcd3 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -48,6 +48,24 @@ dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 = id) return 0; } =20 +static bool dpll_pin_available(struct dpll_pin *pin) +{ + struct dpll_pin_ref *par_ref; + unsigned long i; + + if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) + return false; + xa_for_each(&pin->parent_refs, i, par_ref) + if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, + DPLL_REGISTERED)) + return true; + xa_for_each(&pin->dpll_refs, i, par_ref) + if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, + DPLL_REGISTERED)) + return true; + return false; +} + /** * dpll_msg_add_pin_handle - attach pin handle attribute to a given message * @msg: pointer to sk_buff message to attach a pin handle @@ -408,6 +426,47 @@ dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpl= l_pin *pin, return -EMSGSIZE; } =20 +static int +dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, + struct dpll_pin_ref *ref, + struct netlink_ext_ack *extack) +{ + const struct dpll_pin_ops *ops =3D dpll_pin_ops(ref); + struct dpll_device *dpll =3D ref->dpll; + void *pin_priv, *ref_sync_pin_priv; + struct dpll_pin *ref_sync_pin; + enum dpll_pin_state state; + struct nlattr *nest; + unsigned long index; + int ret; + + pin_priv =3D dpll_pin_on_dpll_priv(dpll, pin); + xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { + if (!dpll_pin_available(ref_sync_pin)) + continue; + ref_sync_pin_priv =3D dpll_pin_on_dpll_priv(dpll, ref_sync_pin); + if (WARN_ON(!ops->ref_sync_get)) + return -EOPNOTSUPP; + ret =3D ops->ref_sync_get(pin, pin_priv, ref_sync_pin, + ref_sync_pin_priv, &state, extack); + if (ret) + return ret; + nest =3D nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); + if (!nest) + return -EMSGSIZE; + if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) + goto nest_cancel; + if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) + goto nest_cancel; + nla_nest_end(msg, nest); + } + return 0; + +nest_cancel: + nla_nest_cancel(msg, nest); + return -EMSGSIZE; +} + static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) { int fs; @@ -550,6 +609,10 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_= pin *pin, if (ret) return ret; ret =3D dpll_msg_add_pin_esync(msg, pin, ref, extack); + if (ret) + return ret; + if (!xa_empty(&pin->ref_sync_pins)) + ret =3D dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); if (ret) return ret; if (xa_empty(&pin->parent_refs)) @@ -642,24 +705,6 @@ __dpll_device_change_ntf(struct dpll_device *dpll) return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); } =20 -static bool dpll_pin_available(struct dpll_pin *pin) -{ - struct dpll_pin_ref *par_ref; - unsigned long i; - - if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) - return false; - xa_for_each(&pin->parent_refs, i, par_ref) - if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, - DPLL_REGISTERED)) - return true; - xa_for_each(&pin->dpll_refs, i, par_ref) - if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, - DPLL_REGISTERED)) - return true; - return false; -} - /** * dpll_device_change_ntf - notify that the dpll device has been changed * @dpll: registered dpll pointer @@ -722,7 +767,7 @@ int dpll_pin_delete_ntf(struct dpll_pin *pin) return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); } =20 -static int __dpll_pin_change_ntf(struct dpll_pin *pin) +int __dpll_pin_change_ntf(struct dpll_pin *pin) { return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); } @@ -887,6 +932,108 @@ dpll_pin_esync_set(struct dpll_pin *pin, struct nlatt= r *a, return ret; } =20 +static int +dpll_pin_ref_sync_state_set(struct dpll_pin *pin, + unsigned long ref_sync_pin_idx, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack) + +{ + struct dpll_pin_ref *ref, *failed; + const struct dpll_pin_ops *ops; + enum dpll_pin_state old_state; + struct dpll_pin *ref_sync_pin; + struct dpll_device *dpll; + unsigned long i; + int ret; + + ref_sync_pin =3D xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, + ULONG_MAX, XA_PRESENT); + if (!ref_sync_pin) { + NL_SET_ERR_MSG(extack, "reference sync pin not found"); + return -EINVAL; + } + if (!dpll_pin_available(ref_sync_pin)) { + NL_SET_ERR_MSG(extack, "reference sync pin not available"); + return -EINVAL; + } + ref =3D dpll_xa_ref_dpll_first(&pin->dpll_refs); + ASSERT_NOT_NULL(ref); + ops =3D dpll_pin_ops(ref); + if (!ops->ref_sync_set || !ops->ref_sync_get) { + NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); + return -EOPNOTSUPP; + } + dpll =3D ref->dpll; + ret =3D ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), + ref_sync_pin, + dpll_pin_on_dpll_priv(dpll, ref_sync_pin), + &old_state, extack); + if (ret) { + NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); + return ret; + } + if (state =3D=3D old_state) + return 0; + xa_for_each(&pin->dpll_refs, i, ref) { + ops =3D dpll_pin_ops(ref); + dpll =3D ref->dpll; + ret =3D ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), + ref_sync_pin, + dpll_pin_on_dpll_priv(dpll, + ref_sync_pin), + state, extack); + if (ret) { + failed =3D ref; + NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", + dpll->id); + goto rollback; + } + } + __dpll_pin_change_ntf(pin); + + return 0; + +rollback: + xa_for_each(&pin->dpll_refs, i, ref) { + if (ref =3D=3D failed) + break; + ops =3D dpll_pin_ops(ref); + dpll =3D ref->dpll; + if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), + ref_sync_pin, + dpll_pin_on_dpll_priv(dpll, ref_sync_pin), + old_state, extack)) + NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); + } + return ret; +} + +static int +dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, + struct netlink_ext_ack *extack) +{ + struct nlattr *tb[DPLL_A_PIN_MAX + 1]; + enum dpll_pin_state state; + u32 sync_pin_id; + + nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, + dpll_reference_sync_nl_policy, extack); + if (!tb[DPLL_A_PIN_ID]) { + NL_SET_ERR_MSG(extack, "sync pin id expected"); + return -EINVAL; + } + sync_pin_id =3D nla_get_u32(tb[DPLL_A_PIN_ID]); + + if (!tb[DPLL_A_PIN_STATE]) { + NL_SET_ERR_MSG(extack, "sync pin state expected"); + return -EINVAL; + } + state =3D nla_get_u32(tb[DPLL_A_PIN_STATE]); + + return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); +} + static int dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, enum dpll_pin_state state, @@ -1193,6 +1340,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struc= t genl_info *info) if (ret) return ret; break; + case DPLL_A_PIN_REFERENCE_SYNC: + ret =3D dpll_pin_ref_sync_set(pin, a, info->extack); + if (ret) + return ret; + break; } } =20 diff --git a/drivers/dpll/dpll_netlink.h b/drivers/dpll/dpll_netlink.h index a9cfd55f57fc..dd28b56d27c5 100644 --- a/drivers/dpll/dpll_netlink.h +++ b/drivers/dpll/dpll_netlink.h @@ -11,3 +11,5 @@ int dpll_device_delete_ntf(struct dpll_device *dpll); int dpll_pin_create_ntf(struct dpll_pin *pin); =20 int dpll_pin_delete_ntf(struct dpll_pin *pin); + +int __dpll_pin_change_ntf(struct dpll_pin *pin); diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 5e4f9ab1cf75..024dc8d660a0 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -95,6 +95,16 @@ struct dpll_pin_ops { const struct dpll_device *dpll, void *dpll_priv, struct dpll_pin_esync *esync, struct netlink_ext_ack *extack); + int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_sync_pin, + void *ref_sync_pin_priv, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack); + int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_sync_pin, + void *ref_sync_pin_priv, + enum dpll_pin_state *state, + struct netlink_ext_ack *extack); }; =20 struct dpll_pin_frequency { @@ -194,6 +204,9 @@ int dpll_pin_on_pin_register(struct dpll_pin *parent, s= truct dpll_pin *pin, void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *= pin, const struct dpll_pin_ops *ops, void *priv); =20 +int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin, + struct dpll_pin *ref_sync_pin); + int dpll_device_change_ntf(struct dpll_device *dpll); =20 int dpll_pin_change_ntf(struct dpll_pin *pin); --=20 2.38.1 From nobody Thu Dec 18 17:57:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47DD125DB09; Tue, 10 Jun 2025 04:10:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="51613216" X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="51613216" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2025 21:10:47 -0700 X-CSE-ConnectionGUID: UN0J4MucT0SuRvbmZlcIOw== X-CSE-MsgGUID: xCJEsukUSXuWAQdx2kCIgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,224,1744095600"; d="scan'208";a="177646795" Received: from amlin-018-114.igk.intel.com ([10.102.18.114]) by orviesa002.jf.intel.com with ESMTP; 09 Jun 2025 21:10:43 -0700 From: Arkadiusz Kubalewski To: donald.hunter@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, jiri@resnulli.us, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, andrew+netdev@lunn.ch, aleksandr.loktionov@intel.com, corbet@lwn.net Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org, linux-rdma@vger.kernel.org, linux-doc@vger.kernel.org, Arkadiusz Kubalewski , Milena Olech Subject: [PATCH net-next v5 3/3] ice: add ref-sync dpll pins Date: Tue, 10 Jun 2025 06:04:36 +0200 Message-Id: <20250610040436.1669826-4-arkadiusz.kubalewski@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> References: <20250610040436.1669826-1-arkadiusz.kubalewski@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement reference sync input pin get/set callbacks, allow user space control over dpll pin pairs capable of reference sync support. Reviewed-by: Milena Olech Signed-off-by: Arkadiusz Kubalewski --- v5: - rebase. --- .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 + drivers/net/ethernet/intel/ice/ice_dpll.c | 186 ++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/= ethernet/intel/ice/ice_adminq_cmd.h index bdee499f991a..7fd0f0091d36 100644 --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h @@ -2288,6 +2288,8 @@ struct ice_aqc_get_cgu_abilities { u8 rsvd[3]; }; =20 +#define ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN BIT(7) + /* Set CGU input config (direct 0x0C62) */ struct ice_aqc_set_cgu_input_config { u8 input_idx; diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethern= et/intel/ice/ice_dpll.c index bce3ad6ca2a6..98f0c86f41fc 100644 --- a/drivers/net/ethernet/intel/ice/ice_dpll.c +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c @@ -12,6 +12,19 @@ #define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25 #define ICE_DPLL_PIN_GEN_RCLK_FREQ 1953125 =20 +#define ICE_SR_PFA_DPLL_DEFAULTS 0x152 +#define ICE_DPLL_PFA_REF_SYNC_TYPE 0x2420 +#define ICE_DPLL_PFA_REF_SYNC_TYPE2 0x2424 +#define ICE_DPLL_PFA_END 0xFFFF +#define ICE_DPLL_PFA_HEADER_LEN 4 +#define ICE_DPLL_PFA_ENTRY_LEN 3 +#define ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S 4 +#define ICE_DPLL_PFA_MASK_OFFSET 1 +#define ICE_DPLL_PFA_VALUE_OFFSET 2 + +#define ICE_DPLL_E810C_SFP_NC_PINS 2 +#define ICE_DPLL_E810C_SFP_NC_START 4 + /** * enum ice_dpll_pin_type - enumerate ice pin types: * @ICE_DPLL_PIN_INVALID: invalid pin type @@ -1314,6 +1327,89 @@ ice_dpll_input_esync_get(const struct dpll_pin *pin,= void *pin_priv, return 0; } =20 +/** + * ice_dpll_input_ref_sync_set - callback for setting reference sync featu= re + * @pin: pointer to a pin + * @pin_priv: private data pointer passed on pin registration + * @ref_pin: pin pointer for reference sync pair + * @ref_pin_priv: private data pointer of ref_pin + * @state: requested state for reference sync for pin pair + * @extack: error reporting + * + * Dpll subsystem callback. Handler for setting reference sync frequency + * feature for input pin. + * + * Context: Acquires and releases pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +static int +ice_dpll_input_ref_sync_set(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack) +{ + struct ice_dpll_pin *p =3D pin_priv; + struct ice_pf *pf =3D p->pf; + u8 flags_en =3D 0; + int ret; + + if (ice_dpll_is_reset(pf, extack)) + return -EBUSY; + mutex_lock(&pf->dplls.lock); + + if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) + flags_en =3D ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; + if (state =3D=3D DPLL_PIN_STATE_CONNECTED) + flags_en |=3D ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN; + ret =3D ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, flags_en, 0, 0); + if (!ret) + ret =3D ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_INPUT, + extack); + mutex_unlock(&pf->dplls.lock); + + return ret; +} + +/** + * ice_dpll_input_ref_sync_get - callback for getting reference sync config + * @pin: pointer to a pin + * @pin_priv: private data pointer passed on pin registration + * @ref_pin: pin pointer for reference sync pair + * @ref_pin_priv: private data pointer of ref_pin + * @state: on success holds reference sync state for pin pair + * @extack: error reporting + * + * Dpll subsystem callback. Handler for setting reference sync frequency + * feature for input pin. + * + * Context: Acquires and releases pf->dplls.lock + * Return: + * * 0 - success + * * negative - error + */ +static int +ice_dpll_input_ref_sync_get(const struct dpll_pin *pin, void *pin_priv, + const struct dpll_pin *ref_pin, void *ref_pin_priv, + enum dpll_pin_state *state, + struct netlink_ext_ack *extack) +{ + struct ice_dpll_pin *p =3D pin_priv; + struct ice_pf *pf =3D p->pf; + + if (ice_dpll_is_reset(pf, extack)) + return -EBUSY; + mutex_lock(&pf->dplls.lock); + if (p->flags[0] & ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN) + *state =3D DPLL_PIN_STATE_CONNECTED; + else + *state =3D DPLL_PIN_STATE_DISCONNECTED; + mutex_unlock(&pf->dplls.lock); + + return 0; +} + /** * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin * @pin: pointer to a pin @@ -1440,6 +1536,8 @@ static const struct dpll_pin_ops ice_dpll_input_ops = =3D { .phase_offset_get =3D ice_dpll_phase_offset_get, .esync_set =3D ice_dpll_input_esync_set, .esync_get =3D ice_dpll_input_esync_get, + .ref_sync_set =3D ice_dpll_input_ref_sync_set, + .ref_sync_get =3D ice_dpll_input_ref_sync_get, }; =20 static const struct dpll_pin_ops ice_dpll_output_ops =3D { @@ -1619,6 +1717,91 @@ static void ice_dpll_periodic_work(struct kthread_wo= rk *work) msecs_to_jiffies(500)); } =20 +/** + * ice_dpll_init_ref_sync_inputs - initialize reference sync pin pairs + * @pf: pf private structure + * + * Read DPLL TLV capabilities and initialize reference sync pin pairs in + * dpll subsystem. + * + * Return: + * * 0 - success or nothing to do (no ref-sync tlv are present) + * * negative - AQ failure + */ +static int ice_dpll_init_ref_sync_inputs(struct ice_pf *pf) +{ + struct ice_dpll_pin *inputs =3D pf->dplls.inputs; + struct ice_hw *hw =3D &pf->hw; + u16 addr, len, end, hdr; + int ret; + + ret =3D ice_get_pfa_module_tlv(hw, &hdr, &len, ICE_SR_PFA_DPLL_DEFAULTS); + if (ret) { + dev_err(ice_pf_to_dev(pf), + "Failed to read PFA dpll defaults TLV ret=3D%d\n", ret); + return ret; + } + end =3D hdr + len; + + for (addr =3D hdr + ICE_DPLL_PFA_HEADER_LEN; addr < end; + addr +=3D ICE_DPLL_PFA_ENTRY_LEN) { + unsigned long bit, ul_mask, offset; + u16 pin, mask, buf; + bool valid =3D false; + + ret =3D ice_read_sr_word(hw, addr, &buf); + if (ret) + return ret; + + switch (buf) { + case ICE_DPLL_PFA_REF_SYNC_TYPE: + case ICE_DPLL_PFA_REF_SYNC_TYPE2: + { + u16 mask_addr =3D addr + ICE_DPLL_PFA_MASK_OFFSET; + u16 val_addr =3D addr + ICE_DPLL_PFA_VALUE_OFFSET; + + ret =3D ice_read_sr_word(hw, mask_addr, &mask); + if (ret) + return ret; + ret =3D ice_read_sr_word(hw, val_addr, &pin); + if (ret) + return ret; + if (buf =3D=3D ICE_DPLL_PFA_REF_SYNC_TYPE) + pin >>=3D ICE_DPLL_PFA_MAILBOX_REF_SYNC_PIN_S; + valid =3D true; + break; + } + case ICE_DPLL_PFA_END: + addr =3D end; + break; + default: + continue; + } + if (!valid) + continue; + + ul_mask =3D mask; + offset =3D 0; + for_each_set_bit(bit, &ul_mask, BITS_PER_TYPE(u16)) { + int i, j; + + if (hw->device_id =3D=3D ICE_DEV_ID_E810C_SFP && + pin > ICE_DPLL_E810C_SFP_NC_START) + offset =3D -ICE_DPLL_E810C_SFP_NC_PINS; + i =3D pin + offset; + j =3D bit + offset; + if (i < 0 || j < 0) + return -ERANGE; + ret =3D dpll_pin_ref_sync_pair_add(inputs[i].pin, + inputs[j].pin); + if (ret) + return ret; + } + } + + return 0; +} + /** * ice_dpll_release_pins - release pins resources from dpll subsystem * @pins: pointer to pins array @@ -1936,6 +2119,9 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool= cgu) if (ret) return ret; if (cgu) { + ret =3D ice_dpll_init_ref_sync_inputs(pf); + if (ret) + goto deinit_inputs; ret =3D ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, pf->dplls.num_inputs, pf->dplls.num_outputs, --=20 2.38.1