From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CC522D9E0; Tue, 10 Jun 2025 12:33:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558800; cv=pass; b=WL/5tY32qoo0VLpPAvBEz1OLInwtaHQ/0K6lL9TYjsWWAzAt/6FL6xftm1x4HTUjPQEJ9hHjU5CjHnC3AsaMeN2Axz2C/wMPokCUs+3yLWwXeqghu1x5JiSAOeJaK0P+WiovqW8QJGZHVQr1euhrtI71PpnPfLaMvGGuBvGJLMo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558800; c=relaxed/simple; bh=eO2+e+Z6SVkDsCMkTxaUjbggom3QyHMw23h4D7QNraI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qkvyeb9w4FVpHuBLtxOQ96r+U+5oo9fFtA0QOd3FCL6SSuh/uTV+5IqBLk4nlHxVdMCE4lKwNEWohNWpnT1zTQ2R5VIUWRB7nAJqwY2HTOPhKwF2wGVatKluDmhXPqfnt5+rWpkV0IceGLOz+C42Z2o+g6Or1TetZzeyvqViWLs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=cB0jGed+; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="cB0jGed+" ARC-Seal: i=1; a=rsa-sha256; t=1749558771; cv=none; d=zohomail.com; s=zohoarc; b=Y/HWAl+BrVvwcj3QIGlOh+eH8RGYVyzKfX1d0+Tk1LKJ2zfwnXZKj+S6/GH2WWq4zNFFgBl/oPYGc4DzgsBqoKnNEES+pH+KoqXAgvJRv0YaCzEfZhoDQ8ANR1+ArGy2f3tPDbJ/R98v4f9xuEI8U2jBThJmCQ1iJkTA9FpEU5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749558771; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Tnp7bdW/um/Nf3Hkgt/EOyvTtoi0plo3EB+bh3F7o3o=; b=NGD2fXCk7pG4diymGtx2OYJQzF5bZl7zpEPKSP8+25n8fncHp+g7UQTJf///oIAUDD7quPWqiCVEDg4qAJTco3BQwqv4PbZ92HS94d3fJI9d+cZGIVtiVZr9ViKI1N4YsmmQN1vGYpf4ue+hwpsSCYuuwNIYnIm8BvaTw78sPGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749558771; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Tnp7bdW/um/Nf3Hkgt/EOyvTtoi0plo3EB+bh3F7o3o=; b=cB0jGed+HtxmlOcbiif09rpri7CVAT2t0+RhgfBMafdP8nxkDlGei+FEvTXK88iB xZ1iFy++EpOT6N+ZyiYTiHDW8LYzLxfv5pkClMP0jRo0DuWgv7muV/E3+rb2Zriw/zN bcgTF7p3bARCKb5czFkAnz+9k4e/laDT8542rA7k= Received: by mx.zohomail.com with SMTPS id 1749558770257746.9148597054228; Tue, 10 Jun 2025 05:32:50 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:37 +0200 Subject: [PATCH v6 1/7] thermal: rockchip: rename rk_tsadcv3_tshut_mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-1-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The "v" version specifier here refers to the hardware IP revision. Mainline deviated from downstream here by calling the v4 revision v3 as it didn't support the v3 hardware revision at all. This creates needless confusion, so rename it to rk_tsadcv4_tshut_mode to be consistent with what the hardware wants to be called. Signed-off-by: Nicolas Frattaroli Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index a8ad85feb68fbb7ec8d79602b16c47838ecb3c00..40c7d234c3ef99f69dd8db4d8c4= 7f9d493c0583d 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1045,7 +1045,7 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iom= em *regs, writel_relaxed(val, regs + TSADCV2_INT_EN); } =20 -static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, +static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, enum tshut_mode mode) { u32 val_gpio, val_cru; @@ -1297,7 +1297,7 @@ static const struct rockchip_tsadc_chip rk3588_tsadc_= data =3D { .get_temp =3D rk_tsadcv4_get_temp, .set_alarm_temp =3D rk_tsadcv3_alarm_temp, .set_tshut_temp =3D rk_tsadcv3_tshut_temp, - .set_tshut_mode =3D rk_tsadcv3_tshut_mode, + .set_tshut_mode =3D rk_tsadcv4_tshut_mode, .table =3D { .id =3D rk3588_code_table, .length =3D ARRAY_SIZE(rk3588_code_table), --=20 2.49.0 From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A0F629553A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-2-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Add a new compatible for the thermal sensor device on the RK3576 SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli Acked-by: Heiko Stuebner --- Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yam= l b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index b717ea8261ca24ebaf709f410ec6372de1366b8a..49ceed68c92ce5a32ed8d4f39bd= 88fd052de0e80 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -21,6 +21,7 @@ properties: - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc - rockchip,rk3568-tsadc + - rockchip,rk3576-tsadc - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc =20 --=20 2.49.0 From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBE5B293443; Tue, 10 Jun 2025 12:33:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558818; cv=pass; b=cf1PWDUH/d8UlCenxnZ/t4lpYKxUbVQIBrGuPRm+5FxV8PPEf+dCmkiJ1kJ5/6GX+eceHXObXYMEruCZI19ecEq+n/DYsg0KLBlZpC+l4MQB36XG64NszhMshduya9YvkUtU7bWvZc3WxWdX9SkoDwmTr1AtCYLzgVQjIMPInRQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558818; c=relaxed/simple; bh=vJjZ8FV71hmGWM/Fi2tfuywEghJNM8FdhK5uksVx/B8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RDfcLnAPuDVhRlkvBiTY3SmzcG87d/ythnJtJm6AT4Za52qcnF6rAtp+DWSjab5c/yrTCBuPvMb2dqeAxqCKQdXswbnn1mxxxY0At/s4BXnx7bvlW0aIv/FHYGjzzYU9i7nE/lMdWWKatWFZzQaHPBMogGjddylyfEKHymFcLac= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=Slr9JpiJ; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="Slr9JpiJ" ARC-Seal: i=1; a=rsa-sha256; t=1749558781; cv=none; d=zohomail.com; s=zohoarc; b=HrjOY+W4cCFSA4awnGSsWMRbUlfFTRDGjy2p1mQPrSds9KrrZhN5lY+6MlSiapWb2lXKaOS7RPTKNlEgUYpU2hkHCModV1LgaYLhH/zBrTgJZCpAphfKlIESGl8hGuYVafeXMaEvFmfpzgpyGdkiwON4W9CRJy3FxTyUOgsEzPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1749558781; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=QqVZpS1mMaiLHStCX0I5k62rBcrBowKTfedoAC9Jqi8=; b=mEpGxBwjKuM6BaAYvobE29OzAZb+xj/0U0w5ItRcdWmSUAJBo5Hlf2T9wcEiAl5LhV2qQIsWL7IXBP/Z8GR7wMFyxE2GQaDQTFr6Lsf5GayNwVM2dRKr1ZSAmqlWiWroztWLoyhu3i3wwiLbCnkt8fHC17wV58GCIAx6KvLHOkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749558781; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=QqVZpS1mMaiLHStCX0I5k62rBcrBowKTfedoAC9Jqi8=; b=Slr9JpiJJaDvMY65kIqzX3axOhy2mgQHbHNCluirvJ24edjS/dPyDLWPkmCvKLGj 1ECvuvmxgkrRC5Mx+uTi3Hy1Jzn96iRSFvmt2zcO06GSzIVADoly9XCp4BzvvDLFA79 Ckz1j6ETrYFWlo5NobiLVesCejouTuoAt84dEkO0= Received: by mx.zohomail.com with SMTPS id 1749558779319784.571732238441; Tue, 10 Jun 2025 05:32:59 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:39 +0200 Subject: [PATCH v6 3/7] thermal: rockchip: Support RK3576 SoC in the thermal driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-3-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli , Ye Zhang X-Mailer: b4 0.14.2 From: Ye Zhang The RK3576 SoC has six TS-ADC channels: TOP, BIG_CORE, LITTLE_CORE, DDR, NPU and GPU. Signed-off-by: Ye Zhang [ported to mainline, reworded commit message] Signed-off-by: Nicolas Frattaroli Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 40c7d234c3ef99f69dd8db4d8c47f9d493c0583d..89e3180667e2a8f0ef5542b0db4= d9e19a21a24d3 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1284,6 +1284,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc= _data =3D { }, }; =20 +static const struct rockchip_tsadc_chip rk3576_tsadc_data =3D { + /* top, big_core, little_core, ddr, npu, gpu */ + .chn_offset =3D 0, + .chn_num =3D 6, /* six channels for tsadc */ + .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp =3D 95000, + .initialize =3D rk_tsadcv8_initialize, + .irq_ack =3D rk_tsadcv4_irq_ack, + .control =3D rk_tsadcv4_control, + .get_temp =3D rk_tsadcv4_get_temp, + .set_alarm_temp =3D rk_tsadcv3_alarm_temp, + .set_tshut_temp =3D rk_tsadcv3_tshut_temp, + .set_tshut_mode =3D rk_tsadcv4_tshut_mode, + .table =3D { + .id =3D rk3588_code_table, + .length =3D ARRAY_SIZE(rk3588_code_table), + .data_mask =3D TSADCV4_DATA_MASK, + .mode =3D ADC_INCREMENT, + }, +}; + static const struct rockchip_tsadc_chip rk3588_tsadc_data =3D { /* top, big_core0, big_core1, little_core, center, gpu, npu */ .chn_offset =3D 0, @@ -1342,6 +1364,10 @@ static const struct of_device_id of_rockchip_thermal= _match[] =3D { .compatible =3D "rockchip,rk3568-tsadc", .data =3D (void *)&rk3568_tsadc_data, }, + { + .compatible =3D "rockchip,rk3576-tsadc", + .data =3D (void *)&rk3576_tsadc_data, + }, { .compatible =3D "rockchip,rk3588-tsadc", .data =3D (void *)&rk3588_tsadc_data, --=20 2.49.0 From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 129EA298CB8; Tue, 10 Jun 2025 12:33:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749558821; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-4-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Several Rockchip SoCs, such as the RK3576, can store calibration trim data for thermal sensors in OTP cells. This capability should be documented. Such a rockchip thermal sensor may reference cell handles that store both a chip-wide trim for all the sensors, as well as cell handles for each individual sensor channel pointing to that specific sensor's trim value. Additionally, the thermal sensor may optionally reference cells which store the base in terms of degrees celsius and decicelsius that the trim is relative to. Each SoC that implements this appears to have a slightly different combination of chip-wide trim, base, base fractional part and per-channel trim, so which ones do which is documented in the bindings. Reviewed-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli Acked-by: Heiko Stuebner --- .../bindings/thermal/rockchip-thermal.yaml | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yam= l b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 49ceed68c92ce5a32ed8d4f39bd88fd052de0e80..573f447cc26ed7100638277598b= 0e745d436fd01 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -40,6 +40,17 @@ properties: - const: tsadc - const: apb_pclk =20 + nvmem-cells: + items: + - description: cell handle to where the trim's base temperature is s= tored + - description: + cell handle to where the trim's tenths of Celsius base value is = stored + + nvmem-cell-names: + items: + - const: trim_base + - const: trim_base_frac + resets: minItems: 1 maxItems: 3 @@ -51,6 +62,12 @@ properties: - const: tsadc - const: tsadc-phy =20 + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + "#thermal-sensor-cells": const: 1 =20 @@ -72,6 +89,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] =20 +patternProperties: + "@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + description: sensor ID, a.k.a. channel number + + nvmem-cells: + items: + - description: handle of cell containing calibration data + + nvmem-cell-names: + items: + - const: trim + + required: + - reg + + unevaluatedProperties: false + required: - compatible - reg @@ -80,6 +118,29 @@ required: - clock-names - resets =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: rockchip,rk3568-tsadc + then: + properties: + nvmem-cells: false + nvmem-cell-names: false + - if: + not: + properties: + compatible: + contains: + enum: + - rockchip,rk3568-tsadc + - rockchip,rk3576-tsadc + then: + patternProperties: + "@[0-9a-f]+$": false + unevaluatedProperties: false =20 examples: --=20 2.49.0 From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A8D029995D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-5-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Many of the Rockchip SoCs support storing trim values for the sensors in factory programmable memory. These values specify a fixed offset from the sensor's returned temperature to get a more accurate picture of what temperature the silicon is actually at. The way this is implemented is with various OTP cells, which may be absent. There may both be whole-TSADC trim values, as well as per-sensor trim values. In the downstream driver, whole-chip trim values override the per-sensor trim values. This rewrite of the functionality changes the semantics to something I see as slightly more useful: allow the whole-chip trim values to serve as a fallback for lacking per-sensor trim values, instead of overriding already present sensor trim values. Additionally, the chip may specify an offset (trim_base, trim_base_frac) in degrees celsius and degrees decicelsius respectively which defines what the basis is from which the trim, if any, should be calculated from. By default, this is 30 degrees Celsius, but the chip can once again specify a different value through OTP cells. The implementation of these trim calculations have been tested extensively on an RK3576, where it was confirmed to get rid of pesky 1.8 degree Celsius offsets between certain sensors. Signed-off-by: Nicolas Frattaroli --- drivers/thermal/rockchip_thermal.c | 221 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 202 insertions(+), 19 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 89e3180667e2a8f0ef5542b0db4d9e19a21a24d3..3beff9b6fac3abe8948b56132b6= 18ff1bed57217 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -69,16 +70,18 @@ struct chip_tsadc_table { * struct rockchip_tsadc_chip - hold the private data of tsadc chip * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_slope: used to convert the trim code to a temperature in millicel= sius + * @tshut_temp: the hardware-controlled shutdown temperature value, with n= o trim * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) * @initialize: SoC special initialize tsadc controller method * @irq_ack: clear the interrupt * @control: enable/disable method for the tsadc controller - * @get_temp: get the temperature + * @get_temp: get the raw temperature, unadjusted by trim * @set_alarm_temp: set the high temperature interrupt * @set_tshut_temp: set the hardware-controlled shutdown temperature * @set_tshut_mode: set the hardware-controlled shutdown mode + * @get_trim_code: convert a hardware temperature code to one adjusted for= by trim * @table: the chip-specific conversion table */ struct rockchip_tsadc_chip { @@ -86,6 +89,9 @@ struct rockchip_tsadc_chip { int chn_offset; int chn_num; =20 + /* Used to convert trim code to trim temp */ + int trim_slope; + /* The hardware-controlled tshut property */ int tshut_temp; enum tshut_mode tshut_mode; @@ -105,6 +111,8 @@ struct rockchip_tsadc_chip { int (*set_tshut_temp)(const struct chip_tsadc_table *table, int chn, void __iomem *reg, int temp); void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); + int (*get_trim_code)(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac); =20 /* Per-table methods */ struct chip_tsadc_table table; @@ -114,12 +122,16 @@ struct rockchip_tsadc_chip { * struct rockchip_thermal_sensor - hold the information of thermal sensor * @thermal: pointer to the platform/configuration data * @tzd: pointer to a thermal zone + * @of_node: pointer to the device_node representing this sensor, if any * @id: identifier of the thermal sensor + * @trim_temp: per-sensor trim temperature value */ struct rockchip_thermal_sensor { struct rockchip_thermal_data *thermal; struct thermal_zone_device *tzd; + struct device_node *of_node; int id; + int trim_temp; }; =20 /** @@ -132,7 +144,11 @@ struct rockchip_thermal_sensor { * @pclk: the advanced peripherals bus clock * @grf: the general register file will be used to do static set by softwa= re * @regs: the base address of tsadc controller - * @tshut_temp: the hardware-controlled shutdown temperature value + * @trim_base: major component of sensor trim value, in Celsius + * @trim_base_frac: minor component of sensor trim value, in Decicelsius + * @trim: fallback thermal trim value for each channel + * @tshut_temp: the hardware-controlled shutdown temperature value, with n= o trim + * @trim_temp: the fallback trim temperature for the whole sensor * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) */ @@ -149,7 +165,12 @@ struct rockchip_thermal_data { struct regmap *grf; void __iomem *regs; =20 + int trim_base; + int trim_base_frac; + int trim; + int tshut_temp; + int trim_temp; enum tshut_mode tshut_mode; enum tshut_polarity tshut_polarity; }; @@ -249,6 +270,9 @@ struct rockchip_thermal_data { =20 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) =20 + +#define RK_MAX_TEMP (180000) + /** * struct tsadc_table - code to temperature conversion table * @code: the value of adc channel @@ -1061,6 +1085,15 @@ static void rk_tsadcv4_tshut_mode(int chn, void __io= mem *regs, writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); } =20 +static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table, + int code, int trim_base, int trim_base_frac) +{ + int temp =3D trim_base * 1000 + trim_base_frac * 100; + u32 base_code =3D rk_tsadcv2_temp_to_code(table, temp); + + return code - base_code; +} + static const struct rockchip_tsadc_chip px30_tsadc_data =3D { /* cpu, gpu */ .chn_offset =3D 0, @@ -1298,6 +1331,8 @@ static const struct rockchip_tsadc_chip rk3576_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv3_alarm_temp, .set_tshut_temp =3D rk_tsadcv3_tshut_temp, .set_tshut_mode =3D rk_tsadcv4_tshut_mode, + .get_trim_code =3D rk_tsadcv2_get_trim_code, + .trim_slope =3D 923, .table =3D { .id =3D rk3588_code_table, .length =3D ARRAY_SIZE(rk3588_code_table), @@ -1413,7 +1448,7 @@ static int rockchip_thermal_set_trips(struct thermal_= zone_device *tz, int low, i __func__, sensor->id, low, high); =20 return tsadc->set_alarm_temp(&tsadc->table, - sensor->id, thermal->regs, high); + sensor->id, thermal->regs, high + sensor->trim_temp); } =20 static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *= out_temp) @@ -1425,6 +1460,8 @@ static int rockchip_thermal_get_temp(struct thermal_z= one_device *tz, int *out_te =20 retval =3D tsadc->get_temp(&tsadc->table, sensor->id, thermal->regs, out_temp); + *out_temp -=3D sensor->trim_temp; + return retval; } =20 @@ -1433,6 +1470,104 @@ static const struct thermal_zone_device_ops rockchi= p_of_thermal_ops =3D { .set_trips =3D rockchip_thermal_set_trips, }; =20 +/** + * rockchip_get_efuse_value - read an OTP cell from a device node + * @np: pointer to the device node with the nvmem-cells property + * @cell_name: name of cell that should be read + * @value: pointer to where the read value will be placed + * + * Return: Negative errno on failure, during which *value will not be touc= hed, + * or 0 on success. + */ +static int rockchip_get_efuse_value(struct device_node *np, const char *ce= ll_name, + int *value) +{ + struct nvmem_cell *cell; + int ret =3D 0; + size_t len; + u8 *buf; + int i; + + cell =3D of_nvmem_cell_get(np, cell_name); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf =3D nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len > sizeof(*value)) { + ret =3D -ERANGE; + goto exit; + } + + /* Copy with implicit endian conversion */ + *value =3D 0; + for (i =3D 0; i < len; i++) + *value |=3D (int) buf[i] << (8 * i); + +exit: + kfree(buf); + return ret; +} + +static int rockchip_get_trim_configuration(struct device *dev, struct devi= ce_node *np, + struct rockchip_thermal_data *thermal) +{ + const struct rockchip_tsadc_chip *tsadc =3D thermal->chip; + int trim_base =3D 0, trim_base_frac =3D 0, trim =3D 0; + int trim_code; + int ret; + + thermal->trim_base =3D 0; + thermal->trim_base_frac =3D 0; + thermal->trim =3D 0; + + if (!tsadc->get_trim_code) + return 0; + + ret =3D rockchip_get_efuse_value(np, "trim_base", &trim_base); + if (ret < 0) { + if (ret =3D=3D -ENOENT) { + trim_base =3D 30; + dev_dbg(dev, "trim_base is absent, defaulting to 30\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + ret =3D rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac); + if (ret < 0) { + if (ret =3D=3D -ENOENT) { + dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n"); + } else { + dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n", + ERR_PTR(ret)); + return ret; + } + } + thermal->trim_base =3D trim_base; + thermal->trim_base_frac =3D trim_base_frac; + + /* + * If the tsadc node contains the trim property, then it is used in the + * absence of per-channel trim values + */ + if (!rockchip_get_efuse_value(np, "trim", &trim)) + thermal->trim =3D trim; + if (trim) { + trim_code =3D tsadc->get_trim_code(&tsadc->table, trim, + trim_base, trim_base_frac); + thermal->trim_temp =3D thermal->chip->trim_slope * trim_code; + } + + return 0; +} + static int rockchip_configure_from_dt(struct device *dev, struct device_node *np, struct rockchip_thermal_data *thermal) @@ -1493,6 +1628,8 @@ static int rockchip_configure_from_dt(struct device *= dev, if (IS_ERR(thermal->grf)) dev_warn(dev, "Missing rockchip,grf property\n"); =20 + rockchip_get_trim_configuration(dev, np, thermal); + return 0; } =20 @@ -1503,23 +1640,50 @@ rockchip_thermal_register_sensor(struct platform_de= vice *pdev, int id) { const struct rockchip_tsadc_chip *tsadc =3D thermal->chip; + struct device *dev =3D &pdev->dev; + int trim =3D thermal->trim; + int trim_code, tshut_temp; + int trim_temp =3D 0; int error; =20 + if (thermal->trim_temp) + trim_temp =3D thermal->trim_temp; + + if (tsadc->get_trim_code && sensor->of_node) { + error =3D rockchip_get_efuse_value(sensor->of_node, "trim", &trim); + if (error < 0 && error !=3D -ENOENT) { + dev_err(dev, "failed reading trim of sensor %d: %pe\n", + id, ERR_PTR(error)); + return error; + } + if (trim) { + trim_code =3D tsadc->get_trim_code(&tsadc->table, trim, + thermal->trim_base, + thermal->trim_base_frac); + trim_temp =3D thermal->chip->trim_slope * trim_code; + } + } + + sensor->trim_temp =3D trim_temp; + + dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp); + + tshut_temp =3D min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP); + tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); =20 - error =3D tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, - thermal->tshut_temp); + error =3D tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_t= emp); if (error) - dev_err(&pdev->dev, "%s: invalid tshut=3D%d, error=3D%d\n", - __func__, thermal->tshut_temp, error); + dev_err(dev, "%s: invalid tshut=3D%d, error=3D%d\n", + __func__, tshut_temp, error); =20 sensor->thermal =3D thermal; sensor->id =3D id; - sensor->tzd =3D devm_thermal_of_zone_register(&pdev->dev, id, sensor, + sensor->tzd =3D devm_thermal_of_zone_register(dev, id, sensor, &rockchip_of_thermal_ops); if (IS_ERR(sensor->tzd)) { error =3D PTR_ERR(sensor->tzd); - dev_err(&pdev->dev, "failed to register sensor %d: %d\n", + dev_err(dev, "failed to register sensor %d: %d\n", id, error); return error; } @@ -1542,9 +1706,11 @@ static int rockchip_thermal_probe(struct platform_de= vice *pdev) { struct device_node *np =3D pdev->dev.of_node; struct rockchip_thermal_data *thermal; + struct device_node *child; int irq; int i; int error; + u32 chn; =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) @@ -1595,6 +1761,18 @@ static int rockchip_thermal_probe(struct platform_de= vice *pdev) thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); =20 + for_each_available_child_of_node(np, child) { + if (!of_property_read_u32(child, "reg", &chn)) { + if (chn < thermal->chip->chn_num) + thermal->sensors[chn].of_node =3D child; + else + dev_warn(&pdev->dev, + "sensor address (%d) too large, ignoring its trim\n", + chn); + } + + } + for (i =3D 0; i < thermal->chip->chn_num; i++) { error =3D rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], @@ -1664,8 +1842,11 @@ static int __maybe_unused rockchip_thermal_suspend(s= truct device *dev) static int __maybe_unused rockchip_thermal_resume(struct device *dev) { struct rockchip_thermal_data *thermal =3D dev_get_drvdata(dev); - int i; + const struct rockchip_tsadc_chip *tsadc =3D thermal->chip; + struct rockchip_thermal_sensor *sensor; + int tshut_temp; int error; + int i; =20 error =3D clk_enable(thermal->clk); if (error) @@ -1679,21 +1860,23 @@ static int __maybe_unused rockchip_thermal_resume(s= truct device *dev) =20 rockchip_thermal_reset_controller(thermal->reset); =20 - thermal->chip->initialize(thermal->grf, thermal->regs, - thermal->tshut_polarity); + tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); =20 for (i =3D 0; i < thermal->chip->chn_num; i++) { - int id =3D thermal->sensors[i].id; + sensor =3D &thermal->sensors[i]; + + tshut_temp =3D min(thermal->tshut_temp + sensor->trim_temp, + RK_MAX_TEMP); =20 - thermal->chip->set_tshut_mode(id, thermal->regs, + tsadc->set_tshut_mode(sensor->id, thermal->regs, thermal->tshut_mode); =20 - error =3D thermal->chip->set_tshut_temp(&thermal->chip->table, - id, thermal->regs, - thermal->tshut_temp); + error =3D tsadc->set_tshut_temp(&thermal->chip->table, + sensor->id, thermal->regs, + tshut_temp); if (error) dev_err(dev, "%s: invalid tshut=3D%d, error=3D%d\n", - __func__, thermal->tshut_temp, error); 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Tue, 10 Jun 2025 05:33:13 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:42 +0200 Subject: [PATCH v6 6/7] arm64: dts: rockchip: Add thermal nodes to RK3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Add the TSADC node to the RK3576. Additionally, add everything the TSADC needs to function, i.e. thermal zones, their trip points and maps, as well as adjust the CPU cooling-cells property. The polling-delay properties are set to 0 as we do have interrupts for this TSADC on this particular SoC, though the polling-delay-passive properties are set to 100 for the thermal zones that have a passive cooling device, as otherwise the thermal throttling behaviour never unthrottles. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 +++++++++++++++++++++++++++= +++- 1 file changed, 162 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 1086482f04792325dc4c22fb8ceeb27eef59afe4..dbc527ec60cfac0bbdb881a27d3= ff765366be99e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include =20 / { compatible =3D "rockchip,rk3576"; @@ -113,9 +114,9 @@ cpu_l0: cpu@0 { capacity-dmips-mhz =3D <485>; clocks =3D <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 =3D <&cluster0_opp_table>; - #cooling-cells =3D <2>; dynamic-power-coefficient =3D <120>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_l1: cpu@1 { @@ -127,6 +128,7 @@ cpu_l1: cpu@1 { clocks =3D <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_l2: cpu@2 { @@ -138,6 +140,7 @@ cpu_l2: cpu@2 { clocks =3D <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_l3: cpu@3 { @@ -149,6 +152,7 @@ cpu_l3: cpu@3 { clocks =3D <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_b0: cpu@100 { @@ -159,9 +163,9 @@ cpu_b0: cpu@100 { capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 =3D <&cluster1_opp_table>; - #cooling-cells =3D <2>; dynamic-power-coefficient =3D <320>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_b1: cpu@101 { @@ -173,6 +177,7 @@ cpu_b1: cpu@101 { clocks =3D <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_b2: cpu@102 { @@ -184,6 +189,7 @@ cpu_b2: cpu@102 { clocks =3D <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 cpu_b3: cpu@103 { @@ -195,6 +201,7 @@ cpu_b3: cpu@103 { clocks =3D <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; + #cooling-cells =3D <2>; }; =20 idle-states { @@ -520,6 +527,143 @@ psci { method =3D "smc"; }; =20 + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&bigcore_alert>; + cooling-device =3D + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&littlecore_alert>; + cooling-device =3D + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , @@ -2285,6 +2429,22 @@ saradc: adc@2ae00000 { status =3D "disabled"; }; =20 + tsadc: tsadc@2ae70000 { + compatible =3D "rockchip,rk3576-tsadc"; + reg =3D <0x0 0x2ae70000 0x0 0x400>; + interrupts =3D ; + clocks =3D <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names =3D "tsadc", "apb_pclk"; + assigned-clocks =3D <&cru CLK_TSADC>; + assigned-clock-rates =3D <2000000>; + resets =3D <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names =3D "tsadc-apb", "tsadc"; + #thermal-sensor-cells =3D <1>; + rockchip,hw-tshut-temp =3D <120000>; + rockchip,hw-tshut-mode =3D <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity =3D <0>; /* tshut polarity 0:LOW 1:HIGH */ + }; + i2c9: i2c@2ae80000 { compatible =3D "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg =3D <0x0 0x2ae80000 0x0 0x1000>; --=20 2.49.0 From nobody Sat Oct 11 12:12:43 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A8829A9F9; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749558799; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=um6+orYZmvWyjIKPMULKaYcq3cJ+8tX54fBBdRjWSS4=; b=W0/9qBAL+3hppBxV14yeK/+YXV9ZLHBdKRb1IcsGBA7q/OdEWF51zA3ektCeiYGJ A7KcbEuelECBy6fus3Q64ZJVF0Rmrfa+Lu6PsO43vd+494aTq7xnAPVNEpSFF3sVR8U Qsa68HZvAeWbF9+JwfzSeRqkZxOR1A57QLNkBOT0= Received: by mx.zohomail.com with SMTPS id 1749558797642874.6088758885295; Tue, 10 Jun 2025 05:33:17 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:43 +0200 Subject: [PATCH v6 7/7] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com> References: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> In-Reply-To: <20250610-rk3576-tsadc-upstream-v6-0-b6e9efbf1015@collabora.com> To: Alexey Charkov , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jonas Karlman Cc: Sebastian Reichel , kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index dbc527ec60cfac0bbdb881a27d3ff765366be99e..c388fbb510ade0f06e64c1025dc= fa59b8187bc97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1919,6 +1919,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg =3D <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg =3D <0x24 0x2>; + bits =3D <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg =3D <0x26 0x2>; + bits =3D <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg =3D <0x28 0x2>; + bits =3D <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg =3D <0x2a 0x2>; + bits =3D <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg =3D <0x2c 0x2>; + bits =3D <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg =3D <0x64 0x2>; + bits =3D <0 10>; + }; }; =20 sai0: sai@2a600000 { @@ -2443,6 +2467,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp =3D <120000>; rockchip,hw-tshut-mode =3D <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity =3D <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells =3D <1>; + #size-cells =3D <0>; + + sensor@0 { + reg =3D <0>; + nvmem-cells =3D <&soc_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; + sensor@1 { + reg =3D <1>; + nvmem-cells =3D <&bigcore_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; + sensor@2 { + reg =3D <2>; + nvmem-cells =3D <&litcore_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; + sensor@3 { + reg =3D <3>; + nvmem-cells =3D <&ddr_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; + sensor@4 { + reg =3D <4>; + nvmem-cells =3D <&npu_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; + sensor@5 { + reg =3D <5>; + nvmem-cells =3D <&gpu_tsadc_trim>; + nvmem-cell-names =3D "trim"; + }; }; =20 i2c9: i2c@2ae80000 { --=20 2.49.0