From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51A6A29B789 for ; Tue, 10 Jun 2025 14:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564375; cv=none; b=R0BwOxHQUHmwh59f58da6IDFkAWa0xNPpWoDWPuJpraRior8myzv8l34ryDe7aZ+QyLhu29ZkJy9d9gDchSIlObZGPtgY8RXEn027zc3kTKmmQ6D1QG7oFYOGSqoDG81IaTNAO50g6KgsRFMGLmj/Uuq8/XH8nU5ivYhkM+9JKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564375; c=relaxed/simple; bh=6p3gmVNgeWpM5P5NgnZSHUvO6bicpNKcBnOP1+C75sg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LK7V1IxAvUbuYB4fCoC7nHUoPSlE6xhrSqSajxRSm6yMgRAO7t+hhQDKMygBc3ggZPZQ0Pzm1u/H9MUuEGdeQOJWTJ8mdvgiIa4TCW0NJd/Dvj6oRdsK2VCHYFbO3aoCu+yH8a1dh5i3XGeSzoqnFX90Fgieaj/rAh+q6EcO75w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=phRFrQBr; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="phRFrQBr" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3a4e575db1aso720737f8f.2 for ; Tue, 10 Jun 2025 07:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564372; x=1750169172; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B4X7DaN4+Map/kL0OnjyI+6NxQr2TtGJmMy/gmAt3s4=; b=phRFrQBrljrcRCzfuzcSLVY8F1cEMQM0goN6M0zSxW66J6znJU6Q9pZLGeAiqVwaIn az293bo4P7Dk+saEKLx0Wyi9vjaeVwbuAP9ZFU/YpV0lMYn4UNww00h0kDC+h9GDJEC8 fQylDdg8BwZpzdKTI+FAt7wB0VWnxnlS0S3vQhI2MQgxuGPLsOImfPJzAKhFseG0ctf4 7fGU0Q//YtXIzFap3d+uSZrrmQNF3g6LqQ0FT+BWwS0PLNz7rrfeRQFtv16jFveWhCtI S2brltkB+K3b72TobMlfZpE+r7LBkpo4RNTsd7rZ1eZ+ajyCekbA2AUqsX5k0/63KUMz QwWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564372; x=1750169172; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4X7DaN4+Map/kL0OnjyI+6NxQr2TtGJmMy/gmAt3s4=; b=SUCCzyMbARNDw86GQ5y6jFnPVe6z0DnNosOO1x2YzoTAiJrTCXjyOMaOdiYEHOP1vf yhae94HaWns+wHn6EIX0jRTqCHCDWIRI6yDE89LEVpcW4MwJz/hRRo6jedW+0bjGFbCD vz3dVw1L36lmjCa+2TV44lrr3sa6sKVrJNcEqQB5Nf7m9RjDcKJftrTBt6hlgidLQIJm MPcEKe45qEFqfwSQCw8OuBWZHX9RswsXnkcjZ7oSssoBib6yLIPDm/WfkBVVJDvx38Nl XYCJO9mrLVb1vNH0Hks50tiYkQtQKNaMDH2Wd7hwzHODZr75gD73Z+NOQFUldwqx3jcp LsFA== X-Forwarded-Encrypted: i=1; AJvYcCU6y8GS5z27mXGyW2kmxQYpcFXaEmruvfVruCnBRTaSGLtsC/cYhc8LtpMS9nX1EEskWgt9opMrFExD+pI=@vger.kernel.org X-Gm-Message-State: AOJu0Yy4NpNuOoZuUAnwRVgvXmNMzilH3A9GkzcpHPQNtGiteieQ+dGF Rv8QMkA36LDelBXgKAVc4xA9PX5DhMOvRGl80sf3dhiZXFMJikydabTxq2t/ljHiiGA= X-Gm-Gg: ASbGncu5oOt/Xg+a0rgfJ5GAHRQ+MWpeKdf43F1kc7BkGRsswtje608I+NlmNa2ODn4 m/P9HZI7Hm/ws9JqQ8lRDiyWZeFKSVPTjmWX0LEETPLkCw2mTNqTvlYlahNHAi2jWTzyrPHi2RT jNvJIl49itlCx6L2Hi/sN/1xfK+y7XU/QfP4t56UO18MrVk2JGW3eea2DNyl9/Jcgxp7njV1y4t I6xTn2uvs/ppqL20OkhDGqwcqHcCIbv2woJmNUsVYoasbw25pkpYJol69UVQG7mbypqjlirqml+ +ihmMKHzldv9XW6JLs8ApHkhA+eFG4qeHcLFb8njE12Kn8iFtIiQxC4sOze5Fs4e/qBO1/DjyEp +tHaSJA== X-Google-Smtp-Source: AGHT+IE1BPh9K0tsvS2irh9slIs2O8I2IOLea/2GWBdBPLJ7P+lih7SyOyAlCDTffkcTPSwFJR6kEQ== X-Received: by 2002:a05:6000:4025:b0:3a4:eed9:755b with SMTP id ffacd0b85a97d-3a53315704amr4816797f8f.4.1749564371436; Tue, 10 Jun 2025 07:06:11 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:10 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:39 +0200 Subject: [PATCH v6 01/17] dt-bindings: display/msm: dsi-phy-7nm: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-1-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=6p3gmVNgeWpM5P5NgnZSHUvO6bicpNKcBnOP1+C75sg=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDu/qPyxSZr5uQgETQ9z+HGRjh6JyUCMstBR5 md4b/PmrcmJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7vwAKCRDBN2bmhouD 1w0PD/9GgT8PUxfu86n+kcyB03P7Gw4/ycsNaJmnr0wzsebLzXby5oB6UEvkB4/MCKHhdpfDL/a rCvIquz/8M7jMhEgVw2yLc0MWBwcsPSOi5z6iTGHLz43eN5J5517ETTrsG45jucq4LgZ928YkKR /VNFmPklDDRNd0KZhw471vuGhtJg9/O7GJunrg8CAyJ3igcEL8Xa1E8mG2y9RG2RRffqzyjgeCO fp8uDttlMY1wsSc5dmzQl1JyAyBKfVVkKnZOiRXyurhb7i4zK/skjmu8LxsX1nuYO81VWbU0b0l fA3C0eob3/kyHYnNqbhWIDjElj0TF7hCB4FR9bfD3FDCeFDCb2U4GcBGVULVfTV37uIV8kNLIhk 5idnNT7l5NP8UICj6wMB2HSt/wrAMWjfLKYabTLOy3C0Fw6vsKzw6dBg11Qj5+ieoQfWodyUWgQ C6AV97Yil29ylhmXcRpw32CoSVhidWRKQ7uGB9Eg3ATYfAQq5ZXgxYqCE68NfIbeMd6rM1HK/LE DwUHSLE8r9CMzY/PwbNSo/AQp8gSoWo+bnDne2/YBayYMzpOTQ1t/uBMnVyY6Cy3ssEGcolks0Z y+tYb1Wb7L/25zKlBFGwYvb8QAP1/E3ahn3jtAl93W3Da8yDfwC7zmqAfJ+ImEz198M1TOMqs1Q COEegQZ5A86rK4A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 3c75ff42999a59183d5c6f9ad164023d6361ac07..1ca820a500b725233e161f53cbb= bd59406326876 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -25,6 +25,7 @@ properties: - qcom,sm8450-dsi-phy-5nm - qcom,sm8550-dsi-phy-4nm - qcom,sm8650-dsi-phy-4nm + - qcom,sm8750-dsi-phy-3nm =20 reg: items: --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6003B2BD02A for ; Tue, 10 Jun 2025 14:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564377; cv=none; b=VBDoS6YN8bEAgtG1q+DKJ/zVR/Y9a912e411px4WdDiBrAPZmOg6leVLNoSEpVGe43dCnamVKAA5rxaJpS0f2DpUKxILdJZnddG7v4m+Z45I7iec5Cbn4UdmyEiaK/f/bP6AqC3C56z6YlGpihbszBv0b+j/HCipklNUz3lP5QU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564377; c=relaxed/simple; bh=yhNmcVev6YviCoPWMe9VUWm+x64YmaIBhLXpEPpZ7Gk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g2+30NklACp4uGbDcuBvd6sQKoIbK+wFhtlpeE+FSzC1s4AQmA9FBLBqbcsPgd+cDtvgu803uW1KE8oWo55zA89SPhBlsBZXkkMUm0oIbTg3N3gQUUIhrUv1a7J6t+xP7EqfjSFOs3WrdYJxFyDIgQZWrfOfC3J0hgjOGjQ+v6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZzPMsubV; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZzPMsubV" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-3a4ebbfb18fso482441f8f.3 for ; Tue, 10 Jun 2025 07:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564374; x=1750169174; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QjftRN79TvWO6QuKUy67aBlRYEHheVO5KyEXzVb5XhU=; b=ZzPMsubVZdY4cV6Ulz04GukjnEDnr4UeTyPf7LWUnk0AIJ7zLNc3N2VmXlmCuspcm0 Q4pOVI0TuvkwFM4Et07rIxjrj6w+mupTlShaQv9ytkaV7ILvvJyMaKiHBXr81/JOkHM1 OVbzP67Q3qlXB5uX3IjDCQ6HCEr/KJu7cLOOBuQ4RdMa2Szgvq+0xfmniaikAJc1qzFu LPWFZbSG2o0zc0Jot6rJl4jowkYof7ZQGmGEAb6fnLIFDnnqNl2vf9Ps31XbMQloeQre VEl01W3IjWebotqbMMeTBbXkcWjken86Xhid17kH/C/mTaR5YkN+nsudH5OLqfsgOm+j o9Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564374; x=1750169174; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QjftRN79TvWO6QuKUy67aBlRYEHheVO5KyEXzVb5XhU=; b=GlwbjawefsjL66cBMBg9z+QdhsvBfkjQ2ZBGdd9pJ8A9LE1NIFp06zYL+eoRw4dbZf cMSjzg2pLI6tI6bGWWrWRaXsYazP06WT2PgQd8p3WOZG7sgpz/fdi95KNnjX+CZtxgDt iWfpy9rf1vUDjNUACdtuGiLjFVD2LlK+E4eFiTIIp22ZF6PN0kfkmlnyDRi6+akCa1sC Q5t5N/nCdqh9N17xaacgCSuoMR6sFi4RjghAyxuGbA+hjgixBZcLzEfdWapKRduVEVrc loVlLuhh75w6tYXNMKPTXLSEHtig5kL6jG4F5zOOE7pw2+7bLRKrN2WQg/KNxT7VZzaF qgOg== X-Forwarded-Encrypted: i=1; AJvYcCWOmTQISjFtoIpIiPPYcEyvNLQi/FvvO0tBUCzJ9G8SC+V3GdGJcvpWMG2TVBgumdnLC2sVFTrvMXmhUZE=@vger.kernel.org X-Gm-Message-State: AOJu0YwI1KlQqWrPRAH88cmBy3KWTGI++WlGz6jbjE5sdVT3oTW2lk+c GVy8Z8KvCmalifYYOglKGpEaiWe4QsYp7YsRaq6RxiERegllvq8WfKGpwa8Xt/79rkE= X-Gm-Gg: ASbGncv6bOiYl/JHmEi55u2zb+pRWy1osqtgGDFMTtFJZZC5dgT63lPGo0ddyW7ynEQ 4phUx+47P3yRcIxjBdQIPsl66nVwcGFh3I0/ftaNN4bgP5VKgtuAdCljCGp8RqFwl9+1RCvHBTX K8iiHGcvRAWIAlmGRd9hvRtiOkM3PGEKgZQvk18r08SIDaxcx2uEpqKyI10qqlIGMDUZ+ApZwtR SlXF8ru4dVwoOXjhqI+lQFg5BSBbEjVkc3fvkyDul/n6y9QeG0b3K2GFRE6HmZXJ08WVbBosfQm fc9w0Q/HOa8n7jI+cYPXJqE052LkoC2sR6xR3ESzBJwDjCRiWkonf0dpYZ7/QYyacxUZ6LRGb2s 9gMxUZA== X-Google-Smtp-Source: AGHT+IE8m9vNXCXJib4lvAobDyKN92NL9hduxtJo+sH3CDc8emVv2Z83tmvOkDG0E5rFAG5xNiixzw== X-Received: by 2002:a05:6000:1a8a:b0:3a4:f8a9:ba02 with SMTP id ffacd0b85a97d-3a533143257mr4846738f8f.1.1749564373627; Tue, 10 Jun 2025 07:06:13 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:13 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:40 +0200 Subject: [PATCH v6 02/17] dt-bindings: display/msm: dsi-controller-main: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-2-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4373; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=yhNmcVev6YviCoPWMe9VUWm+x64YmaIBhLXpEPpZ7Gk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvAnTGYNiceDs1Si8NBAvdNZ2GTuc/x9HM/Y lE2QCBPEAGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7wAAKCRDBN2bmhouD 147UD/9+eGofQl+6iI1dCqHNQL6e/FHxAyir4raIkr/ZKhgiqQ+7u3O0H2x7OT93P87jrkpqB2R UaVvdIKwpUWxgpfm6d2F11C3UglzRoRSdCyXnhww9DNf7eT6K3cbo+z0dn6IzNP4qbZZSI2t8Gu MWoDfbuZReYnQtIeCEQcgFleQgDseodzVg0GCDfhmZy/U2eodJl+4QlcZjEnGSRnOFa2Oo1CDZt TO8HPNl3xapxWyLr0bvm8vk6dD958R/zp7vAHHJbOnK1hwjCvDSPc2W14nfSN4NX7diFmtH8nTv /zVTfR0d5qk658B7xhVxbblBBsWGoVx/SvuCXtefAbF+Vig+hWWoXumGDVqU7K1CC4IR0klqH3s 6Il4oDQNwi7MxtYR7fwVSUbinD5hpyYKFxOKemFT80hsqYL3Puvp6a7ob3t105q/O0QcLTaxEQl vcPUS6rGrs9vTg9Ba6LTXntsyGrJ5FHP8/5304ffFk8VUctdk601pzvj/ui9veGw8Hzd7awYem7 7XTBcecsFtA4mOFJ0LcctlOeg+/wfLGWvY29oKYd9QrvWF4083FSeddw14msEaQPPCZlMENPSQx JaN1Nc0lvlYfnvucJuYFyBLsqra6/i3BfwVlQZ5EDASlk7QOiw+xi1PkH1QGZHK5HS3Oo05qtkI E9+5mL32MqGToSQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI controller for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. It does not allow the display clock controller clocks like "byte" and "pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not configured (not prepared, rate not set). Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure. These clocks are now inputs to the DSI controller device. Except that SM8750 DSI comes with several differences, new blocks and changes in registers, making it incompatible with SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/dsi-controller-main.yaml | 54 ++++++++++++++++++= ++-- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 82fe95a6d9599b5799549356451278564dc070de..d4bb65c660af8ce8a6bda129a82= 75c579a705871 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -42,6 +42,7 @@ properties: - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,sm8650-dsi-ctrl + - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl - enum: - qcom,dsi-ctrl-6g-qcm2290 @@ -70,11 +71,11 @@ properties: - mnoc:: MNOC clock - pixel:: Display pixel clock. minItems: 3 - maxItems: 9 + maxItems: 12 =20 clock-names: minItems: 3 - maxItems: 9 + maxItems: 12 =20 phys: maxItems: 1 @@ -109,7 +110,8 @@ properties: minItems: 2 maxItems: 4 description: | - Parents of "byte" and "pixel" for the given platform. + For DSI on SM8650 and older: parents of "byte" and "pixel" for the g= iven + platform. For DSIv2 platforms this should contain "byte", "esc", "src" and "pixel_src" clocks. =20 @@ -218,8 +220,6 @@ required: - clocks - clock-names - phys - - assigned-clocks - - assigned-clock-parents - ports =20 allOf: @@ -244,6 +244,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -266,6 +269,9 @@ allOf: - const: byte - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -288,6 +294,9 @@ allOf: - const: pixel - const: core - const: core_mmss + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -309,6 +318,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 - if: properties: @@ -346,6 +358,35 @@ allOf: - const: core - const: iface - const: bus + required: + - assigned-clocks + - assigned-clock-parents + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-dsi-ctrl + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + - const: dsi_pll_pixel + - const: dsi_pll_byte + - const: esync + - const: osc + - const: byte_src + - const: pixel_src =20 - if: properties: @@ -369,6 +410,9 @@ allOf: - const: core_mmss - const: pixel - const: core + required: + - assigned-clocks + - assigned-clock-parents =20 unevaluatedProperties: false =20 --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6B8B2BCF51 for ; Tue, 10 Jun 2025 14:06:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564379; cv=none; b=EZzPnCDHpbfAjE0FazUdgtFK26OdBgvo2HnklrvC/MbXKHheY9Rt9OYf3zpmCzATWS0ZGdzAymCG3easNUjA5Kgq2+gr5Y02si9mZIGJ+Osg3BwmPguLcnSGboTLVcoVv3rX9V5Lp0pcjOESmUJiXMmZhl43D/iLWVAtMIIaHeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564379; c=relaxed/simple; bh=zXT5KqsXrSGK/lPM3MXSFlSxuq5G3CuX3u2b43D0aEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S+htmuHT3jkhCwpw7hFpWCTmOK5cNfmLFWhQ77Z4fanrdElwGuUiv3XBaZ0yusJrnDfo67qA+8dRLEwXRhV5x8ZkFA6mRC0QcZQgQ+I6HaSMtqFiZcYyHN9ty/ifGlQjqjw6ZualbVlXhmKJd/+k2AjKfOgvw6+H0b5mKhk0zWs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=bs9CdH2q; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bs9CdH2q" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-450d0526132so2555745e9.0 for ; Tue, 10 Jun 2025 07:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564376; x=1750169176; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FzIry+niRGay8PThnz32i8jV1sSA67calFaeSw/btE8=; b=bs9CdH2qJRYH/lyQAikmhYv/aBGJ8yl360ZW5njZ8vQoR6xrdkaN9UUd0CmlQSgxiQ 2NZV1wt6/l+Be28vkkx59Wo2VgD0FUX0RYVbwas2Ti2/A+hUwNlLProeQbQibCjOfIN2 ntxeDpjCcTS7ayCC2mTU8WIGHfcYLPCxi2Ce8bevwPMNGXjdd3ddVdifL+SzW4LLpbFF PofGLStPJlZhULaQWfwE4m9WEFGeTyzud3BRwjTxxDoboXLGK6o/9SWCFtKeNnD+sPGo XAc6wPuqUMU7zcXqXiCyktibc/E2h3PhWldInF1MypI2DgMWELE0YTjLG6tvFdLd7jdx WqPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564376; x=1750169176; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FzIry+niRGay8PThnz32i8jV1sSA67calFaeSw/btE8=; b=Y73LWL/4G+7++D592YVxBPbT3xAWiBYi/8oyV0CBKcofS+8ECc4zHSgwMb7eqvDJI9 Ln3CAumawyRxe9vVpFwaTBcbGi4w/dnLLYAv0J7pORfNUFHHKR9fUt/j1jShvB1qcxyh AclZCLJgr3vc4ewZgGXV7VHo7tvwfQJMt2BZ9QJVzxul/z8pgYREKItihfibAxpa5xR1 gVgPkxPK7B9x97kUpnEfoVIOpljUSS1PZyfYMlGPxBHUtSWhFXfuLUzxDHzQjUw+4VP1 NWyBh9KeudNuEIUOMz9ozU6tohveeGaHPneJCHisLFwBnIqb2UWvVVfTBCelgvMh9k+Y zejA== X-Forwarded-Encrypted: i=1; AJvYcCXwgcKMH4Hs2+V4m04DhIDe9YJX8hnkFD7Xe+Zs/2RETKc7d5XWgIJpbGncmLK/sQW5BbbOTCmNTxafeAg=@vger.kernel.org X-Gm-Message-State: AOJu0YxB9wipdtJd7Zu1+rQxyPRUqOR1S33r/3IQmAiJQ9gE6MBhuIuc BxXedF/1ZsWwz5mlrvdY/JtikoTHu6CXXDzXKaztMJTSIX92syHKwWB2O3npRkj7Ns4= X-Gm-Gg: ASbGncsor8dRDHmvK8Et+Kov3xPojEGfOtdFUwVRfke3FheZXmmmo12wHmCeCnbG3qb pnzlYiU12gMpM+RGxGz9BNzSAzSow7NFg2t46NfKZmzPS9cWCgbiJ2G4aLj/iKCX4cH4jhPrbxb pJrXh1nwfOlEm6ZfyHuXDMXOVuYzFMr0QV3mogSIKkGUh5gfTnCOvp6KNzg3NXYrlgRMbyR6lY5 linyAPFQz0kORJrsZf6E9bzJGDlSVsiCHSBzmgU2hVGHKgtEbgkzwvEwnrA0/vGXHtfY8erMunD SDIQeCHW4PUXwYHkJllocKNIC2pJDtEi4RQHRCgjtcDgDNTFYdCKIFn6KAAjLUSIP/pXW5Ecwr1 EeTSdFw== X-Google-Smtp-Source: AGHT+IFm9QPIPtKj88kCIYqZXKQx3x9C5G98AeBxEuV4QWyOUJnApYLXqRwTArllLYrUbNaqeStteA== X-Received: by 2002:a05:600c:c83:b0:439:a30f:2e49 with SMTP id 5b1f17b1804b1-452014b3cdamr58900325e9.5.1749564375620; Tue, 10 Jun 2025 07:06:15 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:15 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:41 +0200 Subject: [PATCH v6 03/17] dt-bindings: display/msm: dp-controller: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-3-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1260; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=zXT5KqsXrSGK/lPM3MXSFlSxuq5G3CuX3u2b43D0aEw=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvBcBnYyTfiL8zs/evhNuS7T+Hr5JIuH05SG aYTeABkv3aJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7wQAKCRDBN2bmhouD 1z8YD/9Hu6oG7XIW0TSKmpY6kmKcXGI1YkCyklXDyNvXdkTDAgAHII8m4k/zWtNiKHPbPrPJu+x usF+MqYI8h1uJ86crkJCdDy1zM18kr23DKFG5+3yqZfWvSKjl47IEGTXI5/GgXc+kG2a6FdaY37 aMRmAESSmgTUn2ZEKRbB45pSSKIi2qaeegOP/xNPIIp4ewm/YmRNGvj+x69xfRkFE0BDpFjfurm jdsvopb8XV55PqRtyGqWXf35CdZEB3a91avjTgY9UERXzpqMAGdmokzeKoCqIrDgtb5RobQ5T4H Nq7rc4co+/qkkYuoSSqedmGU3ed042KVcp8OHlnR7CEP97Sx3FS3SLljZ5OLlcbGIG/+j6m+Lpn EBimXHouJrsOev6ogYy8x62VhpUSVCoqan2YSM4pVcJC60AJJEpKZALYUIpIJOrYeC22QYdd1/Z V09reHRMtJ62QbYRIM0zDySRN00Ft+b2ouxVTP7M9FSyHsZXorl2lSeM8KR8q86IggLVu4yfwrV O5V5IK6/JMwY8yVMzAItlxEAjZ1QH/LEc4F/I2zAc56kin0i5Fzr+pYZRUPa+SrS2T7wE8hMj5A VnMP9+5n8V36v54XZg80EriuA8Yjvfa2sPLQofwxtlLLxKVbv7SQfj7gJsLOIpM9Y4R7L3gB38G 9NhjA0CTiCHMoWw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks fully compatible with earlier SM8650 variant - both are of version v1.5.1 of the IP block. Datasheet also mentions that both support 4x MST for DPTX0 and 2x MST for DPTX1. Acked-by: Rob Herring (Arm) Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Extend commit msg --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 246bbb509bea18bed32e3a442d0926a24498c960..9923b065323bbab99de5079b674= a0317f3074373 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -38,6 +38,10 @@ properties: - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: + - enum: + - qcom,sm8750-dp + - const: qcom,sm8650-dp =20 reg: minItems: 4 --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 614ED2BEC31 for ; Tue, 10 Jun 2025 14:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564381; cv=none; b=izBLL8dtHc+2iMh3k6N/wipbTAcwGKj7i+6S6ERQAVMx5NZc8CQR9gC8oNUG7aTCOQYvP+mwC1h3YQKEg1tYHaHqtHiFbAJ60ixzsV9ZYhJGt+KJr/pU92gtucd1BArIuH0/7ViCh1ZmwBQnPisyHTkvxkWizzXRNXV4d9vqjlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564381; c=relaxed/simple; bh=XU5572AbRAlL2dnAZKnz9YY70ssdWL7hBDylOur/otU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FbomNIEbfxrImC4o5CwEOp7F/rRyPQXV3fMot60czmx00Qb49dGk/eQIS8dchE1fJ+hchvzAQAuegSDWg4ZELt+L2Kzd/jh/sUT0X/FGlT4isLd4bw69XIzludKFKUi5Va03fOHjABG2pCXxN1vruMfmPALMJLEYd/0MCsKKuFw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Hj/szyH0; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Hj/szyH0" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-3a4eed70f24so443595f8f.0 for ; Tue, 10 Jun 2025 07:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564378; x=1750169178; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LYwgiUzq75NuT9nEk3WuZ2BIh7wkvlMFp5zrsAIKP/U=; b=Hj/szyH08Mko4l2Y1CXmH+64L1Yv7JvPx1OrOzV3GWsZM64jS+I08uyiQleZdYLmCE QAbzt1+vsBrrAbr9arVSQppl4FQ+wwNSz4meNEn8iUJ/aYr8eGIzFkeo0/U/454j/RMW MxgHqraVrxwLQeEQWvZCh17NWI7d2atjnvEngEBgKKbaGpW3l+4dtGY0iCv5K8uGdZNk DvrPIu2xN747nw1EHJiJYmEvMPwnemgaFDkAILczrpBz5YT8kaC4DQ0+mRXW4sbW/aMw dsSf9vhTgRMrmSsnmMWV1LEVua/AJRTWBTbIBkXlKjc853FFwkx4ua6hWItNYyls8fDu dQ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564378; x=1750169178; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LYwgiUzq75NuT9nEk3WuZ2BIh7wkvlMFp5zrsAIKP/U=; b=j+KKhgx4zfczWQpwPu07b85hFYk4V1X+C2X/Werb1AbB7lNIaAzl22pivf5ZwVG4Ri SPF4/F19MKZsu4kobcBfy2BklJI9ywKVHeBbYB6ufUv2Si6+WjIZfx9UVy1yLrT5Zq/7 /zfwF7r/eEhqr/TK1Q4EFDAmWH6lko5dlO6M7ZOK4gRN0bUBoWRv/q6fyIbmlmLOSXxl rlznV9IpYkHMugp9ytO+zRA5YBZlRkjeewy094SGT7ykA20nHqeLqALw2SBzfgKnZLu4 nr6gSTeFOpZMKosf88L83k2VIQkEwn749eNkTxP1RbBDTHbYRZ8sTj3E6LU4Gr0K8IlI S/Sg== X-Forwarded-Encrypted: i=1; AJvYcCVpn7ewy3VA9JKp0F0s4Qn0yVpDyNnoaZogwcjU2Mqaqb3KclgQYUQgzx5R3A6/TPsbVDo4epM+gyXly00=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+J2vEvfELi9aT1Zxpy4cWZAWJDDJ8n+4twJGm12cDORmhN3GQ fxGsNv5GmAkrAt1krtMox3AWpa5fxvcVRmh31E1UPUpTHbTe6+7IgOuigc8neNsrWgs= X-Gm-Gg: ASbGncumMVwQfyiSH2mB+jXQLrFD6QtvyXeSWbGZWZlL8chgdiec07evVsnWXuNdQGO KaEcaC7ZxuCWtu+GUag58f7w87/669BO7mfuCvQ3FLLbBAq2fk0Wloqv4GgqjwO78hqA2th/fsm HxrkMRFVSpqMPm+gdfnjQlKNPv4O2Gi4rfREc3lrWyDgC3hcEqf+3/wWSAlRGhMxoBXIysUxL46 EEccsgPxwoWLDtzeNI0Hp3N0uDIe89zLgkdIcfXjLNvC6sgDzgVtDskuItrSaJa7tnK4lLc+BA1 H4HBBP9ilh5Ntznu+NE9M+YXYIzTo7N6nhR6i/CcxT09h9X7iURGUXbkt6Jo8nS2UNHm3CklODk RF9tZ/w== X-Google-Smtp-Source: AGHT+IH25gKgo8d1gYAXhu9lWH0BmA+6Au/NMRgukcCSeLR32XCsUqrr/CCJpz5l/lsXeticymgVQw== X-Received: by 2002:a05:6000:144a:b0:3a3:6e85:a550 with SMTP id ffacd0b85a97d-3a533143e5dmr4792126f8f.5.1749564377666; Tue, 10 Jun 2025 07:06:17 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:17 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:42 +0200 Subject: [PATCH v6 04/17] dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-4-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=943; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=XU5572AbRAlL2dnAZKnz9YY70ssdWL7hBDylOur/otU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvC2lB3lIxtbsNFzyWORfZgsGtzg3s+vk35z /dPmTfPLbuJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7wgAKCRDBN2bmhouD 134XD/0d1lSSjv1+CB5AgL0VUzorFocmxjRuPcFE2sJHZWxqDzRNRynQD6x9VAr0Shl9tFORtxC 8DkQQ2uR4ZjnjhvnhSAa/ki40J03d/MdQWr6HeJwlAaCVKGO3B6dqzJRtaIMHwO2JtVVfqbN1BM wXb1lZhR/6McXk51ULNzCqwhSU9tl6gERabgsEPNT7LI9SkhRQ+/a+MutB3gNFY3GuS3qFccz2Z DvPmibAcl1AO4QRoEsNdKLW23BFqfHhpRsGiRnNC0JHbrp4tOZo7MmAkxXyNilN+kDNRwjyHurD K216/cd9UAvqhzDo6FK/0rq1EjL3IvPNsVhCrrLSX7QbS2IC8gqTdkVlnfFY0KL6giNbJ3/qL1V VY0UMPgEDQ+uVNdz+cUtP2YYJbmL3DeaXKvxXB3Pjwd8krdc6dTmyfoOEcErTIwSBaCPwqeI/Ob Y69EuoyarJ1KY8eRVyRpIcgceGRW63D/Dg8eEtyrWgEH3K2hgQYPaP4Arcr7PniTIiFvEc/A9jE 9Jj0bugI1whaH/BsqGp6Kia8VdabiQ/Is2hkHxmzpsAczNAvrXE+Bu07GQ1A/SWUTUDrwaEWp6W 8NaUYft0uDbjzb6ISM8zwKArfCc82KutxoiV8Xf2Vgvq9L0bVcxR9w68Hc8YbkO80ZIwwnThDPN 6iDFXdGLfdUJKkA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU for Qualcomm SM8750 SoC which has several differences, new blocks and changes in registers, making it incompatible with SM8650. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index 01cf79bd754b491349c52c5aef49ba06e835d0bf..0a46120dd8680371ed031f77738= 59716f49c3aa1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: enum: - qcom,sa8775p-dpu - qcom,sm8650-dpu + - qcom,sm8750-dpu - qcom,x1e80100-dpu =20 reg: --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D612B2BEC3B for ; Tue, 10 Jun 2025 14:06:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564384; cv=none; b=nyzHToD87zi1clQ9S51Qqup4yOjbFgAMZ+AUrUBrFdYs0aCELDIiaRTNjrUNjZ9ybO71TCM98kDli11x7z228xcjcf9v4/hn7z3pzH8AuVmM2RMG+PgOJXzK+2pKnzeMfZHwisWPwIyF95gmdf+Z5kcBy9FCmJ8PAa3rx0I+n6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564384; c=relaxed/simple; bh=GkWQl4AHuV9DjDU+IEnl4HWYAg7OOc0kIv/ZNv4aHT0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QuJ9mnyscesZkov9GW2/lUkwwwl9OUERiEOPigU3ShxyNjiNdsTnUrGuX/b89IIPcCrtz/yaQLsDrjWLQN21rHCWVwdeDLzWr+dkGpx6z/ZmNbNLxbAlGTNoIq4oJ34YIH7BoXF44szXnifTKXxk7+AbS1P/IaiVJXZY7vwjHKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZlQh/pQb; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZlQh/pQb" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4531898b208so1002755e9.3 for ; Tue, 10 Jun 2025 07:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564380; x=1750169180; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wAIPDns1zRlLkDTDA2ufc+iwOegg3wkdBuYVEqu/EmA=; b=ZlQh/pQbLY1crj1erQh/lf+GMQwqD/UpF4FkG9znKw1o430BucQUwRV0fTgsTs/uy+ YoNgpZrKJ6qQHRdFYM+52RzB/RcdAyUpG5x/U2spNK2OAPFz5febtpvx1YmSA/57jV30 sM7GNq8EVmjh0ycV1R3110Bc0Wvkg0Bzoij5hxCYunge0ZzXP00kY6faFyTqvVsyKNdt g3T0EaO6ZW6Om1+ZaJydTTzWQKGsgWYT/bqqOowqfFJbm5Fzvie9R4WhLAb+ArzMUVEt yB3Ds7KtU65NUIxPwmEAuSOioF/0qYDS0rGCriIqm+v+x4NIsgKF57tPOy5JzkA+XNOy zkQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564380; x=1750169180; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wAIPDns1zRlLkDTDA2ufc+iwOegg3wkdBuYVEqu/EmA=; b=BHrBrl0w3miXLaKYqZRmRDTU0h2GmAOW3HB/NGU+o29SIAzOVZP6hsjP78JEgQV+8o /hYxWep/8el6jj10cQLPwE91ckEPck9lzKJIYJ2IGVdDEJAOcKzLIMLCx1nv/XDr3amm VtAyHhfvrvAjsmU8bdNNNrRLOWLclc1fnuDqNefXXLyS+IyrApKPhrlmC4NhQcwD+zt/ E1/HTcsb2R3FamONLDpYBZ/4GOMwTugSfTU248Zu1bqP89Ks+gbRqYtbfM7JVhT/YuPi Q6LC+Aifhw4qWDzdS3SZmEGUnDqCgPDT95A61fQwlvLTRs301x0IVA6vq4OoY6JXJ2Lf uk+A== X-Forwarded-Encrypted: i=1; AJvYcCWvLVcwBKJmpmSfVrh12cjSntvq1FMJ+Uqy/VF9gLUR7j/TUYMJm4htKhvmEvX3Z5vidQIhi45pzatS8JE=@vger.kernel.org X-Gm-Message-State: AOJu0Ywpil32Z/FGl3v+BqqcvVAHmCNMbqUsI3iUfoT80NmoQfwj+AFR xpSoqLaQOiFsVak1o0+f51dAX6mpXPcyNo/9Q3OcjdsMqQdUF7rviYmGkFvkN/uT6Qw= X-Gm-Gg: ASbGncsLtaQtYXPUPHK3Uj3e0Cw8p6KDtYNHyM0FEVWmqXBOlksQ0S/KqEfueihkl16 t4GJ0xpadfw0YxyAoiIYE7q4EvLUAQ7TxD2hK9eBOEmVr68Hma8HbK35VNeH0dvcrcXxZQ3Hx8n jlVSQcguqyuPTMlyoQ9E/qOOCFGDBzpy7Ynk2pGvE2bWzYC+WfWtROSrrL+wOZeKxvsYb3g6LR1 uIFp4DTrgrII4ZDqUp88M9TSLhxut2MKpqjqYVykJwbgO9pTnKri2V3Eqb4fUuuN2jS+D/WOATC /f3450tjcjYy8UHY0dk33R2cxPeCuplGRV+E9SHXj1WsTsAkNti7RFUfT6ifqo/EWq9pGpm8OWd WyNK86A== X-Google-Smtp-Source: AGHT+IEbn++/TrlQ8CnGdJhD4PqH/f8v9pJKkPsUGPoPg26ZqqnyDuiERRk0NcOF/FZqryYt/0nGZQ== X-Received: by 2002:a05:600c:45cc:b0:442:fac9:5e2f with SMTP id 5b1f17b1804b1-452948376a5mr57515675e9.2.1749564379711; Tue, 10 Jun 2025 07:06:19 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:19 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:43 +0200 Subject: [PATCH v6 05/17] dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-5-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16871; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=GkWQl4AHuV9DjDU+IEnl4HWYAg7OOc0kIv/ZNv4aHT0=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvD+Rk7RKM6CRwn07acUzUy/Qw/j8iRA5Rl2 L7rNIsL5ZiJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7wwAKCRDBN2bmhouD 1zC4D/4or9v+mISULfwXs1LzeqUR5hrBRkRa521RoqYo4Fl/I/Au3zOFb8phXx3PWTEv2csOqFT QLzHGvk24pAgh0yXI6RDcAOYDZXIUtIIvC/rEOlJsFhatn7ilXFvHPFpYCoiW0xICEhgaYVNhl/ HqKo+3bqNDgSJn5W2J+PIYMHQ2z82CoeC4bMOxvvlrisncJz1SIVnW/IOs4OpAiJOnLKMWqxY3F k+GjqPGYJzyxwSHWHmPcotf9jfRsyG0zgVjXL40W4NZ8bFBjZ527+rQ9xfLa7/sU3Cj1VowFu/K BuBklqKhBiLGUXRvERqCDPoMOZtbNOW9TtaoI2X6cup+HrgT4cB/Gmed7BXv+X9p9EhtfEfhCPc kqCoZjWnBShM2tQ3AiYXZ+j+pzGl2YldSmqYA/gUivKwmYIa7moN6NeJlsJYQc6HV3kBZu9bxKd EYixlcgLNSEBOhpUJ4nHDERQygpJMuXWApEtb/8dFtL2iMuggAJ8xCA2xp19QySOnXQt8U9UkI/ rCxh/3mDGAUAQjmbJRjYIqxdlHo0MlkNOWDrUsoTtgRlH8AZp/TAH9Ne1ltLgEjBnJ8h9RVUxFw ThpktnxurA0wkFsj+hwLvH/jExM9ov7nkJ/4icEVua94N6Czh8EuEuU8Buh6k/rWpJE/hRoA12b YmqclQYC2MFnKkQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation with two revisions up of the IP block comparing to SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Properly described interconnects 2. Use only one compatible and contains for the sub-blocks (Rob) --- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 470 +++++++++++++++++= ++++ 1 file changed, 470 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..72c70edc1fb01c61f8aad24fdb5= 8bfb4f62a6e34 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -0,0 +1,470 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Display MDSS + +maintainers: + - Krzysztof Kozlowski + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8750-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8750-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_AC= TIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8750-dpu"; + reg =3D <0x0ae01000 0x93000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + vdda-supply =3D <&vreg_l3g_1p2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + vdds-supply =3D <&vreg_l3i_0p88>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + dsi@ae96000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 5>; + + clocks =3D <&disp_cc_mdss_byte1_clk>, + <&disp_cc_mdss_byte1_intf_clk>, + <&disp_cc_mdss_pclk1_clk>, + <&disp_cc_mdss_esc1_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&disp_cc_esync1_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte1_clk_src>, + <&disp_cc_mdss_pclk1_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + displayport-controller@af54000 { + compatible =3D "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg =3D <0xaf54000 0x104>, + <0xaf54200 0xc0>, + <0xaf55000 0x770>, + <0xaf56000 0x9c>, + <0xaf57000 0x9c>; + + interrupts-extended =3D <&mdss 12>; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_dptx0_aux_clk>, + <&disp_cc_mdss_dptx0_link_clk>, + <&disp_cc_mdss_dptx0_link_intf_clk>, + <&disp_cc_mdss_dptx0_pixel0_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&disp_cc_mdss_dptx0_link_clk_src>, + <&disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_= LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VC= O_DIV_CLK>; + + operating-points-v2 =3D <&dp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dp0_out: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + }; + }; --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E72822C033E for ; Tue, 10 Jun 2025 14:06:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564385; cv=none; b=iCF18EmsccNolouwkFWXVRfbxd66S3FXdEZGAi8bv83a6Z3C/8ESAJzBvhitaAxkgxE8LZnfdtUbVPwssrPLMaaj42kAyNTx6MGPrKBKVveHyxy4UyHaDqDXBZ0r+F39HQTUSF68f3/e/wrlDmFVdCulO5JR0b1hoTDgxXs8hxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564385; c=relaxed/simple; bh=hOZPlM1KyWeQGK+fAet9Nxs5Wt17jNDUM1Ff6e36WS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GwiTXSR3rikxBMP3l4jBpyR1y8TwzTX+F0IkqtuW3vLOzFZUjci+GzOi77HCIrRsMiowYZZH5maZvH61oxwUFtVDOWhmLIi3XS5OYVNcBU+Pfql9P99Ze4lNTFjTVFe8GHNckaUNkh6qPTfYSS29LEMdbD6bf+ZdjWbnOU7TnuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=M2KtoO9t; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="M2KtoO9t" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-45306976410so630725e9.3 for ; Tue, 10 Jun 2025 07:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564382; x=1750169182; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c08nNQiRjpMuZiP/f1jVDn68latr5bwhdLQgcHIbV2Q=; b=M2KtoO9t0tnmiOKPKbKIwiL/wOTAYzLD7/5ictVkbGj6PVVqXgD0bkb3QQPBbtGj5a fkzN/UWJJjE+C5/MDdrBkWSaRJw094HFiayM/Sy9M5Q5l3PQqnyjMx/AYBlqig3TVThG 2X+Am8JaOYtpxW/gG3TsgemAaVI/n/raMgQv7YdQoLKdT0S1NelesWZOBe9dcVt9LFSh Vg4m4qNnTfGpI6uZuJrA1W6pCmVcZj7/Gt++uvdXBtZrSnjpsbc0GgZvbFOxqmL/GWAB qbHnw1BaIsCoHHWkafHeVlPEZtQH8gSG+QVWgnD/isp9ZKxbmJExEca2xGsIemAT3n69 GcSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564382; x=1750169182; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c08nNQiRjpMuZiP/f1jVDn68latr5bwhdLQgcHIbV2Q=; b=n71gm1vJAenGkFdiiguNQBAnFQJvKfxksha6cS8Qp4wB3OORWn9ytEPTErPIdMRnDq T60wf4sSnEYsr93IA4qWuLoYnVndEWEewfX0X9nPRfbRMGjX4dEpy5qzX230jUmEuuqr wONVWLDlDSmPVjXeQdb1AwPD17AoQKdo1c1gN7InGs43DIjGWGAz7oWeWcg2hwSQCkiP GlY2T/nSH+0P07UDSzS8tOId0NTdQeKYolk7pvIxngzzQ4Zm/AxaaigvFABHtk01SVKr JmYZrsttegRtvJWcB47kOjjoYLnMahqvj6Iu3438BADnGEs2D9aP0Tq310cCnxFKO5+X eoJA== X-Forwarded-Encrypted: i=1; AJvYcCVHEc/Y5dEW6SeM5YcdzAIx4tSotVRsBQhgBYPOAC1VskGQSQ1EOcrFSBgkhNIKvaQWxITyXHAyG6KWel8=@vger.kernel.org X-Gm-Message-State: AOJu0YyY3UwYSyzNoUKADR+GNig9TZZavrXqAcg6MJXwxdSEj5LCCZ9E uOh8bpOyiEQfuUQw5Hyw7I4fk4BACrxsHFzv5kR8nR983omzb4jVvl9byvz2MwDfmLM= X-Gm-Gg: ASbGncu0lyw6W4VU98AtaDISWHfLn7zzzcJ0KUibi6ePB3UFuJf5t+piMmuYi1VK5i+ gMg9VwEo5tBNyk9ejPJMttI5Y3efe8fMOFAaUrZ/IN3DBib3tbT3qQZ8XDa7Tr+hIEu7h4/1PFs NWtfioy3tJ+DnF4049LQuOgDrH+xeUEmFOZVbSOLGBE0uL+cvnZVGU0q7Wd9Jr5ooQSmjGBkdWN nW2CURNWoBX76aRitN4fomcTrBxP1ff/ERe7si90jNZNVdFnLYxfqP5JFlhynvb4I9jAmtYJ0+2 nrCq8hKWe0Y/uJ1AtjGrlVfPRxdi2dgfjGBbcc0C4Pm3wdiMoWp49QSCicmM+RgbWtrNYrb5Yxu B97VEzg== X-Google-Smtp-Source: AGHT+IHDxukPheSrxBOvxKpZYaa8h9T+95Gg5jKYThUcUHQbgCqlc/EbIO/Sp6kjBnRf7HNWZ6eJEQ== X-Received: by 2002:a05:600c:c04b:20b0:441:c5ee:cdb4 with SMTP id 5b1f17b1804b1-452a470122cmr33063215e9.4.1749564381956; Tue, 10 Jun 2025 07:06:21 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:21 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:44 +0200 Subject: [PATCH v6 06/17] drm/msm/dsi/phy: Toggle back buffer resync after preparing PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-6-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1275; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=hOZPlM1KyWeQGK+fAet9Nxs5Wt17jNDUM1Ff6e36WS0=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvEFaGVfcvc7I+WsKnLa00SN5QPTkSzfiWGJ PahrGboSN2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7xAAKCRDBN2bmhouD 1/FCD/996DPQkeSTgHdKYXZwdFyt3uizbqcoRQhLkEEg860tSjn7Kte3DUkvlR7EWtxQc1vwNij h6zflWghpo2l50dYyFTsw/N7CR6NRHryv3B7+nv+2r33l7WcaoFYkGM4FsAkCJKMPl6bGpRNQvA 9jYFY0BIHeuFg8AXYSEvLhDdZ8R+Zdx37F7ax1PugZeMApDCjDLkq9ba2ok7D7AoApGrHVyuZce kRFTFCEytra1l3KwEc4Mn+XdmielljNWWsKSC6JX9ReyWvrwewEpGU7twwfCxB7LwVqmnbhzP/Y OpmQ2JKetVRFnfrvaNuaTttsyTjub1lLnKUP5t23B8qKg2BrTwdsdVbvD8j6L0ykRwn9BMAaOAu z9dNv2P7/vnLpPNE1JmD8TbtHsmK15kV34zypREhkFVycSF8QAeMOA1Mr2SY5MXginxjTNRkS3H DHBBUWus08o+ao5tXURP0ryJuFyaWOJ+omsvAmjClWK2RIWoZLvhOAoPHumWwrZ7c/FLW3Fm3XN 7CIJpoOxTfq/cRbfsadOyaALh7+jFh5l6qhA5aFXQionaHY2c+4Nxh680d/6/sTx/hEyXCmoXD6 wl5tCEHIljBGjnYYUs2fMNCaFMtpUQeNbctmXaAWguGng2Fehbc2OAm4mwDti2rpffedGvjZJix lW03btC9avV5Gvg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B According to Hardware Programming Guide for DSI PHY, the retime buffer resync should be done after PLL clock users (byte_clk and intf_byte_clk) are enabled. Downstream also does it as part of configuring the PLL. Driver was only turning off the resync FIFO buffer, but never bringing it on again. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v6: 1. Fix typo in commit msg Changes in v5: 1. New patch --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c19890358b7479c85c793aa7470904127c2d0206..f0ff6c9fbc2e6d28c96c08114c0= f417708d70b10 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -467,6 +467,10 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) if (pll_7nm->slave) dsi_pll_enable_global_clk(pll_7nm->slave); =20 + writel(0x1, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + if (pll_7nm->slave) + writel(0x1, pll_7nm->slave->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + error: return rc; } --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EDA92C3770 for ; Tue, 10 Jun 2025 14:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564389; cv=none; b=BiMg9Ag/wCwByfkHOAdCn+9x6ARtNIiYNtGBZjws9G8xaENb6MZ0yObixM+QwIg66SU2gb/F0htVPd6H79R/cy00s3Pv/1D4oozcw2E9bnP67mHtAhy92dW4ZTbiAWsNvxo75tYynKqXBWPrNfayX1YVXEh8pBGXDnXVDQpGKo4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564389; c=relaxed/simple; bh=RNboVNFWutHKxxSCJ7Ad+xBqpxMQb2M+r4Es9Fz+OXY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=utLyzYUqalQ/ydyCjgI1MXn42K6iBYGrp9lfxkGkRxTSpm0+vKiOy75AzmS4MZFj4UrQg1NfS2dj14s4Zz+hVvRvf+/171UWH8vabKi3UMab2vGoOx+U+0dfYG/dqrBe2ekCXWCwdVBqMr1yd02m4yBoEfHHsUiqMrF0Sy/f/Hk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=m0v/ZUKK; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m0v/ZUKK" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3a528e301b0so728755f8f.1 for ; Tue, 10 Jun 2025 07:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564385; x=1750169185; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rpOiO+FEaa+w4A+7D6YhlJmVtA2pagPAEL+dLTD4VlY=; b=m0v/ZUKKZqZe5TNcEGLKccHUc6SgEYjmvh9vLrNTZ06zZCsbPU33NlRXDOoTvrAvL6 Hykiq1i8wStE7c126I3M2GewwPMDaOi+gFv81yZl/OjoJ6m7SN5KBagglzahtSoYIFh0 Tm1RvgLuESlHQgW7uyExAGrGKxlJxSxv5P+iCtpkNP+PMivz2E1xVT/QEXKW7BHAUkBm cOEzPaXQVfIl0gtWCJQ9Y9xirmWuEJvB569QEc0dqIImoD1Hslg7P/dUc7DxgLphYpSZ SkEyYxIfYzPaWCu9t0tTYnIIehXiZqIipUMxb3o3cHB6u77G7ZeuGFhNhLN+pJs7N5Nq VYiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564385; x=1750169185; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rpOiO+FEaa+w4A+7D6YhlJmVtA2pagPAEL+dLTD4VlY=; b=IR4JrX80TW5Y6a1m84UJeAt0J2h8r2qc2ezDVnRgujffbjlybTty+pKLrFmwBGTQKi YvLuuzik0ZBqAFGdzMznDmql5CXJL+20lXNEDDtQltKPdMG9woPXTN6A5+GXP8CbeETE LffveTra4qxr7kJwu4id/ivWyFXMFCmyUrY+o/V/+90OYGvyN3usTewMhoBRweX+5eTb eiu+gi6c9gW3M5P+AvGvZOvsk1MY/yiTXEQ1W98SusTBPPSyhxWN028y2sBixnFpHVam lxzSlOfRnDQy2h7sNl9XLaltl4v38rFv6Cs24VMHXtvrQF/h7JSGFTwS8SjKmHUBCPqC U4Tg== X-Forwarded-Encrypted: i=1; AJvYcCUMo5Wkt/FkwTfVd4fEhNDP1t/SkEzplVoxp6FUMCA9dM0/UkAjtb5QiJ36ywKxxNRypALyLvAR7fHC7N0=@vger.kernel.org X-Gm-Message-State: AOJu0YwE1OK0dEbEyloQybLBVTfdCPzcb0COupHB4ru+jYYZlqxrbG5H qdpL7yWCTOezLaN4qlF3i657kcpOjexbcqOrB3TmWFY86CbFi7bfFZMs4/O6YLkeArE= X-Gm-Gg: ASbGnculyio5WdvQIl67kfCHhyoMCugURA6rYe2hwC8U3qhnYoikF2weIZdGsSEjDiI K7sSX/Z84ky8+XKgpFj0rdNyvOZLKYsCGBOND1WS59hpXGZiUfofNSgo0kXR6iE3LzB/XybpD+q W+dJpb56l1pwyVFTnhb3GvIs+y0WAa7cAJKWisgfcwFr/pFj2J3MuBP65I/Lt3JHNeMjhJJgaiK 7K6wWcxFKIZSJ841S6BiEuTBQsYCs8lfzBlUXTAVgqAFMiOG0cAgyKPVUpc71gqtMaQSvmRmlsl PWZmIsnICGBKGEm6f04Fvh3ArY7WJpTpKWIHDy0YFqomPaEzW4qHo2KW8/kNP5wUBQtu54BRboe 4PsoFqQ== X-Google-Smtp-Source: AGHT+IFMhckmXcGnjChqtVdaAAq6SLAgWxkzv2bzSAaK4VvB5QeKCr7BJgtMZofJPhIMMyh+0XvSKg== X-Received: by 2002:a05:6000:18ab:b0:3a5:324a:89b5 with SMTP id ffacd0b85a97d-3a53316bea1mr4327656f8f.8.1749564384148; Tue, 10 Jun 2025 07:06:24 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:23 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:45 +0200 Subject: [PATCH v6 07/17] drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-7-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3534; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=RNboVNFWutHKxxSCJ7Ad+xBqpxMQb2M+r4Es9Fz+OXY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvFX0W+WTwJ4w1LSGespVXTP1AzgrXMWkFy8 TE7C6mdXrKJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7xQAKCRDBN2bmhouD 17NnD/4mMwgXpWRaFzN80tziJN1bGIPXDrhr0vKKLTqKnew/1/UgO2cwOucF397xWD9s37gwisF xlibcQo3MGfJXYyZDuLn5/TXMiPelmJuGAZgP8VI6Yu77rAkURXwjixbNTCvC6A5DXGgsbRs6/l Juhn+UPvEDD0yc5VgrMjeQNHED1NPV1Z86yU0gB+P7jxLygbrhWO2apN2/r+ohNrz1p2Mo8YvD2 Q6oT6mkARDuT5hAwp8cT5NVODU17FcLU/rdU1Si5KqN4T5xRYHXypoaCft/SYy3IaLI3QsuM3Eo 0OC6/GVtEoTJhVjmSFlQMuQ7j2+MeR1zXOUnG2cyV2viAK1HtRj2jKhakvpxxTyCSDUfmx9GUpo oOqHseSgzZJrWwdH4igX6ttQZ/JUX9yD02MMV9noYd20mGPUxoH8+9sWeaGsx8bSzbtJ+88ZQ4X tKng722zYkuG6sZPw8gGjFQsl4DXG1YBovz3UNK5ZUS+6YrVdDZQrq9AOawb+bVsH499RAq3pbA zBv1vnYAjJzHUOLEFeIiC0xDZeHTXrfx33F4vL7naLp8yx6s6t+lJg6mpNQC5/howyMAeF/aBkP QBQJfHfNfBEL6eWtMNRhGXSS/OceJx9A575nEBEGq2zjxcLPKowStveSoCBjnFZBgjw2hLYhCLK LnKLQ+LNpwXLafg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add bitfields for PHY_CMN_CTRL_0 registers to avoid hard-coding bit masks and shifts and make the code a bit more readable. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v6: 1. Add new line between declarations and actual code (Dmitry) Changes in v5: 1. New patch --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 16 +++++++++++----- drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 11 ++++++++++- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index f0ff6c9fbc2e6d28c96c08114c0f417708d70b10..4df865dfe6fe111297f0d08199c= 515d3b5e5a0b6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -361,18 +361,23 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm= *pll) =20 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data; =20 + data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + data &=3D ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); - writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); ndelay(250); } =20 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + u32 data; + + data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + data |=3D DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); =20 - writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); ndelay(250); } @@ -996,7 +1001,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, } =20 /* de-assert digital and pll power down */ - data =3D BIT(6) | BIT(5); + data =3D DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B | + DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); =20 /* Assert PLL core reset */ diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/driver= s/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..d49122b88d14896ef3e87b783a1= 691f85b61aa9c 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -22,7 +22,16 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> - + + + + + + + + + + --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04CD22D0289 for ; Tue, 10 Jun 2025 14:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564390; cv=none; b=BN8Zbcxx5DEnNk5HbLzvaQvJuVWF0trajc1fAnFi0jz/qy4ODtl36yeJg9bBOyWgRMS2+fC8D8xxX3skRFvyAfgSjMt3HK9TpOi+vkxdoQaJN3f1rU0Sq8lOiqZSFIqxs+0p3Z48Ut6ARYJHn8QRmkejIxolwoxusLZ+kxm32fE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564390; c=relaxed/simple; bh=JEggE4aGkw0e9clcohgBckgczcMgMJlvG2hLK8vTaTQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dkBD1bqHXJ9pNOrMkTkZQUj9c2xqXsh0d5AxA+4ImFUw2yN8s+QLXeL/cZwnghY+jEGU/MpsHmYcr8N9nMzz88oEhTWkwUylTw+mJvY9bGKOUbKvBwUdCQACNrk6fCsp305uwAqQqk6ckmBkfJMOiWDbKawEEBhrDRfvd6tJaNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pGk7n5Cr; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pGk7n5Cr" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-45306976410so630795e9.3 for ; Tue, 10 Jun 2025 07:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564386; x=1750169186; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c1KnLM1NPxNXZz/8JZFIjv2R+0TiPb/2BYtiypsnLxI=; b=pGk7n5CrbX373Yx8bi8FiXY3eJ0NYgX7DDqeR0obLo2T326I5i6w8jzWS0dzAjPXp/ /7QG8iSJ+FLVORiRgIhIaxDF/1Gch9qdRKhSiVB2ayEI4eLfhSCp2TByA+OURn7JwXAA Ct0396iqcz73ZHQj9z7DBZMCtzMjl//0lneF9U9FYH+2nb5NTu917cSIvabV4+28mbqF rjZHQP6o/40V+Eh8hwU1KOxaI0/LTSq0bDEjLYo10AJeD3HH74X45htOBZbFSgObTEq+ eRQPcsAJ3eqlQqgN4Gw7encIDhCDDZDN8DegK08qx31rR1ukeZjr78Z3IRi9n5rEO+ee XQRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564386; x=1750169186; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c1KnLM1NPxNXZz/8JZFIjv2R+0TiPb/2BYtiypsnLxI=; b=Fku2AhUnR8VASFXaGXwN/T8vk/vzOWU4+ereGkzQgcu1YF8puklMxNh50+di4mTQkK obEDDRJjR/f1E3u0fiyzab5oSHGLDiV9ILsHGLoHzYa0Orte29pB6Tf18mWj0NQWVA3L zGNldufIdNxfZceMHxRvzbWC2sbh/xJw8oDXrKW7omKYnkcY3GakK6VdZn4hBjm2log6 ZepU2uCoIZyFRULqhzarCenifeWYrY+HDaImu8isX7szzEftEbXuwsSikREFVwkiKVMX j8nHwko6t8aKaZqdRMsWnTb/iReq7hw2pSItSuTh0ZFoQ8bQrZMLmkjaiWPgpsGX5UHg B8LA== X-Forwarded-Encrypted: i=1; AJvYcCUZur6cBMIFOVAvPfFQm9pkY7SyQZyELiR83kNxBm4Fy7ndGIOHtWMEza59g1AqVav8dUUaDEgv/oL3aAg=@vger.kernel.org X-Gm-Message-State: AOJu0Yz/W8mqZvxRxvO78OK4KCdjNSd+Xjqlct0ydOaQe1PYP7Lmkapt wmtDRSUaN+zfSr7Rd3u8Y1JlIiXmi1/35XAeX+3eZRmz4p9iSMBZBFi2CQqKcKHk7Cw= X-Gm-Gg: ASbGncv/Z4H5sZqBlzWGIMcq1ih/FtNDvl1WiD6nL2AJpgIpR8EUeARtg1QW3iNUSMX O8RojvM0nm3tkTJqqQAmmPEtFugBfkD2H75OObZsfv3QpygQTyw9eCBrdA37DRIjj++D6H+Rm/V Ufa9Qkp7NW7iiXpdRL4zkHrkAoRuLmjpEy0s/w1g9LRV1eLdkUpH8FimVBq2Zm4r98do4FEsZBx PlNVWHkBDrNouoolLhR2OUGDC1xphCOxIW7i+ITZpfVYw4ZCU1WYgEwmfcfCS4e2Z3vsae3Zm9D 5xaLkJmSc8U9zUaogKcT98zKLkxxxgWin5Ccg7+ZXfYOpA3fgXxZoZIXloUoHoF7bbLXVrqPbPT keHlbyg== X-Google-Smtp-Source: AGHT+IEwWcvYaimoww5hM1GBZ3AEqmQUQ5RJD+K72W8jKVRT3hyLsep9VyFM47tqr7v/rXlXGRe5sg== X-Received: by 2002:a05:600c:350f:b0:451:eed7:6d76 with SMTP id 5b1f17b1804b1-4530538bc36mr37681375e9.8.1749564386213; Tue, 10 Jun 2025 07:06:26 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:25 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:46 +0200 Subject: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-8-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8466; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=JEggE4aGkw0e9clcohgBckgczcMgMJlvG2hLK8vTaTQ=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvGiQKQC/7r4PPleERPmdWoG8uIMN39/Siti IjU1gMyb5CJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7xgAKCRDBN2bmhouD 110hD/4jJB2SuxaT5PB9fySSb4OSXk43iif0GUV+JRpbsLOlXL1dvUFFc+O/gYf2qppQ10L9Nnw ZHnw4E60dYCzRvwyFBDtRZkgBjyZnFgiL10/1R6rrSan27IPiJ6CHRIESiFLHUrv3M+dmMscQLB DM7wfVkopFxOMgFD9fH1Umw8NNYWAjCy2+U6TyLB6nxaTs6eUUGlEEjEGlE3kXpSIrjaJc86Ozw aAHdPqjdeUjDDy4Curi2ymKMnndcbVIxHTf6cK3MbAvCFOyg2rB5GnpRkbbKcvK9ammiZGomvkz 4aHttLnObh2jN0JE58h1Tt1CPzy3Z2kGZtdYW2qLUp7bdYsEvktu7ee7P3tG6PblW6TPb0CFXCb swLjiewCjfsJqkUEFkQ7kQoG1RmTbHmkBLZdP3Y2ejBgDnBr4hLpZeFYn5JTDjYCLHcD1x344rp r5q2PDLBE3/kCISSRAJmFrtCk2VQ8B2LkL4kKG/Bf6qKwiV6GUV84m71NncwGD7d8/5fj/oT8VT suiV+7oOdh4u9KBXKUoNPOupzq1ve+bEuJJtebx4rpdvNC5SV/iA4ju0oIRQpVrJyMJPRbDznBX z9c64HMpEFh9315j52fcSrqX/GV9x+8QrWrVKLszuy5SoASwg2VIp0KGp3QlGmwsaOJLitpB2b5 mL0CG2i7a0dpuZw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Hardware Programming Guide for DSI PHY says that PLL_SHUTDOWNB and DIGTOP_PWRDN_B have to be asserted for any PLL register access. Whenever dsi_pll_7nm_vco_recalc_rate() or dsi_pll_7nm_vco_set_rate() were called on unprepared PLL, driver read values of zero leading to all sort of further troubles, like failing to set pixel and byte clock rates. Asserting the PLL shutdown bit is done by dsi_pll_enable_pll_bias() (and corresponding dsi_pll_disable_pll_bias()) which are called through the code, including from PLL .prepare() and .unprepare() callbacks. The .set_rate() and .recalc_rate() can be called almost anytime from external users including times when PLL is or is not prepared, thus driver should not interfere with the prepare status. Implement simple reference counting for the PLL bias, so set_rate/recalc_rate will not change the status of prepared PLL. Issue of reading 0 in .recalc_rate() did not show up on existing devices, but only after re-ordering the code for SM8750. Signed-off-by: Krzysztof Kozlowski --- Changes in v6: 1. Print error on pll bias enable/disable imbalance refcnt Changes in v5: 1. New patch --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 53 +++++++++++++++++++++++++++= ++++ 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 7ea608f620fe17ae4ccc41ba9e52ba043af0c022..82baec385b3224c8b3e36742230= d806c4fe68cbb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -109,6 +109,7 @@ struct msm_dsi_phy { struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; void *tuning_cfg; + void *pll_data; =20 enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 4df865dfe6fe111297f0d08199c515d3b5e5a0b6..22f80e99a7a7514085ef80ced1c= f78876bcc6ba3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -88,6 +88,13 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */ spinlock_t pclk_mux_lock; =20 + /* + * protects REG_DSI_7nm_PHY_CMN_CTRL_0 register and pll_enable_cnt + * member + */ + spinlock_t pll_enable_lock; + int pll_enable_cnt; + struct pll_7nm_cached_state cached_state; =20 struct dsi_pll_7nm *slave; @@ -101,6 +108,9 @@ struct dsi_pll_7nm { */ static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; =20 +static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll); +static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll); + static void dsi_pll_setup_config(struct dsi_pll_config *config) { config->ssc_freq =3D 31500; @@ -316,6 +326,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, = unsigned long rate, struct dsi_pll_7nm *pll_7nm =3D to_pll_7nm(hw); struct dsi_pll_config config; =20 + dsi_pll_enable_pll_bias(pll_7nm); DBG("DSI PLL%d rate=3D%lu, parent's=3D%lu", pll_7nm->phy->id, rate, parent_rate); =20 @@ -333,6 +344,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, = unsigned long rate, =20 dsi_pll_ssc_commit(pll_7nm, &config); =20 + dsi_pll_disable_pll_bias(pll_7nm); /* flush, ensure all register writes are done*/ wmb(); =20 @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm= *pll) =20 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { + unsigned long flags; u32 data; =20 + spin_lock_irqsave(&pll->pll_enable_lock, flags); + --pll->pll_enable_cnt; + if (pll->pll_enable_cnt < 0) { + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, + "bug: imbalance in disabling PLL bias\n"); + return; + } else if (pll->pll_enable_cnt > 0) { + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + return; + } /* else: =3D=3D 0 */ + data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); data &=3D ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); ndelay(250); } =20 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { + unsigned long flags; u32 data; =20 + spin_lock_irqsave(&pll->pll_enable_lock, flags); + if (pll->pll_enable_cnt++) { + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + WARN_ON(pll->pll_enable_cnt =3D=3D INT_MAX); + return; + } + data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); data |=3D DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); =20 writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); ndelay(250); } =20 @@ -519,6 +554,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct= clk_hw *hw, u32 dec; u64 pll_freq, tmp64; =20 + dsi_pll_enable_pll_bias(pll_7nm); dec =3D readl(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); dec &=3D 0xff; =20 @@ -543,6 +579,8 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct= clk_hw *hw, DBG("DSI PLL%d returning vco rate =3D %lu, dec =3D %x, frac =3D %x", pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); =20 + dsi_pll_disable_pll_bias(pll_7nm); + return (unsigned long)vco_rate; } =20 @@ -578,6 +616,7 @@ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *= phy) void __iomem *phy_base =3D pll_7nm->phy->base; u32 cmn_clk_cfg0, cmn_clk_cfg1; =20 + dsi_pll_enable_pll_bias(pll_7nm); cached->pll_out_div =3D readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &=3D 0x3; @@ -589,6 +628,7 @@ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *= phy) cmn_clk_cfg1 =3D readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); cached->pll_mux =3D FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK, = cmn_clk_cfg1); =20 + dsi_pll_disable_pll_bias(pll_7nm); DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, cached->pix_clk_div, cached->pll_mux); @@ -807,8 +847,10 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) =20 spin_lock_init(&pll_7nm->postdiv_lock); spin_lock_init(&pll_7nm->pclk_mux_lock); + spin_lock_init(&pll_7nm->pll_enable_lock); =20 pll_7nm->phy =3D phy; + phy->pll_data =3D pll_7nm; =20 ret =3D pll_7nm_register(pll_7nm, phy->provided_clocks->hws); if (ret) { @@ -891,8 +933,10 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, u32 const delay_us =3D 5; u32 const timeout_us =3D 1000; struct msm_dsi_dphy_timing *timing =3D &phy->timing; + struct dsi_pll_7nm *pll =3D phy->pll_data; void __iomem *base =3D phy->base; bool less_than_1500_mhz; + unsigned long flags; u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0; u32 glbl_pemph_ctrl_0; u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; @@ -1000,10 +1044,13 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *p= hy, glbl_rescode_bot_ctrl =3D 0x3c; } =20 + spin_lock_irqsave(&pll->pll_enable_lock, flags); + pll->pll_enable_cnt =3D 1; /* de-assert digital and pll power down */ data =3D DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B | DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); =20 /* Assert PLL core reset */ writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); @@ -1115,7 +1162,9 @@ static bool dsi_7nm_set_continuous_clock(struct msm_d= si_phy *phy, bool enable) =20 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) { + struct dsi_pll_7nm *pll =3D phy->pll_data; void __iomem *base =3D phy->base; + unsigned long flags; u32 data; =20 DBG(""); @@ -1141,8 +1190,12 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *= phy) writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0); =20 + spin_lock_irqsave(&pll->pll_enable_lock, flags); + pll->pll_enable_cnt =3D 0; /* Turn off all PHY blocks */ writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + /* make sure phy is turned off */ wmb(); =20 --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AF3B2D1F59 for ; Tue, 10 Jun 2025 14:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564392; cv=none; b=h7ZOQ99VDimDkxWpmhTx23ZUx+lCyW+s6gCGVNr/QSwMUImc9nyGX6nchdSIo4IodsgGJbPYxJTyJG/p1QZF3h4A4ju8p56cMHOZ2+WZdjJyke1DsssMDcxe0YyCZH6wLl1emHnoGUCCjfC3CbDxkfm5J5XFKvjszDH4Mm8XqFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564392; c=relaxed/simple; bh=r3bCNGwO02nDr7rPnLE+84z6dEiHu1cfrjHc5wvaEJQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=phfNRVArjQU2fJpiWPeVSmr/x6UNQhYFPpAqInORB37kmN1z40lQr2JofweJNH5IKHXF7uh+J8rAFRr3fMjmrtpJsRTOkzi3uiT0gyd3wZWytxlsqUI1q2s7OYIH2i+xUWmjPFmBwXiUo3Oe/W+3lyBE6nmFdof7m5PvpsqzEdA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=viBVZIfd; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="viBVZIfd" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3a4ee391e6fso560647f8f.3 for ; Tue, 10 Jun 2025 07:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564389; x=1750169189; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nqJFAhZImmJLT6F/iwuPqcVqD25Q3l0Dm4UgxTgH1KM=; b=viBVZIfdyhKoS6jTqwrHgf1HJgIwk0eYch6n/eGUtVuMfz5wtFuHu+HErWwjeqdohI cp/FY/5IXZZ89gfiO1kqUWNIJkWc9U18kQTTENl375jqHJt8NxmaMI7TWR4R6FKS9zQG G2//NU08KH1JTdpTkuSLBMFoUFpFc2KRKWT92bnohU8Y8I1Zna/AxAPwMc8WvV+JWWPX Z6HAyz/vwfk6fPvVhDyJRH6KrwuJWidw+IoRhysmhx/Zz/9i0enJin74vbk7IrPLHqxA zFOt3LQbCf6VSi7gG1BK5rYAkt01ciN3zcn6WxA/RHezo5CcQzGkUH65/oPcAqMaVsTb K3Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564389; x=1750169189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nqJFAhZImmJLT6F/iwuPqcVqD25Q3l0Dm4UgxTgH1KM=; b=Fn+AmqXZq0dq/IDbgR9h7PwOMaLntMdfdqKmfaN4+rlwLMHtyLUnvZeJZSVTLnKnBM mAGuilUJ0jaWgrS30TbO0Uq9oeHv5JLleAGYJ4TuHuvHo7ojSNPIc1u2457PUNIkkL3w nrEj50TrafkUIHtIx/wM8NNccpmv8Yd/ybwbXEh8DDNQyjbchEaXdeuxpSIQYbth9IfA 5eZLUioayzfKn070yyCL/OGbUHRgvarJ/ut+UYKJCzft2XE/U7TOTJRzKIU0IEP6h8lW isfMqdRBGsSfMCOegFgZbeXKul4YyLAj1aAyDurRD1BbAVqxPgvp5Fxc4feAG8I70cME Jx4Q== X-Forwarded-Encrypted: i=1; AJvYcCVNqm/lrFQ2RTbHiLvGZBJR+Y3bMhwu41SV8S1mMtLJlMoF4C5f9PcigbrG9J/Ml+wQNY/CTP9OMLpgRjg=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2KGYPk3r0sooWPXJIjWgqxbjnKLBnyEerlMAtdnZy5yI2T7AZ X5EmeS8B2URe5lo7kOtQ+S8kjPM8i7xQ9aWrdyguu+LdKPc2jcWgVv54SDhJ+gd9qBk= X-Gm-Gg: ASbGncu5BKZnxTqegABQvP/SGOG5mhD/GFJ6e2dT/fMfdJ4qwOibPEoDIZac2QrAGa6 o/xL3h8KLir3WF93ZsJuO4/39FfAxPAAn7iYdMZLJDh5ukfhKZiPBaMFZaL2Xs+qZWP6lt/M6qF IhEkLKUXdPuiBw9bLbULYJCx0hwhOeLMpMlo7Cx+JpfdMTs5rMgkV+n2v0W8XTG/vNhWm4WEytf 3EkwD8AHA1Z+Ni5NskaiMxzOQd/7l3y7ELYCM+wjVFY4DcyF60kuDrfhSKTh9HCAMpqIRkEXkOq nu3nFoumhUghJt4Y2/ttfWrjyoSGhJziDFUOR+Xzn5bEq0rXpcZVSDVlmJrurw4OcLB6xaJk9KE ShbCRkw== X-Google-Smtp-Source: AGHT+IEEJ6z8QUKh5XvglJLU8dvLQFphknatasXcUl6yo3VjJtNGAm6I6i0raNXrO7ZgnDH935MaDw== X-Received: by 2002:a05:6000:1a8a:b0:3a5:28f9:7175 with SMTP id ffacd0b85a97d-3a533191acfmr4616866f8f.9.1749564388440; Tue, 10 Jun 2025 07:06:28 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:27 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:47 +0200 Subject: [PATCH v6 09/17] drm/msm/dsi/phy_7nm: Fix missing initial VCO rate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-9-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=r3bCNGwO02nDr7rPnLE+84z6dEiHu1cfrjHc5wvaEJQ=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvGQ72RTtMUU5JnIlCVSvh5DzJZTSCqtoC5f BLQ4MyBpFOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7xgAKCRDBN2bmhouD 1zxeEACV+ExG0wpSXh33T1H+6hfRwdZoJkMXq+pm3YaQ+LGLPYYRWRou/s/wAzV1Ggs39lpaqNM g3w0Wd/jyxS4Qqtf+ARoEO0NQPFXxXIkGyzlo1KZumESOxLJs479OAWcCPHQ2v0INNhusUyjabc tqD0WbEgdnUN7lRLhkfWzAJfH5J55eK2Vs4wZyrueipTtV0JUPIpyBfWNiNaNhUphYeARojUXbs 75WxP2LwNe4I2/sipeFsBQ6xwd/Hdh1elSXhm5ieoHR0TeyfiYBfnE3LGm2xVyQVm6RpQTj0pik hdUKhb4D9e2WM7Y8s04KrtxaxsZk9+Po/K9UceFvpayNfVgZx24wSteHLP2lRGBrh/PQsS5vSth PVf4AmohlAJId1pDS2D8KILoF3H8zflnIttuPpXhgD8N5nFMi0gDh53QOXLGBS9GMXPwPvDBpxr lLiKK1f17/f8mJjgzIPz6nw6iZCrgFzmr6pdkSNtbvr30xMg0Ah770CXWzl8XMmiKDKxeEISXzF S818rKPfELfaJBSanJlOWXPzbPQ3IggHyOEr6dTAPXB86D+7C+LpQBDVH8Q7jxEplJgj0vPsCPL kVZTdwGGMJUx+LlhM6/yR8LO/rgULXFTspW6wtwnK/t+jAew9e/FPIvZuPoNbIfvJ3vYUTRCe5y ABTKmPoZbjI5mAQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Driver unconditionally saves current state on first init in dsi_pll_7nm_init(), but does not save the VCO rate, only some of the divider registers. The state is then restored during probe/enable via msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() -> dsi_7nm_pll_restore_state(). Restoring calls dsi_pll_7nm_vco_set_rate() with pll_7nm->vco_current_rate=3D0, which basically overwrites existing rate of VCO and messes with clock hierarchy, by setting frequency to 0 to clock tree. This makes anyway little sense - VCO rate was not saved, so should not be restored. If PLL was not configured configure it to minimum rate to avoid glitches and configuring entire in clock hierarchy to 0 Hz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v5: 1. New patch --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 22f80e99a7a7514085ef80ced1cf78876bcc6ba3..c8b4a84b38340e0f907e0123299= b493768454160 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -862,6 +862,12 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) =20 /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_pll_save_state(phy); + /* + * Store also proper vco_current_rate, because its value will be used in + * dsi_7nm_pll_restore_state(). + */ + if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE)) + pll_7nm->vco_current_rate =3D pll_7nm->phy->cfg->min_pll_rate; =20 return 0; } --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6983A2BD580 for ; Tue, 10 Jun 2025 14:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564394; cv=none; b=osurImzrnRFBwXlXrJfAkCYe8vCupJ3wPHzMslJAAagqjl2BFhAU0uGEI5fMVeoNX/UQ0AQG75qGvRdL1KCr3/94ZryZ3r4Gj6Q326kXpC7F+FX4X+90loN7CTKB+16JI0FWm+ITacuKSbn/5ChHOBBii8Yq58NE2nr4jL8PZ5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564394; c=relaxed/simple; bh=rD/vxqx5nSUfP2XbOh0k+p4MMI3tgwoJRLYjdRzeMRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k+HqbNDOHrY/CIHLF1zyf6/GJmZcl3Vx4Kkxy1+RwnMDB57t0Y0h4APzxbULHCATeRq/sI6vSaK3iZJBuQAFzXO/pljHYp4iD0D2JvvoaRoB2XV9xxm//fwXSIBi/SemYcFu9MIy44GxkhUUroFpmo9q2qsj5OOQvlUY6duBC4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hLFuOwzC; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hLFuOwzC" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3a4e749d7b2so729247f8f.0 for ; Tue, 10 Jun 2025 07:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564391; x=1750169191; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J+s2K9q0nfSbrKocqSr/McebFVTHHj9+pTuCq5ceG5Q=; b=hLFuOwzClrjVbfFh6VfW6VvqQYuxpyKFSgIv0VC+oQNIX6SF5KQYwyLITJ/bldEGa1 kdwQhV3SX7Rp0mBP0GWEmravGGRoEumBBCyjk+bSipFfO4XzXbAk7bm7FFxbRAdIpxAx n5JrfVoByZKIhSfHfxy35Mzms2CFPuShoNwBvDHjFW4eqn44fzQZbl1gs8pMdadI9FN7 bkTbVAuBTwdALD03KDtcvIsfuufRDiOo2ahQZWekicFj7+Gce1H3wOm7Fhm+mh+VTRMz uwooEhDoRa1mWrgBylU6Rafw02xBK4iJ6pyvoyUqTzb7QC/687E5XbPivO7oegeOvz8n 7QVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564391; x=1750169191; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J+s2K9q0nfSbrKocqSr/McebFVTHHj9+pTuCq5ceG5Q=; b=W0BrtneXQyRZoCBsWXO7AIRuseDXNqVFpHcY8iLoJG0MUNTOC6v1dlnLlJS6BGxOFv iuj4t6Bp0iHlTiKrWRdjVOzVRgW4PlhWQOLYTAI1HuOlBRhjmY5ykVKQv8SMr6S+M7TQ Tu36uDRVc4+f/DjNuAGdWAPBzsnb1rrFjrq2LmCgQxnaRG8QX9o3R3K35i+JKkokDpaG oFd9+UNAnJtb50rpFIbtkUnPrhw2YuyBV18AWNHlwKoQ1Ea/8ZT0+BTuuK6JtWwCfEVf Bs5HISz35uxqFRsbH/SyaIEx4yXy8Kj8e9OmYunVnv7Lt8qwPHEeabbHqwBHCB+hf2Dz n9AA== X-Forwarded-Encrypted: i=1; AJvYcCWzNnj27iczFB4E1dbsXrzC5Urqb7ZH+MxXWdWPDGu1QulEM8ptIykXevjhMfG+Wo1LxqNZ3GMKugh7PtQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzdGfUxqk/pXWwSqrrZ11c6yLw7xDsnir+92DG+tPgrBRGQUXVY DH3eoInLijwRdKWr6MNPrDGe+0stOSd252r1PeoY77rZv2OJmlLoSWt6kTZmaRKv1iI= X-Gm-Gg: ASbGnctVNbTwRSGx8p8kKMLpf5OHh2SZixfVlNos0Rz+RRZUcTwi2NsBlqTatINF8bR IwF2P186uRqV6z35vX4FkriL2bDjSJ/vcCXiu5KLmWu60QsDcGsHRrnIEqpc3jaThTHJXgB6ZXr sdbzpi0i7q9aaYaOTXKu/u1tcuVfua22Lwoxl4kX6jLy4IhI9WOcFhtrsZGoumvp9YExQaOJ+CK uhMVUbZjh8Q11M6XXk+RnB0CeX4EOq3caTJ2SNT1L6SPdMVHW64cl11xHvhZ7ag/0BwxrYNSRBw 3TakFHkQV3KZBpGvEfFgrj8WXfqbCs+Lw8tqjwhu4WQoKubCh6dJu0RBtdeto2ta+s2hpPP2iin kMiWOjw== X-Google-Smtp-Source: AGHT+IGOD7neS88gds4HjMSeiykUy2lf9EPuFamRjB8ThGGIlXT3+gNiU9q5oyf/nxbFns/0GxUlTA== X-Received: by 2002:a05:6000:26d3:b0:3a4:d7c7:89d1 with SMTP id ffacd0b85a97d-3a531789bb8mr5438073f8f.4.1749564390577; Tue, 10 Jun 2025 07:06:30 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:30 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:48 +0200 Subject: [PATCH v6 10/17] drm/msm/dsi/phy: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-10-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10153; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=rD/vxqx5nSUfP2XbOh0k+p4MMI3tgwoJRLYjdRzeMRE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvHUNhdu3vSKx/mraq9Kly5KAZiQfWX7c0JK 41wUf+BNMSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7xwAKCRDBN2bmhouD 14IjD/wP95Wp0SNg33Fm+5sDnjY4h7IEFpwDtESb5WPp2bnpxwdKV543cD2webG8KFgWAqn3t64 P3Mtm+DSpy2AWdtJNpoicTOyWL355MkW95Qpja0snlHcN2fF9X4HrvkdcxKMcOpWgJT9u1o9sd/ bL9ZN6SbtAcYUxNi0q3Rfnuaqt4FrqNe47bZirxwfilTaDK4S/k1XhnyP3o5buo7nd8bH3ecsNB cw6P26Hffj+bjI1ywxyNja0sYZrrzmafQlp5wdFGkj4DFsVbCvfxYuc5YLPq0h91MoZP21ye3kb FfTvfW8YgicTuo5dRZwxg/E5BecI6ybNfqhibhmTrwlPNCYeSRfdEBMpKgk7vQfTTnA1htJqPIs 9NS/3srf0SRZDdplpVsepChyX1uMMC+k09vu8rugzNKPjLAqD6+pV4dTYEex7M9efbuZtgmBhrB 6b4EwnKk9vFCr5/Mg6Ih375zIJe5/SOZa4tqq9dWvcRHzvsQz4RFbjoK0E4ZvVxWRMp9/ciapgu /2/MO17YPelMXquw7n6qIpC/4PSRXQ/sfUtl89b5FYd+g+J7jihSzgxwLJEcxDRD+5cSFh0f+nn jdYhFueUP2R4/7U2+OwVmATGv3BK34IJeQbl9yr2xZJEmz2BDNlQTjqK687QEAtjRIjwSLmFuc5 1rY6JjXSnZt4PTA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Fix pll freq check for clock inverters 160000000ULL -> 163000000ULL --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++++++++++++= ++-- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 ++++ 4 files changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 5973d7325699bf5fc67c4cf93fcaf04abb618b46..221f12db5f8b7686b2f37524322= ea3e118f503b1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -597,6 +597,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8650_cfgs }, + { .compatible =3D "qcom,sm8750-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_8750_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 82baec385b3224c8b3e36742230d806c4fe68cbb..93fb5a30a755f7cade56af27164= 0670cbb2e50a0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -63,6 +63,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfg= s; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index c8b4a84b38340e0f907e0123299b493768454160..fd405e257f89181f32432dc4865= 475eeb7a88f5f 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -51,6 +51,8 @@ #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) /* Hardware is V5.2 */ #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) +/* Hardware is V7.0 */ +#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) =20 struct dsi_pll_config { bool enable_ssc; @@ -139,9 +141,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *= pll, struct dsi_pll_config dec_multiple =3D div_u64(pll_freq * multiplier, divider); dec =3D div_u64_rem(dec_multiple, multiplier, &frac); =20 - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { config->pll_clock_inverters =3D 0x28; - else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll_freq < 163000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 175000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 325000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 350000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 650000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 700000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 1300000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 2500000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 4000000000ULL) + config->pll_clock_inverters =3D 0x00; + else + config->pll_clock_inverters =3D 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (pll_freq <=3D 1300000000ULL) config->pll_clock_inverters =3D 0xa0; else if (pll_freq <=3D 2500000000ULL) @@ -260,7 +283,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7= nm *pll) vco_config_1 =3D 0x01; } =20 - if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { if (pll->vco_current_rate < 1557000000ULL) vco_config_1 =3D 0x08; else @@ -669,6 +693,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy= *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm =3D to_pll_7nm(phy->vco_hw); + void __iomem *base =3D phy->base; u32 data =3D 0x0; /* internal PLL */ =20 DBG("DSI PLL%d", pll_7nm->phy->id); @@ -678,6 +703,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: pll_7nm->slave =3D pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; + /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) + writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); break; case MSM_DSI_PHY_SLAVE: data =3D 0x1; /* external PLL */ @@ -966,7 +994,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* Request for REFGEN READY */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); udelay(500); } @@ -1000,7 +1029,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *ph= y, lane_ctrl0 =3D 0x1f; } =20 - if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (phy->cphy_mode) { + /* TODO: different for second phy */ + vreg_ctrl_0 =3D 0x57; + vreg_ctrl_1 =3D 0x41; + glbl_rescode_top_ctrl =3D 0x3d; + glbl_rescode_bot_ctrl =3D 0x38; + } else { + vreg_ctrl_0 =3D 0x56; + vreg_ctrl_1 =3D 0x19; + glbl_rescode_top_ctrl =3D less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl =3D less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (phy->cphy_mode) { vreg_ctrl_0 =3D 0x45; vreg_ctrl_1 =3D 0x41; @@ -1066,6 +1108,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) =3D=3D 0x20) writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); =20 @@ -1182,7 +1225,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *p= hy) =20 /* Turn off REFGEN Vote */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); wmb(); /* Delay to ensure HW removes vote before PHY shut down */ @@ -1453,3 +1497,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000, 0xae97000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/driver= s/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index d49122b88d14896ef3e87b783a1691f85b61aa9c..f41516dd0567ca7406b0d41c941= 0e28084f2b03c 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -35,6 +35,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -200,11 +201,24 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> + + --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E82C2D3A8C for ; Tue, 10 Jun 2025 14:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564396; cv=none; b=o9InLHyhbJ+OCYla2haiwS7oWcG3fVLscO/K9pFhfU2wHU8v/FAWHiJ3xAbMgijYxQygZ0VbmbO6BqU6z08WQiQRhuEfaLtXk1GCr/fa0qcldFGRzcfkgtKNzZdPz0L4J/dNf6Vxx3TQ1zdCdgfWP2k23XiDQXrqKW/Kue7v26E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564396; c=relaxed/simple; bh=RVRVpDpk5e02GBpHtLhC0zusFHyQp8dYyvMNvbXaCMM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E8HN7j1YnsWmx/i+3to6QYG0LxWy0f73p4RSzyGV+pW3+j0eJW4VCNZv1v8gbaeZQtgkg2j+Ng01+yKCxkulgsF/vLWzFkKTxwnZ2S3oSP2XLubgIV4lo6coWc4/NXkOt0x3JrL7jfwoPrC+/1mFCuTmRZa2GhAfOu4M9zAKLRo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=YoP3byUl; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YoP3byUl" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3a4ebbfb18fso482471f8f.3 for ; Tue, 10 Jun 2025 07:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564393; x=1750169193; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=O7Xnhdm6O067a6DKPfqxzqYdx8kufZxaDc0SclDxluo=; b=YoP3byUlZhmSyyIFNFKGjlwQgdNR1QIrOBtVL3vJQMDRSwA4oxfbCgYwqftUAE0uGW mhJrzPx1jUPH2FmPDaHXW21NPUGf0sf8BPTZqjcmCtZF/0yxbnNeOFv+8cfXaLRMzSkq H+ciiNSOtMGvT0SQZe03yTpN+n5RBOYEA60+CM+vHwdJBhcaEBfRs/1WxQ3PGZPI6isa aXAMGipzdkvurvJLKO7QtgaqTyVc9YBR2HwRr4X5bPzlX9AxHXkk+4ntkTbXEQZAhQSb vSnuKxtLWJN05lGvYfgrrLnfinIIaEPfHmmuRUHvVvQKE0Orr1Al23hv3r08id8JEb4B 40eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564393; x=1750169193; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O7Xnhdm6O067a6DKPfqxzqYdx8kufZxaDc0SclDxluo=; b=r1T0iOBmvrEtwBr1fZRDA0JFzqeXWjsMf5Pyh0pBSK/CB27S7oFTrpGiK9ifkQ3WYp +WTWPx3gsJ7Q7NAkC0mekLeA5uYqCszs1vDkKvEl4EnEWZ+DxGI3hcVshRRjXol3BNsE i615K7bBulNBRddefBStwzXbuukVWPZjjXdO6e0RMYB7etUUV4OfOW5Q8iaCSZRnXfZw 0+rBWxvwc1syzs2SJ42nZcpHUs8TVR529Doo5SAAIdQhP76rYtf9h81pwz+rcpp/rCaj kuYQEAmBa0Qbg8FVw/9JIP0CSz0PXwEV9xfQq9/NdjMoe+Ea+AotnoLxD1+JyFgGrudC CRWA== X-Forwarded-Encrypted: i=1; AJvYcCX8BHZUGfdpQ9QSZI8PCoFIh58/PHrnC88rbQYfFYSOfeKbwBLAkp6hi+246YkeXN8iBThm0pODvspZ++E=@vger.kernel.org X-Gm-Message-State: AOJu0YwwBvInQTPag9aKd3RlZbzvFVX+fZdHFwT7pJ1Fb9YybA1iq6mU imLDFskd/+B4GLcTswlLU6k5Z0zugtmXQN+dakMu8TW5WW85s0NyzdhHFwxotws1tTY= X-Gm-Gg: ASbGncuvkiHuUurO0/fPCh1TLkQuZocEGPqGtDrVdeMrnp1J1dJTZkjVrW+K2Ouxviu LZPBrGjT/8roUJGK6xpfHo484lJrLs9qqoWqSQP9GjBlci15lmXUeUTe8hOkpp8c7xA8fAZ2q9c tWD+GEbKQvP2Lkm0m1v6F3zBvR+CPAyzP/fcgxhq6V6HVuk+ndf+yHl/LPHEoti7beXI/D36OC5 s0nwy6mY+vlSD2bBGAAAMBAi5v/U1aUVK8GIwMuLlzJfqcmd62nkxK9ZHzeOs5uoprga28ycJRc USS/AGxT69K0YA0h5B47grbxz9IkamMXz++NIwoTte5tMaaA4v59hTlCommI2GSjMzALRfitxbB 4NjMfnQ== X-Google-Smtp-Source: AGHT+IGOYy6gNJvwDYDuWTcTmfKk+w0ICVA8j4N6n4/MeNFl8oHxLLgNUbYgeuEtyugbX6DHbnBWOg== X-Received: by 2002:a05:6000:4284:b0:3a3:6a3f:bc61 with SMTP id ffacd0b85a97d-3a533169e7bmr4838341f8f.7.1749564392604; Tue, 10 Jun 2025 07:06:32 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:32 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:49 +0200 Subject: [PATCH v6 11/17] drm/msm/dsi: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-11-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7262; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=RVRVpDpk5e02GBpHtLhC0zusFHyQp8dYyvMNvbXaCMM=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvIDUbJ5ORF7joqZD6O3hJp706AO4TzyryqB Qv3Jjc6uAeJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7yAAKCRDBN2bmhouD 16wDD/9s8xESUj9eoTpTjqRpca/XfYi7KbfOZtPrPIeYYQ1YnnFV+zuM5K7ewyqr+G8XfEzZXTb zSHXvou4p0civOltuE1swZk5662u1xGLHHlGxjyoJkQsUrnqiqrTVclnENvnyMgi9fZDjAmMV9I WV+OtZRCCTodmNM+toiRT84FF1PUkZY+16rztGcqTWCQge9UndUk3OEyevR4l/JTNHSjLDbB0FO 4w3kvULr8KJxOC9zrp/VutF5AnkrkQWkDaJkCpUMRs2h4QNtwm+97aE4a+L2nA5xmgImzkcebjI O9sufazjN8voiYDZiEh5GsMLzPD/t+hh7khpZRhCZRE+q6WXJwoPYS1ZPJ8saEe1rU3pCQlzL9+ 73bIU9XySDDIcf87HbAl5a68uC+JM/+v/MunYVUuNzE9bV+RIrErO7uLC3bNKJMPF0Emo3kbPaj oeWj8b2Y2ir5SUhRXwZY/3aH6rj9UUSSu3JHIML7D+KyqsLnBgh/Pd5baYlnYpqYzCGRQrarmtb lG+XPBXXFTD0XbMx5Q9YL1sBjWqZdx1MPqoMIYkaDSQNPHiRBWH5RR+zHWeEvQqmwdzJ2rDPXFk QPp6iQpO4PXKzPCF0XQi03+0EiPpvddddvEZRzp/aj3B22WVO1ou0LmzDmR4Se+vLEXCfNqrcNE mBeGqf57qzHnytw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI on Qualcomm SM8750 SoC with notable difference: DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as parents before DSI PHY is configured, the PLLs are prepared and their initial rate is set. Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- Changes in v6: 1. Drop redundant parent clock enable, because this was fixed in the DISP CC clock controller driver. Changes in v5: 1. Only reparent byte and pixel clocks while PLLs is prepared. Setting rate works fine with earlier DISP CC patch for enabling their parents during rate change. Changes in v3: 1. Drop 'struct msm_dsi_config sm8750_dsi_cfg' and use sm8650 one. --- drivers/gpu/drm/msm/dsi/dsi.h | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.c | 14 +++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 87496db203d6c7582eadcb74e94eb56a219df292..93c028a122f3a59b1632da76472= e0a3e781c6ae8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -98,6 +98,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); @@ -115,6 +116,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, = uint64_t *iova); int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova); int dsi_clk_init_v2(struct msm_dsi_host *msm_host); int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_= dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index 7675558ae2e5293ff2f239e8b19154f2a5c86957..fed8e9b67011cac1f766a5bc47b= d5117304ab0fd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -273,6 +273,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2= _host_ops =3D { .calc_clk_rate =3D dsi_calc_clk_rate_6g, }; =20 +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops =3D { + .link_clk_set_rate =3D dsi_link_clk_set_rate_6g_v2_9, + .link_clk_enable =3D dsi_link_clk_enable_6g, + .link_clk_disable =3D dsi_link_clk_disable_6g, + .clk_init_ver =3D dsi_clk_init_6g_v2_9, + .tx_buf_alloc =3D dsi_tx_buf_alloc_6g, + .tx_buf_get =3D dsi_tx_buf_get_6g, + .tx_buf_put =3D dsi_tx_buf_put_6g, + .dma_base_get =3D dsi_dma_base_get_6g, + .calc_clk_rate =3D dsi_calc_clk_rate_6g, +}; + static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] =3D { {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, @@ -318,6 +330,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0, &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, + &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; =20 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 65b0705fac0eeb1b7d7b001576215b8578c67e25..38f303f2ed04c37916c9aca148c= cb569e816e35f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -31,6 +31,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 #define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000 +#define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000 =20 #define MSM_DSI_V2_VER_MINOR_8064 0x0 =20 diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 4d75529c0e858160761f5eb55db65e5d7565c27b..6400f72a66f0af2ffd8900a9cc3= c8fa3f79b626c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -119,6 +119,15 @@ struct msm_dsi_host { struct clk *pixel_clk; struct clk *byte_intf_clk; =20 + /* + * Clocks which needs to be properly parented between DISPCC and DSI PHY + * PLL: + */ + struct clk *byte_src_clk; + struct clk *pixel_src_clk; + struct clk *dsi_pll_byte_clk; + struct clk *dsi_pll_pixel_clk; + unsigned long byte_clk_rate; unsigned long byte_intf_clk_rate; unsigned long pixel_clk_rate; @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) return ret; } =20 +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + ret =3D dsi_clk_init_6g_v2(msm_host); + if (ret) + return ret; + + msm_host->byte_src_clk =3D devm_clk_get(dev, "byte_src"); + if (IS_ERR(msm_host->byte_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), + "can't get byte_src clock\n"); + + msm_host->dsi_pll_byte_clk =3D devm_clk_get(dev, "dsi_pll_byte"); + if (IS_ERR(msm_host->dsi_pll_byte_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), + "can't get dsi_pll_byte clock\n"); + + msm_host->pixel_src_clk =3D devm_clk_get(dev, "pixel_src"); + if (IS_ERR(msm_host->pixel_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), + "can't get pixel_src clock\n"); + + msm_host->dsi_pll_pixel_clk =3D devm_clk_get(dev, "dsi_pll_pixel"); + if (IS_ERR(msm_host->dsi_pll_pixel_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), + "can't get dsi_pll_pixel clock\n"); + + return 0; +} + static int dsi_clk_init(struct msm_dsi_host *msm_host) { struct platform_device *pdev =3D msm_host->pdev; @@ -370,6 +411,26 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_= host) return 0; } =20 +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + /* + * DSI PHY PLLs have to be enabled to allow reparenting to them, so + * cannot use assigned-clock-parents. + */ + ret =3D clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk= ); + if (ret) + dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); + + ret =3D clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_c= lk); + if (ret) + dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); + + return dsi_link_clk_set_rate_6g(msm_host); +} + int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) { int ret; --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 607DD2D8DB9 for ; Tue, 10 Jun 2025 14:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564401; cv=none; b=Fiwip8S2WAuTNgArrFfhqTPi9pddhQeWsT0iWok1zk893nuA64uXhdrHHplRhsHj1Swua4unfK558Q2+QoG20dQbpKThT+Kwd2C7SS0BHQOSRPDoN2OIJ9+ZsEZziIBine9HzP5qSP8S6ypR8V66RmfT//76QKfnuP54+YgKOxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564401; c=relaxed/simple; bh=9Pj7Z/cWajLnxwxWaf/h+pVz5yTEei1Ql0+OZD4CqNw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aEomRsib61uP/uRJ4EJyTwbONRkQH6NlL08jYnJOjMzB47XDnw+6x3wYZxC+BUEnweNIkeIdyi68yymAVjLuQrDjJ0xSEcDT4etwdWsJ+Z6U6Sswc3+CUTA8XYQ83O+qcZyFjm5VfCPQsvdI0j6qISTTC39NuErekAEgamzc5LQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=HV7R75ET; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HV7R75ET" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4530e6f4db4so980045e9.2 for ; Tue, 10 Jun 2025 07:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564396; x=1750169196; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=A9ZWQybGIT9pk/r23HTdQ1LqXIT6yHtJ2X2MvFB13UA=; b=HV7R75ETiAWBnYemxFYuG0x/J/sw+twferUcAYc5AebUFVH+IzpZLDMra3VNY7cqzU qtO9FLmaEb/a8kX1p+hR0BYMr6tKUTJVLstbT1S37DIMUF0W2GVVsyKhUmqhjqYxZfuG q24uVjyMSVKPoSE0c0yUgN8sG6grLqX+J6smUB30Pclv7eHLF2p+DR/ObK34P8J6ltij ayuY/37JaMIF9mkydzv1KJxMzrDF4p0xvk6gbrItnlhuIMMk1vX6utrIYC7agoEIzWLz M8ZozNtg4GPdzzMDroPPdDauHPxq+s7pxDclP098gpV79y8y66/yv/gjLyXgIXYnGRX5 /9yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564396; x=1750169196; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A9ZWQybGIT9pk/r23HTdQ1LqXIT6yHtJ2X2MvFB13UA=; b=qsFhLP6KP60G4+FGtnJeHxBP3RV+3YaQBr6msXON29GgVTHsOQwU/AkYX52uGRRrZv 58addxchrB5GW79hXwthYZp0401MZYaIA7f2XuPlLQlaNt434rARwDtCg9qa2uSz7tMG NUsuYyZ8V9Ltb4YHqp7HV7NLuL1RhBystel8dI/6j6z8o91rIqfmsh27d5cElUKIsra+ 5t8M0SU1CW4mTPPFniyweNmVwKKOhGQwvyXYyKrAuyXoAF3+iw+WwJuEg2Do2lJyEJcD 4jEjlN7cskg0ZWwP7QaY0x8kLRo9khbrKprt4z4s41FRrIecQ38ursOP43zCvuqs0LvR 2XEA== X-Forwarded-Encrypted: i=1; AJvYcCUR+bFvh4LV03xs13fSxPJ+yKeykAgNYpEgMnRLnDVLK5J7yRuPKaaRpnYzYsxxDHmwr24sAL/NcK/pHzw=@vger.kernel.org X-Gm-Message-State: AOJu0YzsWZo+W3Jw/InWEvCo84Xd+g/O9HzWLkQsJTc7HgIg+oK+qf1y wnQURurX/YwgXbh12mNnN3YaxCF97QILDU7mguk0aKmtJQNskWTkEIszHQMvOv+dJQo= X-Gm-Gg: ASbGncuFe7Oz34Fh3FNcHDf4wAJIRn6Ok4tiomIlkpHn+TE8LEYJWlvPoyhw5nsrd6W +mAyu16JRbwQ9prx0SvvbOkg8DDYpqpmfuVBWIc84XgSjE2GYJyMmUWxvtPm5ahCwP4uU3uFWZ2 66BPbUH7fp9d3nkVaZFVbENJ6vF5H02BNi/e9uGYEDjAqOhCuGC0Gf7D/0gDhDeoDsziZvKJart +bZZbHwSMIlHlfk3vRdt2T3WywHmgFb0fST//rAzhRDtcYo8oseMIxCAsjv4pQnnN3stBnlo00Q w4lFxd6kKe/BIHxqkOMINDivfcbqy+ZyxOqSklKQ4SfvcmH5s8b3K9oQ9S9nW0LEs3V/w9UM4RV Ha0g1nQ== X-Google-Smtp-Source: AGHT+IF9rWetZA8aq/ZyInH2riOru8Jxxffwa5+89PShq0USi64/M5xsdt7ibbjw3+PcuCXHaBleqQ== X-Received: by 2002:a05:600c:c83:b0:439:a30f:2e49 with SMTP id 5b1f17b1804b1-452014b3cdamr58907795e9.5.1749564394723; Tue, 10 Jun 2025 07:06:34 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:34 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:50 +0200 Subject: [PATCH v6 12/17] drm/msm/dpu: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-12-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19147; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=9Pj7Z/cWajLnxwxWaf/h+pVz5yTEei1Ql0+OZD4CqNw=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvJOVtF2cgges6j3KUlPKS2nDMBORl5ceKZf PXPGyiNn+CJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7yQAKCRDBN2bmhouD 1+xJEACDhoUc9fJFVwzJFf9XFjTHEFDkvjYB8qJmm9qWJqTlYk6h6RtxBtIPmtmhd+AhOdrfJap tJyS/t9/fTQ9qdXyke9pJqZbkTUCl+mKMoSmLMzMOYE2yHkRu8yA3hcrshsl5CwpJESCIUHrFgU Fy158Lxki9LA5TUYcPywgsp0Qvpye0T0Z0PgjmncPqHqGv7LCrBmGdw8JqzObUeeo9GVHa0YWYZ Hi6LDybR7XxeM6EVeHsRRqQ0VD9g9AClJ1My/MNjNQA5n+/Ui/bE9pLoGsiRVA2LjLu80BkY3o5 BpaokHKHywlXEWbuRXg2ePjOx6Z8FWvxI2uyd8FY1nABUyuTwY+MK4ugZ/oeQqWnVUg+t/8q6Xc okyBWJNkGaUJoQmdzLoKlAr6lmdzI8+OIyXA8DyTGaU+A0p2CGOH3o1rT4HpWO2MCtwqGan9upg ssBfGmihjkeeU816WVDPx7VECH8ST6eWb4AXLjN5lc5h4LRnN4bmMw4DaL2XKuPaaf6j5hycgVX X3JvUapp8E4JA49tYfRNxYi2A8PL55cBi49eC9U4zwHArE9mgp8rT1SmPKx+PK7z73gXSHNlWkr kJv4Fu25a/zE2emQ1QRUGQXqkry3NT5+eQNNTSd9+HNj0TN4KGUBhlRLFIeb+khuI/zk3jsxxGm HEbu8iga2BQezBQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU version v12.0 support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v6: 1. Changes due to rebase on newer HW features patchset rework from Dmitry. Changes in v2: 1. Add CDM --- .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 494 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 525 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h new file mode 100644 index 0000000000000000000000000000000000000000..db8cc2d0112c87711a420e4912d= 6e76dd432bc87 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Linaro Limited + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_12_0_SM8750_H +#define _DPU_12_0_SM8750_H + +static const struct dpu_caps sm8750_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sm8750_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg sm8750_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8750_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg sm8750_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x4a000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x4b000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg sm8750_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm8750_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x6f000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x70000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x7e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x7e400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x51000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x66700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x7e700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sm8750_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x83000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x83000, .len =3D 0x8, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sm8750_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg sm8750_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7e200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7e600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg sm8750_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg sm8750_perf_data =3D { + .max_bw_low =3D 18900000, + .max_bw_high =3D 28500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sm8750_mdss_ver =3D { + .core_major_ver =3D 12, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_sm8750_cfg =3D { + .mdss_ver =3D &sm8750_mdss_ver, + .caps =3D &sm8750_dpu_caps, + .mdp =3D &sm8750_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(sm8750_ctl), + .ctl =3D sm8750_ctl, + .sspp_count =3D ARRAY_SIZE(sm8750_sspp), + .sspp =3D sm8750_sspp, + .mixer_count =3D ARRAY_SIZE(sm8750_lm), + .mixer =3D sm8750_lm, + .dspp_count =3D ARRAY_SIZE(sm8750_dspp), + .dspp =3D sm8750_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8750_pp), + .pingpong =3D sm8750_pp, + .dsc_count =3D ARRAY_SIZE(sm8750_dsc), + .dsc =3D sm8750_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8750_merge_3d), + .merge_3d =3D sm8750_merge_3d, + .wb_count =3D ARRAY_SIZE(sm8750_wb), + .wb =3D sm8750_wb, + .cwb_count =3D ARRAY_SIZE(sm8750_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(sm8750_intf), + .intf =3D sm8750_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &sm8750_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index a276a1beaf95d183f6119452e5516fa8ee60cef6..e824cd64fd3fdf2ab0db92794a0= aaa57c109decb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -326,6 +326,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_2 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 3)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D + _VIG_SBLK(SSPP_SCALER_VER(3, 4)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -360,6 +363,16 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk =3D= { }, }; =20 +static const struct dpu_lm_sub_blks sm8750_lm_sblk =3D { + .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages =3D 11, /* excluding base layer */ + .blendstage_base =3D { /* offsets relative to mixer base */ + /* 0x40 + n*0x30 */ + 0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0, + 0x1f0, 0x220 + }, +}; + static const struct dpu_lm_sub_blks qcm2290_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_LINE_WIDTH, .maxblendstages =3D 4, /* excluding base layer */ @@ -381,6 +394,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk= =3D { .len =3D 0x90, .version =3D 0x40000}, }; =20 +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk =3D { + .pcc =3D {.name =3D "pcc", .base =3D 0x1700, + .len =3D 0x90, .version =3D 0x60000}, +}; + /************************************************************* * PINGPONG sub blocks config *************************************************************/ @@ -412,6 +430,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 =3D { .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x10}, }; =20 +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x24}, +}; + +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x200, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x24}, +}; + /************************************************************* * CDM block config *************************************************************/ @@ -702,3 +730,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 47d82b83ac5378cb0001b3ea6605dc0f98aec5ef..a78bb2c334e30bc86554bde4535= 5808b790c6235 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -778,6 +778,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_sm8750_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d478a7bce7568ab000d73467bcad91e29f049abc..df9d6a509bcd453978bc2491795= a6ef87cc95638 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1533,6 +1533,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8450-dpu", .data =3D &dpu_sm8450_cfg, }, { .compatible =3D "qcom,sm8550-dpu", .data =3D &dpu_sm8550_cfg, }, { .compatible =3D "qcom,sm8650-dpu", .data =3D &dpu_sm8650_cfg, }, + { .compatible =3D "qcom,sm8750-dpu", .data =3D &dpu_sm8750_cfg, }, { .compatible =3D "qcom,x1e80100-dpu", .data =3D &dpu_x1e80100_cfg, }, {} }; --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A50002D4B79 for ; Tue, 10 Jun 2025 14:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564400; cv=none; b=KNYFsSGf9jsmLqkXaxpkX3BBXSvzM0R6+C1U2Lenf/eZbXYz0IoaEDARrKbujHTap3C88ki6ZZugv2qJedp9b025WemlefRPaaJnyn5MeqbC1hfrEACL7q7m9WeI3hdWgNfGRq4ncOL0snUW6JN6+VNYXgNg+OOOJs79/FHHgP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564400; c=relaxed/simple; bh=Ez4rm6PFGrlujB66CVWxeGwNOdP1q/LlPEEBuX2j8C8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L7W/yfS4o96NQY/CTchBFlJlm5v5XjGE/S3eddkIgavK6OyudX/lmlRBgPHMXrnZ+lIaR5HH/eRP/ctdhKTNCi/SNfMZDzBt5azAFNQwQCF8PqVDqDNlbsbpZk1Hajtmva+gV+tSSlJAHd+Ux05vlgbYSR+3MhTmxRIwAZ2C3oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=HFbUKNOn; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HFbUKNOn" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4519dd6523dso5767365e9.1 for ; Tue, 10 Jun 2025 07:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564397; x=1750169197; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fhJitdsInvgOOCf0kNoqN1nTD4JPV3++bcIAyD0Ca8I=; b=HFbUKNOnumaRPpCOBpghWfX7K/MNC+w2rIYpKBU3RsdunyHaUNz+7d4XzjGAuoGuhI 7L5dd8Uc3QVzO9QutlZbXdH7vg0duauNK9KnRQEomJc2BgmMKzMlBSfbpYJNq3CF+CE1 GUZrQzmgE3rdVeOXDbcq1jYp6eD5L2N+t6Pm/nmNYwuGD8ZV3A5BegKonZTNb2DPXV5B Dys3gFmfRv+AfzT3IhsWAKfxD972EZXdY2NrwwUgfCXM4HwmkMGAbG6noIDHY+KztkMK nr1hh4h7A1OlZ0Bd6f+XOFueEAOwOwQgIZgYDjpHCZ7T6F6ai/d2eETIEUZiZDS6yIKZ 9XEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564397; x=1750169197; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fhJitdsInvgOOCf0kNoqN1nTD4JPV3++bcIAyD0Ca8I=; b=oe8wwKY7p8kJ+Y/OBegrxEoDDcPqPG9z6Eyqo0n1xXX3r2BWm8fUDyCV8V90hluPQ9 9xpo2POL6bw+7MZquymW2NxR5tyFSpuvJQ/PkqjFTEIr3N/s9M/WDQv/nqkL1TZ420BH r9AtrlZ79OfOPr9T2c76jMFGdjareTNzf9wxREP3uV/nmb1k4EI+w+u9TNA9+vqCo6Lk F8rEJZ0cFaLdnCY9OYa5L3E36HgEtMattwbv1/90+MihL94fIXkUuWkvC7jCkDP53LEs zNnyCVB+0IISs/sCLmQT7Q3jFPD9+n5sbsq9yStamJGNkzGqph3VS6gIMYpc4JpzPqnl 0y5w== X-Forwarded-Encrypted: i=1; AJvYcCWnxftlVytjGvOZsQzHjFf+csOU7ORtaOcN7y5cj2C3s6v4pWsVDjGsEyqpOZvQ3n13MEVCBqukNvF+V+M=@vger.kernel.org X-Gm-Message-State: AOJu0YzepArKcItnWG9r5dHUCRTSMndYkaQ5ErxMpia+esNOeRvparqN CA9U2kpUXu3lA81EZ4rF6Ewmb9qG/7pHGlRCHKw8lVKIJPAbz+Zzbl+QmuLN1Y2knyo= X-Gm-Gg: ASbGncsw32hDwC2AqglinF+jjkUx7ACMmvEyNecNkRpXUVRa50NPt/qQFMLleDZAZul Ct5DLA9SMVLPM0MmA0nY95KXKZZQonofDo6r8nfcyzHgPX/cGsNL4bJHiAcDeQn9nH8EOdkL9Jx EyC1tsfJgL2NCq6FUrZ4/3sDUzVWyceEoqhTU+8jgi2yNkMvc9iWMXFIx5Iku+QKq9B4bFfd9Oq tVWo6dbIOcUoCTVFxAGUCUfqQexk/dXxM5i8K98nYqP4JHRj91I8DSoHHe5J4LZU5ZqYhBo5D+S wDxoMnZqTuB1CHy1zhV8ctJlU4hMlWbo5/9PDv6HVgOTt8mDP1yhw2u3mu3G2QuIxqlehI1TIwZ L891kcg== X-Google-Smtp-Source: AGHT+IEkH48jxAjPmiEs0V1xdB1+qZh5Jetyjq3/Ap+Rl/OUN1o0Eg/cerOxzkAbgtRzEPBpAjOIVw== X-Received: by 2002:a7b:c4c9:0:b0:453:bf1:8895 with SMTP id 5b1f17b1804b1-4530bf18a02mr23985445e9.5.1749564396855; Tue, 10 Jun 2025 07:06:36 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:36 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:51 +0200 Subject: [PATCH v6 13/17] drm/msm/dpu: Consistently use u32 instead of uint32_t Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-13-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1621; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Ez4rm6PFGrlujB66CVWxeGwNOdP1q/LlPEEBuX2j8C8=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvKYX8JuZ1utyAFUJbhgbb79o5eUdq4TvxK1 hFfk9Ce+16JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7ygAKCRDBN2bmhouD 19NHEACKFn9KQdCuFYHuUiAx1SJj6eWYi2vMCctzJy0GkaTeERePkDCenqfQWHqMJqqGadJIt01 beXorV+bpdEiyCuukJ2gh16oYGdLswG4iyUIlqD35bMqNv6OXQgHA+AfRoq44t/QPJwL4yu4eQU UjdTG+5B2AyD8RfNX8FfdUaOh5PPOjyvgcWeGxf4m7ZFNVOB2ar33N9nvwLupa9ecRX6z9wRchB 6RTSdwwUn4kc7pwnOn3Ei0eorgR+VreMbzEi6sXDkOYJ5Ghat71CissNbX7lSBqofFjyBdMXMsY pgRx9IPqUbyVhI+4IpS0ntiYI/WysKbLt5dyD3HJMpb03iQZ8dDJqeBTGuquJ2YW6gwx/KSI5LI X/xL9Np6O5MesXjYg39F+DNK4SsyZE5HMRpNqP25BNWVH3fuRla3f36tS1Xswr6uWwajfsyal6G u1ksimaH4DA7MIgnq7CT3sThAqCMKuYiewP5+KHR6pw0DpijUS2cOiEmv7SQQOxktzlUrjdWvtO P4yEAIMQqRJpN5WK9Tzsdo6LUbLi+hYj6oX/M3W2ECeq1JNV2htKxnkAmiekL1uDnOkXuyl3Hlg 3yZvxfv5wQndm/A/+hk3LfZgnKLgnavxakOlW08NB+ZcCvgKVJLM0FecSicaxQZz8aHE5nfa7Ja ambj9gvO8vvfGDw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Linux coding style asks to use kernel types like u32 instead of uint32_t and code already has it in other places, so unify the remaining pieces. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- Changes in v6: 1. New patch --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a4b0fe0d9899b32141928f0b6a16503a49b3c27a..92f6c39eee3dc090bd957239e58= 793e5b0437548 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -323,8 +323,8 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, struct dpu_plane_state *pstate, const struct msm_format *format) { struct dpu_hw_mixer *lm =3D mixer->hw_lm; - uint32_t blend_op; - uint32_t fg_alpha, bg_alpha; + u32 blend_op; + u32 fg_alpha, bg_alpha; =20 fg_alpha =3D pstate->base.alpha >> 8; bg_alpha =3D 0xff - fg_alpha; @@ -402,7 +402,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, struct dpu_hw_stage_cfg *stage_cfg ) { - uint32_t lm_idx; + u32 lm_idx; enum dpu_sspp sspp_idx; struct drm_plane_state *state; =20 @@ -442,8 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, struct dpu_plane_state *pstate =3D NULL; const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; - - uint32_t lm_idx; + u32 lm_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); =20 --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E263C2DCBF1 for ; Tue, 10 Jun 2025 14:06:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564403; cv=none; b=lcnzSPAwnwr08NW0aUrkGAUvY4JBzIpDQQilkJKVPWafJousyzg0WupeL/qIcOyPEvhhHxUuIm89QhzgpkWkOxpGPEXGmx94YPvkmjakfvxOWqzwHfdJf3WhQc5hf5dcrOF5l1v5658Ili4PtzdyIRDcu2+KKkHaR6I5kcIp61U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564403; c=relaxed/simple; bh=B37GRMruOX+ZSyC96p19lfWnZVPySg5VUvTqpflIprM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=meXm6o/AkbPeHQeO4/mO2q8JxJiJlviAd+DZqgHB2xKJJSodQCmL9z4sm3L3lvQr8m+Z1XphDIjxxJ0u3SD67uBDAF4SxvWK7u4A/Adj5xosnJM3ojZ5JmQigpzEOegL54S3qoWJReOd8MdhbnETjeE3+8l3nTpHZ57hpW0RS/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cmv+J8s7; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cmv+J8s7" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-453079c1e2eso1113935e9.3 for ; Tue, 10 Jun 2025 07:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564399; x=1750169199; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n82J7xKXmpUjRKj7zBCcVyEW4JwAUsZ8BkHyrQ3/GMg=; b=cmv+J8s7b4DL49yqwFlRZ4skhXwqDVbKJryzN9LR9u8bNm9APVEYDQ7NyizTfr3weP 0CxoYqHLKq2BDLVkVeIiHYSKuVXaXBuXp7xjhzVv/FdyB/SV8TFNKSP9oDiobSCowUTR phbISPcrF/UcS8fXz8sjUuNi00Vm7pwY9i3Eqw0be87UVlKFAH1AF0bvWvj7iy0058dn YAEa8egGNwssBFQPgRIx0AzTv3e3y7mO/RHz1Rfrya8KvWSYLdsguFbVsdDXrP1Egp5j Nhs+hm+Ur23EcawblzmZ5YZL221SOVE72BWUr1+oXGENUnhQYTE732IdPID95kiC4Sge ui8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564399; x=1750169199; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n82J7xKXmpUjRKj7zBCcVyEW4JwAUsZ8BkHyrQ3/GMg=; b=fUws6tjjZzh4UQ9jB2IRQ/qgX9UANUAFNWRWby3EafD/GGOpd8Zo4Vxon511ntYgCk zlXdR/AEs6e9O6YRFBBspHwiLyBuigrbdY1UxIiR6M9VLG03whxOBT22QOdHPobOXh4c KiE/OXttuysC0+tiOCghNiFm0Z7bCAhN6Ciu3cOjnEuvV/IljZqKxwjp0fr/H3MJadfr oyJJSimt0vuNm3VKO+Iz5OizwDxVVdBcgQRXi/MihybiYHYzzbkfggyIx6/svoSNcT56 ySIRa1MOf413/km999rGzlBvJHErU71r2DNtu9cwIny/jxShU62O52pkX6yggEZFIBHu w+Zw== X-Forwarded-Encrypted: i=1; AJvYcCWT7im4cPP9/2sQdacZTDvdgOJOrbk9GLKehhLSUL7E5af6+Cb10JZu9O6kKMAp9zgvXNlzEQF7DJsKLrk=@vger.kernel.org X-Gm-Message-State: AOJu0Yzt9w8r8amrXwMQ8aX6n+niDQXVyRtzMkKc7c+ntJ1IIJCEZWTF Ey/x+EQI1ITpROnorEsBgWQcse7aISw2Epjna7c/0b6O9H807ZO/5Lk3tXselCfomI0= X-Gm-Gg: ASbGnctL0y3gQrnhvjTvnvoYPK2S+EVy2cmeBd6DbqT2Nf7EPeXpqQuEHyhcjboiid7 sVWzFWCjXKiiALmC/+X/NkiKiDm848QPHmeQYC0dVPvBnllm6nYA+2Qqtb7PWGB0e/318IC7C0p VVfkjkCvNZZXcR+UAsMlG5ljWUaVcMdT17wdzDvdR+sTf1m3OGoAu+YFIX3WfW6LSCV1uOouB5S ntTP600mK7eAjzA84Eu2Wpf5hLLtx5LFDnFAMjhVd/juOIe+CVsurktRql8/x2NwqKvGu7RQfxj T2YErUpIWOIqhyKjNDJDXkjWlN+VpLRx7NzB6QoQjukzZB2VJOdjgYAfR7UVEDYp+9f+I0UROjF 4jVXLAA== X-Google-Smtp-Source: AGHT+IG/dBTylLygyD2mPbuxdE/ELraLT0KX1851OeZv3cweWndw3S/3EbupdYYae7LTZf5icINklg== X-Received: by 2002:a05:600c:1e02:b0:439:88bb:d00b with SMTP id 5b1f17b1804b1-4529abc31c1mr59950945e9.5.1749564399005; Tue, 10 Jun 2025 07:06:39 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:38 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:52 +0200 Subject: [PATCH v6 14/17] drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-14-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7947; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=B37GRMruOX+ZSyC96p19lfWnZVPySg5VUvTqpflIprM=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvL7xck0GNYEedf7be2lVr7C90maScpLeaRp XR4GjkJK1yJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7ywAKCRDBN2bmhouD 12gEEACEHHrURLT7ce5ukBw9rVKVSFrrkZt53yHh19ZSi1KTTidp07cRCb6eeHzUR+vH6PXhuRf jeMRljCTZxREf0yuBAsE015l/M/HmvCG8HyWVqnuZ5HN6aMpjBc/XXW+tIvquI3uuz9wvCiCHED 2jkG2XFu5pkRzADKBgOzF82FoV9AbaTFh1tCcv3tgKx9qoJyavtkhwI1rdwR7Iu70SdJpmK0n13 H+w4potU8b1pGuvfHTFGbcQvfZZpQeKNMvVanVCUPJWDNVfQk4mK+LENGVYMGcp7j1d+Juxil+w 477KkhIq8Xv9KSE7Hlaf4IbW5t3hCRWlqXrH6dQjLt2Sjr7yH4a+M7bLieN06lj/9uh+LzCnl0h 9DACq86Aw1Cm4/vU/7rJ3F6Mr/npccB+utjxzhKjpGENjebIInqLCOLRXaWun4pQ7XF9pxqsXnb 1F8N7eU9oOX3XxF3ALtjH2cRvu+LiQC5cAjI0Cd7e8tmW5HrkttMhmNBxj7EF4DpKbc7pgfZWqs yeCkuJunafQzktagMr9+0iNFbEDxZPMQch8pF0g0rUxkFRaMCsuz2Oyb0GTr2lb5GBB2aMRdLjl zDU9wL6t9G4Au0j9bslgnhYvKzDiWNtPj6I7k9VG/AeJ5vKjd+rHTUyFytCkFrGCpfZu/R6DDip P4L1S9YifI2YAqg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register differences and new implementations of setup_alpha_out(), setup_border_color() and setup_blend_config(). Notable changes in v6: Correct fg_alpha shift on new DPU, pointed out by Abel Vesas. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v6: 1. Checkpatch: CHECK: Prefer kernel type 'u32' over 'uint32_t' 2. Fix for fg_alpha shift (Abel Vesa). Changes in v4: 1. Lowercase hex, use spaces for define indentation 2. _dpu_crtc_setup_blend_cfg(): pass mdss_ver instead of ctl Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 23 ++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++= ++-- 2 files changed, 97 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 92f6c39eee3dc090bd957239e58793e5b0437548..5e986640c8ce5b49d0ce2f91cc4= 7f677a2e3f061 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -320,14 +320,22 @@ static bool dpu_crtc_get_scanout_position(struct drm_= crtc *crtc, } =20 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, const struct msm_format *format) + struct dpu_plane_state *pstate, + const struct msm_format *format, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_mixer *lm =3D mixer->hw_lm; u32 blend_op; - u32 fg_alpha, bg_alpha; + u32 fg_alpha, bg_alpha, max_alpha; =20 - fg_alpha =3D pstate->base.alpha >> 8; - bg_alpha =3D 0xff - fg_alpha; + if (mdss_ver->core_major_ver < 12) { + max_alpha =3D 0xff; + fg_alpha =3D pstate->base.alpha >> 8; + } else { + max_alpha =3D 0x3ff; + fg_alpha =3D pstate->base.alpha >> 6; + } + bg_alpha =3D max_alpha - fg_alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || @@ -337,7 +345,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -348,7 +356,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, /* coverage blending */ blend_op =3D DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | @@ -481,7 +489,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 /* blend config update */ for (lm_idx =3D 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format, + ctl->mdss_ver); =20 if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode =3D 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..f220a68e138cb9e7c88194e53e4= 7391de7ed04f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -19,12 +19,20 @@ =20 /* These register are offset to mixer base + stage base */ #define LM_BLEND0_OP 0x00 + +/* =3D v12 DPU */ +#define LM_BORDER_COLOR_0_V12 0x1c +#define LM_BORDER_COLOR_1_V12 0x20 + +/* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_CONST_ALPHA_V12 0x08 #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_m= ixer *ctx, } } =20 +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + + if (border_en) { + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12, + (color->color_0 & 0x3ff) | + ((color->color_1 & 0x3ff) << 16)); + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12, + (color->color_2 & 0x3ff) | + ((color->color_3 & 0x3ff) << 16)); + } +} + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) { dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alph= a(struct dpu_hw_mixer *ctx DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 +static void +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, + u32 stage, u32 fg_alpha, + u32 bg_alpha, u32 blend_op) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int stage_off; + u32 const_alpha; + + if (stage =3D=3D DPU_STAGE_BASE) + return; + + stage_off =3D _stage_offset(ctx, stage); + if (WARN_ON(stage_off < 0)) + return; + + const_alpha =3D (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); +} + static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer= *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } =20 +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx, + uint32_t mixer_op_mode) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int op_mode, stages, stage_off, i; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return; + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (WARN_ON(stage_off < 0)) + return; + + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */ + op_mode =3D DPU_REG_READ(c, LM_BLEND0_OP + stage_off); + if (mixer_op_mode & BIT(i)) + op_mode |=3D BIT(30); + else + op_mode &=3D ~BIT(30); + + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode); + } +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device= *dev, c->idx =3D cfg->id; c->cap =3D cfg; c->ops.setup_mixer_out =3D dpu_hw_lm_setup_out; - if (mdss_ver->core_major_ver >=3D 4) + if (mdss_ver->core_major_ver >=3D 12) + c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a_v12; + else if (mdss_ver->core_major_ver >=3D 4) c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a; else c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config; - c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; - c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + if (mdss_ver->core_major_ver < 12) { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + } else { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; + } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; c->ops.collect_misr =3D dpu_hw_lm_collect_misr; =20 --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6689E2DFA32 for ; Tue, 10 Jun 2025 14:06:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564407; cv=none; b=gE8yhikWxPNBpjY79RliD8/pqO8N2WHeUQsajZcqkoutQnUQ6jNkL1xsqhuWkQiznVOc1ylbuupgVoXnK7aCpITtJ0NLVyIU2H8BspZ1yQt1rC6AuVXBNnS1gfBg+e//TgPUZYOF4m66HgZZEc5Bl6ahaM3wdRGuR41Bm7J3Tqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564407; c=relaxed/simple; bh=PDdJg5qIS7HbPoHRu893zZjvEEa3IuzpHJO/F1Hc654=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kCEdJkfF5dBBOb0AVVYk+03LP9xpGtHDcNkWXHanT5Q7MWkavkQXdTJnOb2j7smJoUOgGZVKhw9zZaeaBEeoOk48psQhj3l5oef1ckmBKQdfiaGa+4RvaHv/ItIdDEfsUShizGVQiW/iYCfHSfvDVHB+lPkteyMZ2SVf/cYZbho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RcDSFZZ6; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RcDSFZZ6" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3a4e575db1aso720817f8f.2 for ; Tue, 10 Jun 2025 07:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564403; x=1750169203; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CBcl3mtlA2qXlHBtwB5KJDW+hrhCZib9hqqSTtK3hgY=; b=RcDSFZZ6/ofukSezyhLNCbJJo9hQ0K9PoWRV5rSrBw2rknL7BW/5s1mCmc8Ng/ANKh TtUpMkKmTEkbNga9EUeKT7kyxDZOs3TwRMIo1CW8t8oZ+d4riwGw1HVJW0lH/f6Z4o9b 1odq8cdbIumSEH8GoWONZ8qpP8wujdCuieDfg16AaQBfqke+iIr+WI2lLEP0W7flpY4B Wyw/eeL1ic5qvYgdnxJCE1O66Vio24/JA75pxgPeX07meZUemNd2VmR/pAw6SKbpU+L8 4JUGaa02yX78lZFgvp8SMdHQ5L3R4r6V76jWIVRyLkC0fMTqzJrHOJ/S++c7qPTZK7Qj VX/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564403; x=1750169203; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CBcl3mtlA2qXlHBtwB5KJDW+hrhCZib9hqqSTtK3hgY=; b=b92cmtuOEukfZWPffpVa6UO7RjJzxxF35Gi4ugPM57C59aGrurRlYPqMQM7PesYTsO Y6blEoP2DAOoSKpM65Oo0ZgmNJ+wSuYZyR/DanMbdY8CyztRvFInIqqfRMdlfM96WTfE VDkNiOjkdjcd+7RQss8gyWTbMUXF58zOXBgn+FI9nW8UIWbgzgyn22XMGo0c2Xf1S8UU BaAtZ5JMjSgvUwgGXljuMd8WrPcUuqTsKxS1fsfD9FnxNoZ0Avik1Pztvjd2bwFyKBVg n5OeNe/VU60BVe5bOCLIRvSAu0QIn2lsKyjiz7d0BcCRMxRYVZqBC7tIhVcFkLhqRUkr 5VAg== X-Forwarded-Encrypted: i=1; AJvYcCVINTz4za2j8i2PjtmdOUuUn1xHJb3eXMkK2gKlYWmHnWrnOU7UC61Q/kwR6qZZy6W6vPmdgNq2ZLCvbXs=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6fcWjlyTXdZ+MOJ7KELLBSRwU689fIgzoPvooY55x1FyZeRT7 4JGVU5pzYjI94xAqtFnEi62NB7wvzAoySRi+7b0CmINGQBEszEWTYbgybSgCCAbzZ7o= X-Gm-Gg: ASbGncuzdU6wim+saoqIoUwy1ZE8tqlWq75XOKx+owDqOUOEHg6fe4VuTWora8yIJI0 v7NvhM26Xxn2nmiXwm7EcIo3ZCb22Rn3hEulS5PX7D2o4HE06I+19n3uGjwLdeCsB/Gfv6n8JPT 9JIlip3pd2zWGlmVZDtc1YZthljVB6UuFEhKMXO8s41vTbAkU5MUCBJelLQAcp0YR7qEjRvPsiM s4grXxp6HpbbQtkbRUGtaY47ux0Zh4IYukkRCHeyRpt/jdDwtrn3zd38B2m2vvyt2LzFNLnY7BW hdS/h6XvAVle3tF5hlr7qmybx7TCUfXgf0iim8uIi10iVoECD4bwsUd8AwnM0ypFQaWz6krfaUA n23wrSQ== X-Google-Smtp-Source: AGHT+IFnue5hc35VVNgvb+VArzqO/xMlK9wQa6Q2rScaAFY6GDOjKfFaMoYtpeOxRfR6atMZBXHMzQ== X-Received: by 2002:a5d:5f8b:0:b0:3a4:e0e1:8dc8 with SMTP id ffacd0b85a97d-3a53319cb6emr4791148f8f.9.1749564401173; Tue, 10 Jun 2025 07:06:41 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:40 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:53 +0200 Subject: [PATCH v6 15/17] drm/msm/dpu: Implement CTL_PIPE_ACTIVE for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-15-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6580; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=PDdJg5qIS7HbPoHRu893zZjvEEa3IuzpHJO/F1Hc654=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvMj11z6OwjHQNIAPJQ3fXNkq2xWlp9svl9k 1pofTOhOXOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7zAAKCRDBN2bmhouD 1/mRD/9fsunALr5xCqYqRm1+udEXhJyuzA6VBVaxqH36ReMkUZmNkTtGNZ5l5Bkv1AXIaRw98aT xStOZ0TJ1wpjKwGkcOnYZ1ocBgKQabXSYrGe/bMRcrkLW96WcvZrzKXsaZz1uMiCn9HKUh/ZhrI UleqjsoasJPBeWWkWFgbeWUgriFkpxpQy9vw3M9Q6oMFjlzPlqiNEssXcZMZpQWIlJD40XPQl7o 92G2z5hfXZn5XQWtstlQzp01i5+2pvLONcDjvfbAptVVhPHXkMqleVJsMCjr21b9UbDtTE3IomF hewtTpeGEE5ADFDtmqB20bb85WUvqPYksxzlQHRGhx++xNdJ/DCVv0SOL/KHOt8BdE+nL7zv+90 qaC9z7ywNg3NM449nP7Bv3TDEfd/R4bUc/9KctsX2EFAv0VME/OdkzML5/czCqRBcSEAcA3PBz2 M8nXXk+9kloa+Sd2w87pbKQToYTfmhL37mVvsDaTFW1xdc8HJXUfbGcmHJYmuCe65/GjBFpFFz1 2mV3fKYv4C3pQ04PiNwl2kA14e/blcPmzLdNbsqpRTFmCv0PcvWoF5dR3x0PsoIMT9mni2bAo30 HjtvO14oNWMPN975mal2ojmvqppLb2o5dCUXDjHyiv0luugrGYODx0epiMGNCkx0bI+Z7g9quHF VkNSkYypmckAJlQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for selective activation of pipes, which replaces earlier dpu_hw_ctl_setup_blendstage() code path for newer devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex 2. Add Dmitry's tag Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 29 +++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 8 ++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 5e986640c8ce5b49d0ce2f91cc47f677a2e3f061..50897de0ab55c2d8dc2e6547b9f= 3a033a3ca9b45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -453,8 +453,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crt= c *crtc, u32 lm_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); + DECLARE_BITMAP(active_pipes, SSPP_MAX); =20 memset(active_fetch, 0, sizeof(active_fetch)); + memset(active_pipes, 0, sizeof(active_pipes)); drm_atomic_crtc_for_each_plane(plane, crtc) { state =3D plane->state; if (!state) @@ -472,6 +474,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, bg_alpha_enable =3D true; =20 set_bit(pstate->pipe.sspp->idx, active_fetch); + set_bit(pstate->pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -480,6 +483,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 if (pstate->r_pipe.sspp) { set_bit(pstate->r_pipe.sspp->idx, active_fetch); + set_bit(pstate->r_pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -503,6 +507,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, active_fetch); =20 + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, active_pipes); + _dpu_crtc_program_lm_output_roi(crtc); } =20 @@ -529,6 +536,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].lm_ctl); if (mixer[i].lm_ctl->ops.set_active_fetch_pipes) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); + if (mixer[i].lm_ctl->ops.set_active_pipes) + mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); } =20 /* initialize stage cfg */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index c0ed110a7d30fa1282676e3ae4c9f1316a3a3bf1..a52d5a74759ed9b1b12a0f00ee2= 417d9ee37fef9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2197,6 +2197,9 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) =20 if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); + + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, NULL); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index fe4fdfb8774b176fb024d76dc0bd269d9736d226..4299e94351d5e5371a86608f5ec= 1246f0cbe4290 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -42,6 +42,7 @@ #define CTL_INTF_FLUSH 0x110 #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 +#define CTL_PIPE_ACTIVE 0x12c #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -681,6 +682,9 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); =20 + if (ctx->ops.set_active_pipes) + ctx->ops.set_active_pipes(ctx, NULL); + if (cfg->intf) { intf_active =3D DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &=3D ~BIT(cfg->intf - INTF_0); @@ -737,6 +741,23 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct d= pu_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_ctl *ctx, + unsigned long *active_pipes) +{ + int i; + u32 val =3D 0; + + if (active_pipes) { + for (i =3D 0; i < SSPP_MAX; i++) { + if (test_bit(i, active_pipes) && + fetch_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(fetch_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -800,8 +821,12 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *= dev, c->ops.trigger_pending =3D dpu_hw_ctl_trigger_pending; c->ops.reset =3D dpu_hw_ctl_reset_control; c->ops.wait_reset_status =3D dpu_hw_ctl_wait_reset_status; - c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; - c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + if (mdss_ver->core_major_ver < 12) { + c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; + c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + } else { + c->ops.set_active_pipes =3D dpu_hw_ctl_set_active_pipes; + } c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; if (mdss_ver->core_major_ver >=3D 7) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 9cd9959682c21cc1c6d8d14b8fb377deb33cc10d..ca8f34ff3964c1adaaacdd3f0a6= 0572da53870e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -258,6 +258,14 @@ struct dpu_hw_ctl_ops { =20 void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, unsigned long *fetch_active); + + /** + * Set active pipes attached to this CTL + * @ctx: ctl path ctx pointer + * @active_pipes: bitmap of enum dpu_sspp + */ + void (*set_active_pipes)(struct dpu_hw_ctl *ctx, + unsigned long *active_pipes); }; =20 /** --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18A2B2DFA3E for ; Tue, 10 Jun 2025 14:06:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564407; cv=none; b=JeUDFOf47mGgu5Y3KE6JWkelxfKqeEv+CUHtaGvbs67Mhf3leu/y/ZC8VxrqdGUOGbWlL2kgkwTXKe0Iv6KkHBV+hbr0t8TuLSCrEnilVVANhbx0PdPXPfTLyMfFlMrfpjVD5+nwS8As8ctG035/jbehtAKuARGhDVGyyinOjXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564407; c=relaxed/simple; bh=D+6Yu1/EgiQrBj2bZZNEmXKI+PQQyM35XpJ4x7Iqr54=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dcjEkkoeb7nxnkw589On5dxbKqc1w1JNWpccxUlK+lfUrCllPYmkNg7CANX+8dNeFWdG2dL0j7yVZwzSZJrEyrjTZh3pMebM/Qvw9R34lR+Yr+lg0aGr+J91CweEixxSCPIVI8tFtQJujUz7WrJ5bhA7ed0MuQ6ryjIDvBKURYg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=R9NjmJB2; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="R9NjmJB2" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3a4ef05f631so521543f8f.3 for ; Tue, 10 Jun 2025 07:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564403; x=1750169203; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sYIOQ6ZhlTG9wMKDyOzgztxEyR0t1ek8t/vwdap4x2k=; b=R9NjmJB292d6ok5k14qqieQBHJCegYlefiSLQfU6RctHhr0piyhVvQdybxx5yY233y /lB74mXtZ41zJ2DMa+utyfQw5e3bmw7l5qdsB7O3m8ac+VzC48NgOnu+kQgdePP0DHkh VjwcQ1s0N4Wg39vMJPkS2KJ28DTCYkUV+fkPN4g3/FuyLHTvY3aUbJ/klxtq/tzrSvf1 3k7YhE3ooSRzr4w2BdaE3Vz2wJPfSOf9GpCXmuslw8kZdwL5g+DgrbKzPMz5YZ88jskV UKh3ukMokUjoshdWejbpOhODRxeQF/9EQYe0WzZ2S0O6vECfM+gklYX33+8NB9GDgBBq u1Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564403; x=1750169203; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sYIOQ6ZhlTG9wMKDyOzgztxEyR0t1ek8t/vwdap4x2k=; b=Vliziuk+fbg45vL6j1dB6HGZaTSAjBLOdpfDTkR7GWmKtC4RsQwYR8qJy3t6M7984G ACGB4uwOnSyMlwk/K3SQKnGk9Qq4Ba3qSRS7vmWSbPRHpUhE1aSSDypqV1KV/XQyDaiU sWT+vyxc+CkJPF7f7RstYNTxFj2r/O26KcBSbzzl0XvJ+n0klQpzj4GKkf68lVbkMfFw +BO3iX/7kxg8dpggXgeFBOb0ZYKjmkr9gOGKBg8QwEwOgrC7TVyhgDQt1lifgfxep4wb O76PvUVqWojKqOVZ9xsTq1ZOIPR5gBope5JGlnPIuzom295yYt8qIRkKC5zE7bEsz7D6 y+OQ== X-Forwarded-Encrypted: i=1; AJvYcCWdIE3g3htkFgZKzyJuKtUA0wMbYDVTH69aE172bWMbMPKWh0MyDFYFD66aJwm1w09YHHN3dQQxxNOjxvE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1bBhRh4FQn8ptzn7PHKrzOmQn0u/Eopa3oVRJU97hOUex1hqf oxJIPZsVjacpNJMMJBlX8yJZT3o+Pcjg73+klh8mGCI0FWY3zip2tL+AiVJ1tDrTEQA= X-Gm-Gg: ASbGnct+PsQKNWtAbXuaSjZL7HBh18z1tKlZLNlUgaSSoJHLkDTl8L5SO++OWBNj5M5 dfhugI5O29p0nG+V+EtTS9M4HPLV7LA9z24Ln+Ntvq1codL0350nio9rjVZZ3wLBWiW/MFOlvkC 78fshHI9K0W8f8mvf59MEydXhS29qlGpj5cTuHuf7uXngAsYkWeXI9R7qkDPJ501faMxdK09I9k IkCXLSCdFDwwFA4AtCy3cEMXVfUnaamiLuIxSRQJS7P2eloxXIeARtSbJanJDJJvRUaJJx7zGUa O8DRwfFytITF2csVsARLx1tUIxLGsGf3wcWzjf86xG/Ijud17F4BlJ1T6srcnlwxiNbcIwx5XL7 YGwMHOw== X-Google-Smtp-Source: AGHT+IHT1nwh85yBDchqkWMiLZ0pByvVB/iTMnjP5S3HM81ODNG7U8SEr0gUNOy+TqUfKgAPTun29w== X-Received: by 2002:a5d:5846:0:b0:3a5:1306:3c30 with SMTP id ffacd0b85a97d-3a531444827mr5350119f8f.0.1749564403279; Tue, 10 Jun 2025 07:06:43 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:42 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:54 +0200 Subject: [PATCH v6 16/17] drm/msm/dpu: Implement LM crossbar for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-16-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12930; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=D+6Yu1/EgiQrBj2bZZNEmXKI+PQQyM35XpJ4x7Iqr54=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvNgmBa8hSmi/qKSgRpVrSxd166fvypUWdIZ sxVBNS3TlSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7zQAKCRDBN2bmhouD 15t5D/9a1nGNxtL2npXUocH3rPH36MyC0LeWEb35oCDUB6CGSq5+FZkMKtk6GHxvax78xaY+D8M NlVjWpK3CARVe+bwml25r6dWkZTfZSXVWgDBnu77HOfWVNYv4FRQn1vZJRUNZPVBJnhH+PXZYBs EHz+OdZo24uzCOgDpZniJiAYTbq7+sIHMYz9HK8S0iMbfyesfR0lmyiHBmJhILkeSXwsGlmMvo9 3RX7wAF9UYOEUJbSIqbbeJ3F/ih0cbjiEG/sYChcvWgGBir/gGNM2BDhlsGodfclW3OPaoEzcU6 KQl+HnSMSjjPckaO20CY628GQ6/Hk7GrmnFLRmqiJ10BGkNaPW3XNG0LyBsDNINA7asCUSDYqis Y3NcadTDBMhviYKyfJ9q8W89KUE6y5aZbZQIywY2fBLqgTiOm3BOmHGmSxxMystRG+/R9wr3PYI ewTMtoPInYOY9prtKGbmK0ee8X2YEt0t1Vll6wK1kAeYKJd53urtceq5Lf2ib/HR3MJOtghOn/m CY7T8ElXCjWkxF9kG/6Kr4Z8ZW6PBdw0EUbdyOLhXJqPpgFHCWUlBdPHxQGikd7IouZeP0zJuaR /0IQhjT9dSKtIVrTGfiZR46GVRQzjxfEP4qE1SgENt1oIoVRi2Sp5+wu2LJuAnP3PHDtlGRU25J ixq2zs4QqSc4fcQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe rectangle to be programmed separately in blend stage. Implement support for this along with a new CTL_LAYER_ACTIVE register and setting the blend stage in layer mixer code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex 2. Add Dmitry's tag Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 27 +++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 9 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 126 ++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 18 ++++ 6 files changed, 201 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 50897de0ab55c2d8dc2e6547b9f3a033a3ca9b45..782aa86208d54cc28c5ad51215e= f458483ff3dfb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -525,6 +525,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; struct dpu_hw_stage_cfg stage_cfg; + DECLARE_BITMAP(active_lms, LM_MAX); int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -538,10 +539,14 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); if (mixer[i].lm_ctl->ops.set_active_pipes) mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); + + if (mixer[i].hw_lm->ops.clear_all_blendstages) + mixer[i].hw_lm->ops.clear_all_blendstages(mixer[i].hw_lm); } =20 /* initialize stage cfg */ memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(active_lms, 0, sizeof(active_lms)); =20 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); =20 @@ -555,13 +560,22 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) ctl->ops.update_pending_flush_mixer(ctl, mixer[i].hw_lm->idx); =20 + set_bit(lm->idx, active_lms); + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, active_lms); + DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n", mixer[i].hw_lm->idx - LM_0, mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 - ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + if (ctl->ops.setup_blendstage) + ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, + &stage_cfg); + + if (lm->ops.setup_blendstage) + lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx, + &stage_cfg); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index a52d5a74759ed9b1b12a0f00ee2417d9ee37fef9..078d3674ff411cf07614ae68889= d8d0147453d10 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2195,6 +2195,12 @@ static void dpu_encoder_helper_reset_mixers(struct d= pu_encoder_phys *phys_enc) if (ctl->ops.setup_blendstage) ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); =20 + if (hw_mixer[i]->ops.clear_all_blendstages) + hw_mixer[i]->ops.clear_all_blendstages(hw_mixer[i]); + + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, NULL); + if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 4299e94351d5e5371a86608f5ec1246f0cbe4290..ac834db2e4c16cfd2053f9761c4= 9d91a02bcffa6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -43,6 +43,7 @@ #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 #define CTL_PIPE_ACTIVE 0x12c +#define CTL_LAYER_ACTIVE 0x130 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -65,6 +66,8 @@ static const u32 fetch_tbl[SSPP_MAX] =3D {CTL_INVALID_BIT= , 16, 17, 18, 19, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5}; =20 +static const u32 lm_tbl[LM_MAX] =3D {CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5, 6,= 7}; + static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, enum dpu_lm lm) { @@ -677,7 +680,11 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw= _ctl *ctx, merge3d_active); } =20 - dpu_hw_ctl_clear_all_blendstages(ctx); + if (ctx->ops.clear_all_blendstages) + ctx->ops.clear_all_blendstages(ctx); + + if (ctx->ops.set_active_lms) + ctx->ops.set_active_lms(ctx, NULL); =20 if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); @@ -758,6 +765,23 @@ static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_= ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_lms(struct dpu_hw_ctl *ctx, + unsigned long *active_lms) +{ + int i; + u32 val =3D 0; + + if (active_lms) { + for (i =3D LM_0; i < LM_MAX; i++) { + if (test_bit(i, active_lms) && + lm_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(lm_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_LAYER_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -826,6 +850,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; } else { c->ops.set_active_pipes =3D dpu_hw_ctl_set_active_pipes; + c->ops.set_active_lms =3D dpu_hw_ctl_set_active_lms; } c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index ca8f34ff3964c1adaaacdd3f0a60572da53870e1..15931b22ec941bcf53b62783327= 36524bc16aa12 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -266,6 +266,15 @@ struct dpu_hw_ctl_ops { */ void (*set_active_pipes)(struct dpu_hw_ctl *ctx, unsigned long *active_pipes); + + /** + * Set active layer mixers attached to this CTL + * @ctx: ctl path ctx pointer + * @active_lms: bitmap of enum dpu_lm + */ + void (*set_active_lms)(struct dpu_hw_ctl *ctx, + unsigned long *active_lms); + }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index f220a68e138cb9e7c88194e53e47391de7ed04f7..e8a76d5192c230fd64d748634ca= 8574a59aac02c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -28,11 +28,19 @@ #define LM_FG_COLOR_FILL_XY 0x14 =20 /* >=3D v12 DPU */ +#define LM_BG_SRC_SEL_V12 0x14 +#define LM_BG_SRC_SEL_V12_RESET_VALUE 0x0000c0c0 #define LM_BORDER_COLOR_0_V12 0x1c #define LM_BORDER_COLOR_1_V12 0x20 =20 /* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_FG_SRC_SEL_V12 0x04 #define LM_BLEND0_CONST_ALPHA_V12 0x08 +#define LM_FG_COLOR_FILL_COLOR_0_V12 0x0c +#define LM_FG_COLOR_FILL_COLOR_1_V12 0x10 +#define LM_FG_COLOR_FILL_SIZE_V12 0x14 +#define LM_FG_COLOR_FILL_XY_V12 0x18 + #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -215,6 +223,122 @@ static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_= mixer *ctx, } } =20 +static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg, + int pipes_per_stage, u32 *value) +{ + int i; + u32 pipe_type =3D 0, pipe_id =3D 0, rec_id =3D 0; + u32 src_sel[PIPES_PER_STAGE]; + + *value =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + if (!stage_cfg || !pipes_per_stage) + return 0; + + for (i =3D 0; i < pipes_per_stage; i++) { + enum dpu_sspp pipe =3D stage_cfg->stage[stage][i]; + enum dpu_sspp_multirect_index rect_index =3D stage_cfg->multirect_index[= stage][i]; + + src_sel[i] =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + + if (!pipe) + continue; + + /* translate pipe data to SWI pipe_type, pipe_id */ + if (pipe >=3D SSPP_DMA0 && pipe <=3D SSPP_DMA5) { + pipe_type =3D 0; + pipe_id =3D pipe - SSPP_DMA0; + } else if (pipe >=3D SSPP_VIG0 && pipe <=3D SSPP_VIG3) { + pipe_type =3D 1; + pipe_id =3D pipe - SSPP_VIG0; + } else { + DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe); + return -EINVAL; + } + + /* translate rec data to SWI rec_id */ + if (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSPP_R= ECT_0) { + rec_id =3D 0; + } else if (rect_index =3D=3D DPU_SSPP_RECT_1) { + rec_id =3D 1; + } else { + DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index); + rec_id =3D 0; + } + + /* calculate SWI value for rec-0 and rec-1 and store it temporary buffer= */ + src_sel[i] =3D (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe= _id & 0xf)); + } + + /* calculate final SWI register value for rec-0 and rec-1 */ + *value =3D 0; + for (i =3D 0; i < pipes_per_stage; i++) + *value |=3D src_sel[i] << (i * 8); + + return 0; +} + +static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_l= m lm, + struct dpu_hw_stage_cfg *stage_cfg) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, ret, stages, stage_off, pipes_per_stage; + u32 value; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->cap->features)) + pipes_per_stage =3D PIPES_PER_STAGE; + else + pipes_per_stage =3D 1; + + /* + * When stage configuration is empty, we can enable the + * border color by setting the corresponding LAYER_ACTIVE bit + * and un-staging all the pipes from the layer mixer. + */ + if (!stage_cfg) + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + ret =3D _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value); + if (ret) + return ret; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value); + } + + return 0; +} + +static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, stages, stage_off; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, + LM_BG_SRC_SEL_V12_RESET_VALUE); + } + + return 0; +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -257,6 +381,8 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *= dev, c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; } else { c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_blendstage =3D dpu_hw_lm_setup_blendstage; + c->ops.clear_all_blendstages =3D dpu_hw_lm_clear_all_blendstages; c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.h index fff1156add683fec8ce6785e7fe1d769d0de3fe0..1b9ecd082d7fd72b07008787e1c= aea968ed23376 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -11,6 +11,7 @@ #include "dpu_hw_util.h" =20 struct dpu_hw_mixer; +struct dpu_hw_stage_cfg; =20 struct dpu_hw_mixer_cfg { u32 out_width; @@ -48,6 +49,23 @@ struct dpu_hw_lm_ops { */ void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); =20 + /** + * Clear layer mixer to pipe configuration + * @ctx : mixer ctx pointer + * Returns: 0 on success or -error + */ + int (*clear_all_blendstages)(struct dpu_hw_mixer *ctx); + + /** + * Configure layer mixer to pipe configuration + * @ctx : mixer ctx pointer + * @lm : layer mixer enumeration + * @stage_cfg : blend stage configuration + * Returns: 0 on success or -error + */ + int (*setup_blendstage)(struct dpu_hw_mixer *ctx, enum dpu_lm lm, + struct dpu_hw_stage_cfg *stage_cfg); + /** * setup_border_color : enable/disable border color */ --=20 2.45.2 From nobody Sat Oct 11 12:06:59 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D8122DFA4B for ; Tue, 10 Jun 2025 14:06:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564409; cv=none; b=O6VcI8Wd0yKiPNAGsAbJWw7zQwkCI5YqZ56qryK9ohJEShsshW4fU58Jf8o84xLomPY47XcMioOWMEiFTa7zMOL8oY61k620yfX4/EwoOTQts474kbCwuJxsfZOl2ImaVtQS9nR0KZwk59KRRlHevNkqZchT4cz7u7oJNX6kw5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749564409; c=relaxed/simple; bh=nJt4ADbxIA14pqN4XsVTOJSsLTO3c7LveRnmHeFCRAk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RoEAvpF5eEaNjZs4WgxoaSZhYDXJg0VmXAZZAYIsOyYEHWvRWNq3cWKK4Mx28B6j0btBnKRUaqQUqxbwvlpIeM8Rl+PECEK21i5kKwiTZ8dCZwj/bmm9JTRBEnOJez3kuY/G9baSQByHZr/qR/BwY1sKR1c0YM79f6LX3n+h5Yk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RftT+IgS; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RftT+IgS" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3a528e301b0so728822f8f.1 for ; Tue, 10 Jun 2025 07:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749564406; x=1750169206; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qlA118QQRrQcU4/5ozkHrMeNhT8icrM9d6BUqE0LJLY=; b=RftT+IgSl5mNW2d1kS+b2viEnsIaUSqOag3iDX3bkTMjXbw5XQlHTlEm6BNgEOl4cZ 0mD0dngwkY/5Awp+1WN8UAQ2wTp9MdPmquVZxjMfh8VWJrgMzNbFL+bFctRR9uKt+YaB Y7H9h8LpbYoMjR2OUoxz3C8d/eXK7DuymcAcLGoREJWBXKzL8YJ/E51/YXHwFgSTXm9P Q4vqUrlWWsKYpgaaYILuutw+FW7yf+80aXvMsQNcE2c/5Gxtrsc9/FjAUhQweAUZkdEo MnZlqxxfboSLIsvdOQ3OqD5qzrmjjbR+VOnk926DPIAbL3iL9ILRBlCFVoEnF8IKj9CC TJqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749564406; x=1750169206; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qlA118QQRrQcU4/5ozkHrMeNhT8icrM9d6BUqE0LJLY=; b=pgqEwVB6SOBN0GzdH3WkMuRFLK6YNt6KfZZuTvnDLQL0a2BvGdAufJr8WgtTY6rynv wTNcGCwiQSTAyiinhtykv/m7ueFeJ36Fd0u9DUDELGGKNg6m20ORVi3pfrWqo1HxpC8y l0asPMW0Dhmccp9RQ+kd2BLlNR7krRMTwjsJtSihZOZwPKU7c81hkrJojRYIjcBUgHu0 cZLbLGZKOqF7p8F7LE54mvN8TSFwiQ5UC0CSXPLyCWVyC1/wlgspuiIvDtvXYSVc2les 2+2MDg4cGpZvZCDebPp6+RkBWO8piaNK8K/t4rUyFLKViLtpV2Wvrdj6eLytLTuTb56L gP3Q== X-Forwarded-Encrypted: i=1; AJvYcCUusTbvjOkV8nHVJ7Uc+O28CT7rxcLOauSTxszhEGcT1X3naBPacJRG+7U3C88aA1trTJ19MbHhXkgpBf0=@vger.kernel.org X-Gm-Message-State: AOJu0Yx/t6La4RIDgG3CirOmNB8rN9UuiliPyo44jHvH25ADPNd9NRGs SoAJNY9gEfinDp787y6AHKhwNE7U84Du0zM13p6OHpqA7M0CGTxRN+uB9eDk2+CSvoA= X-Gm-Gg: ASbGncuyNJwB9LMMhRu4tsKp4JwlciUQiuZQXqv178Y/CRUzjnaXLirBK9LEjUkNJhi /lZIMWJWaHo9/HtLv0It9cn25NQpKaHI3LStHFj6HbuwKYJQwXbxqhzqzZmc29qBPHZzAtdPGWF 2NRfZOthoDEmpd/5o5nlQcwzXtPwS2XJDeeTD9pjmlt2bq6/0lRb6wMeTWq5+ZAtloK+UJAPsad w46FOAObvTdVpE1htCAYxU0AHcaY8g4rEHWfWuoGbyNLArgsYMKEgGSz4E6y3jQ004XOIkvNlns ccNx6DFG2vCJKN3Gj8BbFop1iCVWsshlJBpqwREyl7oqmMZWQeNeZJyiNGZIRHSZqzLM63ShrOk eE8BxSw== X-Google-Smtp-Source: AGHT+IGZufr1wfq+dLRw6f57n5SqOmq2e/nG1YhjXmidlB/YolNYy0WUiexT/5w6foFwU+TjOpZmVg== X-Received: by 2002:a05:6000:4025:b0:3a4:eed9:755b with SMTP id ffacd0b85a97d-3a53315704amr4817877f8f.4.1749564405478; Tue, 10 Jun 2025 07:06:45 -0700 (PDT) Received: from [192.168.1.29] ([178.197.223.125]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53244df06sm12734469f8f.69.2025.06.10.07.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 07:06:44 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 10 Jun 2025 16:05:55 +0200 Subject: [PATCH v6 17/17] drm/msm/mdss: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250610-b4-sm8750-display-v6-17-ee633e3ddbff@linaro.org> References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> In-Reply-To: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3191; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=nJt4ADbxIA14pqN4XsVTOJSsLTO3c7LveRnmHeFCRAk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoSDvOS1VuxS+qjJR9cY8w+d68w2FoCLMiuaNbl Acm4SL6luOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEg7zgAKCRDBN2bmhouD 12VFD/9b4y4SPbBdpJWKma1Ib+xxUjq/d53O3/XX7Zg9z9Q9ZASk2PUqdH4+xyEVg2VvgoI/+kQ OGsv/K6u2k0Gs3Ds+3wY3cLt4H9UMtg1w7YXwmrAHQ1OPcV26IVI4ElYdQ4ndTE+L/orPArl6tf u9KG9SYyFymRkL56lkp5xCcEAyXW8UMqukmErlYoQmYZTuB0d1iEr9flR3cEajYx7Lq44vHlpy8 NdRNpMp9Woo6YbVM1/6nUybbGg9+xJHj397RbhyiSBHQwEHEr0Z0MNZisHK1keT0y5vSFRq6G4W Qv95WQYzV9GPA6SDPI3ZejcDEEeNiKfD1uCsJ8NghZX1Yg0L4BBkps0pCH/sNMLawYL1c6ocfMN xSMsySC3UtQCNUVrjtWaFTJ9ITDsO9QjLtW5dS13faVv0FpLmNAj8jlRkTRaWGhCNNGAXywVMnc thjOIpRnaZ9u04+LP+XQoDDtyo1AN8gJC8uDDuGGTbgmSJBDQKkOmQiik2n8esKuLUv4zPQmbRp o4mCDNGOOjR7QPO1ZDv6QEzPvOLSJrH9IMnsnypxcwuPk1sLp7iAqvNHehlW/y19sAeHyCGpJGA ULlLUL2LR/tOc3jUBQ84mxTYbBWJA8YqYoZO0juqHwhLzpDORNrz99V4RHwSrDkVE91vQ3hj5Ej uifo1hwE+1rhi+w== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mdss.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 709979fcfab6062c0f316f7655823e888638bfea..422da5ebf802676afbfc5f242a5= a84e6d488dda1 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss= *msm_mdss) } } =20 +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) +{ + const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); +} + #define MDSS_HW_MAJ_MIN \ (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) =20 @@ -339,6 +357,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case UBWC_4_3: msm_mdss_setup_ubwc_dec_40(msm_mdss); break; + case UBWC_5_0: + msm_mdss_setup_ubwc_dec_50(msm_mdss); + break; default: dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", msm_mdss->mdss_data->ubwc_dec_version); @@ -732,6 +753,17 @@ static const struct msm_mdss_data sm8550_data =3D { .reg_bus_bw =3D 57000, }; =20 +static const struct msm_mdss_data sm8750_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ + .highest_bank_bit =3D 3, + .macrotile_mode =3D true, + .reg_bus_bw =3D 57000, +}; + static const struct msm_mdss_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, @@ -767,6 +799,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, + { .compatible =3D "qcom,sm8750-mdss", .data =3D &sm8750_data}, { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, {} }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 14dc53704314558841ee1fe08d93309fd2233812..dd0160c6ba1a297cea5b87cd8b0= 3895b2aa08213 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -22,6 +22,7 @@ struct msm_mdss_data { #define UBWC_3_0 0x30000000 #define UBWC_4_0 0x40000000 #define UBWC_4_3 0x40030000 +#define UBWC_5_0 0x50000000 =20 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); =20 --=20 2.45.2