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charset="utf-8" Add four Broadcom Cable Modem SoCs to the compatibility list. Signed-off-by: Jim Quinlan Acked-by: Conor Dooley Reviewed-by: Florian Fainelli --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index c4f9674e8695..5a7b0ed9464d 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -15,6 +15,9 @@ properties: - enum: - brcm,bcm2711-pcie # The Raspberry Pi 4 - brcm,bcm2712-pcie # Raspberry Pi 5 + - brcm,bcm3162-pcie # Broadcom DOCSIS 4.0 CMTS w/ 64b ARM + - brcm,bcm3390-pcie # Broadcom DOCSIS 3.1 CM w/ 32b ARM + - brcm,bcm3392-pcie # Broadcom DOCSIS 3.1 CM w/ 64b ARM - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - brcm,bcm7216-pcie # Broadcom 7216 Arm @@ -23,6 +26,7 @@ properties: - brcm,bcm7435-pcie # Broadcom 7435 MIPs - brcm,bcm7445-pcie # Broadcom 7445 Arm - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5 + - brcm,bcm33940-pcie # Broadcom DOCSIS 4.0 CM w/ 64b ARM =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sat Feb 7 23:21:52 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2188022126D for ; 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Mon, 09 Jun 2025 15:17:23 -0700 (PDT) Received: from stbsrv-and-02.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23603078d65sm59290415ad.5.2025.06.09.15.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jun 2025 15:17:23 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/3] PCI: brcmstb: Refactor indication of SSC status Date: Mon, 9 Jun 2025 18:17:05 -0400 Message-ID: <20250609221710.10315-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609221710.10315-1-james.quinlan@broadcom.com> References: <20250609221710.10315-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of using a bool to track the Spread Spectrum Clocking (SSC), just use a string constant since that will be the end result anyway. The motivation for this change is underscored by a subsequent commit that adds Cable Modem SoCs to the driver. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index 92887b394eb4..db7872cda960 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1320,8 +1320,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) { struct device *dev =3D pcie->dev; void __iomem *base =3D pcie->base; + const char *ssc_str =3D "(!SSC)"; u16 nlw, cls, lnksta; - bool ssc_good =3D false; int ret, i; =20 /* Limit the generation if specified */ @@ -1357,7 +1357,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) if (pcie->ssc) { ret =3D brcm_pcie_set_ssc(pcie); if (ret =3D=3D 0) - ssc_good =3D true; + ssc_str =3D "(SSC)"; else dev_err(dev, "failed attempt to enter ssc mode\n"); } @@ -1366,8 +1366,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pci= e) cls =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); nlw =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); dev_info(dev, "link up, %s x%u %s\n", - pci_speed_string(pcie_link_speed[cls]), nlw, - ssc_good ? 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Mon, 09 Jun 2025 15:17:26 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/3] PCI: brcmstb: Enable Broadcom Cable Modem SoCs Date: Mon, 9 Jun 2025 18:17:06 -0400 Message-ID: <20250609221710.10315-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250609221710.10315-1-james.quinlan@broadcom.com> References: <20250609221710.10315-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Broadcom's Cable Modem (CM) group also uses this PCIe driver as it shares the PCIe HW core with the STB group. Make the modifications to enable the CM SoCs. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 186 +++++++++++++++++++++----- 1 file changed, 152 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller= /pcie-brcmstb.c index db7872cda960..e25dbcdc56a7 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -51,6 +51,9 @@ #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8 #define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8 =20 +#define PCIE_RC_DL_PDL_CONTROL_4 0x1010 +#define PCIE_RC_DL_PDL_CONTROL_4_NPH_FC_INIT_MASK 0xff000000 + #define PCIE_RC_DL_MDIO_ADDR 0x1100 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 @@ -60,6 +63,7 @@ #define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff =20 #define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK 0x20 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 @@ -170,6 +174,7 @@ /* MSI target addresses */ #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL +#define BRCM_MSI_TARGET_ADDR_FOR_CM 0xfffffffffcULL =20 /* MDIO registers */ #define MDIO_PORT0 0x0 @@ -223,13 +228,23 @@ enum { enum pcie_soc_base { GENERIC, BCM2711, + BCM3162, + BCM3392, + BCM3390, BCM4908, BCM7278, BCM7425, BCM7435, BCM7712, + BCM33940, }; =20 +/* + * BCM3390 CM chip actually conforms to STB design, so it + * is not present in the macro below. + */ +#define IS_CM_SOC(t) ((t) =3D=3D BCM3162 || (t) =3D=3D BCM33940 || (t) =3D= =3D BCM3392) + struct inbound_win { u64 size; u64 pci_offset; @@ -757,6 +772,9 @@ static int brcm_pcie_bridge_sw_init_set_generic(struct = brcm_pcie *pcie, u32 val) u32 shift =3D RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; int ret =3D 0; =20 + if (IS_CM_SOC(pcie->cfg->soc_base)) + return 0; + if (pcie->bridge_reset) { if (val) ret =3D reset_control_assert(pcie->bridge_reset); @@ -891,13 +909,13 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pci= e *pcie, struct inbound_win *b =3D b_begin; =20 /* - * STB chips beside 7712 disable the first inbound window default. - * Rather being mapped to system memory it is mapped to the - * internal registers of the SoC. This feature is deprecated, has - * security considerations, and is not implemented in our modern - * SoCs. + * STB chips beside CM chips and 7712 disable the first inbound + * window default. Rather being mapped to system memory it is + * mapped to the internal registers of the SoC. This feature is + * deprecated, has security considerations, and is not + * implemented in our modern SoCs. */ - if (pcie->cfg->soc_base !=3D BCM7712) + if (pcie->cfg->soc_base !=3D BCM7712 && !IS_CM_SOC(pcie->cfg->soc_base)) add_inbound_win(b++, &n, 0, 0, 0); =20 resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -905,16 +923,32 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pci= e *pcie, u64 cpu_start =3D entry->res->start; =20 size =3D resource_size(entry->res); + + /* + * For BCM3390, single dma-range may map to the SoC + * register space in [0xf0000000..0xffffffff]. If present, + * this has to be assigned to inbound window #1, as this is + * the only one that HW allows to map to register space. + * So if we see this range, place it in inbound_wins[1] + * which is previously disabled (zeroed out). + */ + if (pcie->cfg->soc_base =3D=3D BCM3390 && cpu_start >=3D 0xf0000000 + && cpu_start + size - 1 <=3D 0xffffffff) { + add_inbound_win(b_begin, &n, size, cpu_start, pcie_start); + n--; + continue; + } + tot_size +=3D size; if (pcie_start < lowest_pcie_addr) lowest_pcie_addr =3D pcie_start; /* - * 7712 and newer chips may have many BARs, with each - * offering a non-overlapping viewport to system memory. - * That being said, each BARs size must still be a power of - * two. + * 7712, CM, and newer chips may have many inbound windows, + * with each offering a non-overlapping viewport to system + * memory. That being said, each window's size must still + * be a power of two. */ - if (pcie->cfg->soc_base =3D=3D BCM7712) + if (pcie->cfg->soc_base =3D=3D BCM7712 || IS_CM_SOC(pcie->cfg->soc_base)) add_inbound_win(b++, &n, size, cpu_start, pcie_start); =20 if (n > pcie->cfg->num_inbound_wins) @@ -927,11 +961,11 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pci= e *pcie, } =20 /* - * 7712 and newer chips do not have an internal memory mapping system - * that enables multiple memory controllers. As such, it can return - * now w/o doing special configuration. + * 7712, CM, and newer chips do not have an internal memory + * mapping system that enables multiple memory controllers. As + * such, it can return now w/o doing special configuration. */ - if (pcie->cfg->soc_base =3D=3D BCM7712) + if (pcie->cfg->soc_base =3D=3D BCM7712 || IS_CM_SOC(pcie->cfg->soc_base)) return n; =20 ret =3D of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", p= cie->memc_size, 1, @@ -1051,10 +1085,10 @@ static void set_inbound_win_registers(struct brcm_p= cie *pcie, /* * Most STB chips: * Do nothing. - * 7712: - * All of their BARs need to be set. + * 7712, CM: + * All of their inbound windows need to be set. */ - if (pcie->cfg->soc_base =3D=3D BCM7712) { + if (pcie->cfg->soc_base =3D=3D BCM7712 || IS_CM_SOC(pcie->cfg->soc_base)= ) { /* BUS remap register settings */ reg_offset =3D brcm_ubus_reg_offset(i); tmp =3D lower_32_bits(cpu_addr) & ~0xfff; @@ -1118,6 +1152,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) burst =3D 0x0; /* 128 bytes */ else if (pcie->cfg->soc_base =3D=3D BCM7278) burst =3D 0x3; /* 512 bytes */ + else if (pcie->cfg->soc_base =3D=3D BCM3162 || pcie->cfg->soc_base =3D=3D= BCM33940) + burst =3D 0x1; /* Encoding: 0=3D64, 1=3D128, 2=3DRsvd, 3=3DRsvd */ else burst =3D 0x2; /* 512 bytes */ =20 @@ -1144,18 +1180,20 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return -EINVAL; } =20 - tmp =3D readl(base + PCIE_MISC_MISC_CTRL); - for (memc =3D 0; memc < pcie->num_memc; memc++) { - u32 scb_size_val =3D ilog2(pcie->memc_size[memc]) - 15; - - if (memc =3D=3D 0) - u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); - else if (memc =3D=3D 1) - u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); - else if (memc =3D=3D 2) - u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2)); + if (!IS_CM_SOC(pcie->cfg->soc_base)) { + tmp =3D readl(base + PCIE_MISC_MISC_CTRL); + for (memc =3D 0; memc < pcie->num_memc; memc++) { + u32 scb_size_val =3D ilog2(pcie->memc_size[memc]) - 15; + + if (memc =3D=3D 0) + u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); + else if (memc =3D=3D 1) + u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); + else if (memc =3D=3D 2) + u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2)); + } + writel(tmp, base + PCIE_MISC_MISC_CTRL); } - writel(tmp, base + PCIE_MISC_MISC_CTRL); =20 /* * We ideally want the MSI target address to be located in the 32bit @@ -1164,8 +1202,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) * 4GB or when the inbound area is smaller than 4GB (taking into * account the rounding-up we're forced to perform). */ - if (inbound_wins[2].pci_offset >=3D SZ_4G || - (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) + if (IS_CM_SOC(pcie->cfg->soc_base)) + pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_FOR_CM; + else if (inbound_wins[2].pci_offset >=3D SZ_4G || + (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G) pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_LT_4GB; else pcie->msi_target_addr =3D BRCM_MSI_TARGET_ADDR_GT_4GB; @@ -1226,6 +1266,29 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); =20 + /* + * Relax read ordering for chip architectures using RBUS/SCB that + * use WiFi Runner offload (i.e. BCM3390) to avoid deadlock where + * reads are blocked by writes. + */ + if (pcie->cfg->soc_base =3D=3D BCM3390) { + tmp =3D readl(base + PCIE_MISC_MISC_CTRL); + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_IN_CPL_RO_MASK); + writel(tmp, base + PCIE_MISC_MISC_CTRL); + } + + /* + * The 3392 has a bug that requires the NP credit advertised by the + * MAC to be overwritten with 0x10 in bits 31:24 of the following + * register. + */ + if (pcie->cfg->soc_base =3D=3D BCM3392) { + tmp =3D readl(base + PCIE_RC_DL_PDL_CONTROL_4); + u32p_replace_bits(&tmp, 0x10, + PCIE_RC_DL_PDL_CONTROL_4_NPH_FC_INIT_MASK); + writel(tmp, base + PCIE_RC_DL_PDL_CONTROL_4); + } + if (pcie->cfg->post_setup) { ret =3D pcie->cfg->post_setup(pcie); if (ret < 0) @@ -1246,8 +1309,8 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie= *pcie) const unsigned int REG_OFFSET =3D PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us =3D 4000000; /* 4 seconds, our setting for L1SS */ =20 - /* 7712 does not have this (RGR1) timer */ - if (pcie->cfg->soc_base =3D=3D BCM7712) + /* CM and 7712 do not have this (RGR1) timer */ + if (IS_CM_SOC(pcie->cfg->soc_base) || pcie->cfg->soc_base =3D=3D BCM7712) return; =20 /* Each unit in timeout register is 1/216,000,000 seconds */ @@ -1354,7 +1417,10 @@ static int brcm_pcie_start_link(struct brcm_pcie *pc= ie) =20 brcm_config_clkreq(pcie); =20 - if (pcie->ssc) { + if (IS_CM_SOC(pcie->cfg->soc_base)) { + /* This driver does configure SSC for CM chips */ + ssc_str =3D ""; + } else if (pcie->ssc) { ret =3D brcm_pcie_set_ssc(pcie); if (ret =3D=3D 0) ssc_str =3D "(SSC)"; @@ -1715,6 +1781,14 @@ static const int pcie_offsets[] =3D { [PCIE_INTR2_CPU_BASE] =3D 0x4300, }; =20 +static const int pcie_offset_bcm3162[] =3D { + [RGR1_SW_INIT_1] =3D 0x9210, + [EXT_CFG_INDEX] =3D 0x9000, + [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4204, + [PCIE_INTR2_CPU_BASE] =3D 0x4300 +}; + static const int pcie_offsets_bcm7278[] =3D { [RGR1_SW_INIT_1] =3D 0xc010, [EXT_CFG_INDEX] =3D 0x9000, @@ -1739,6 +1813,14 @@ static const int pcie_offsets_bcm7712[] =3D { [PCIE_INTR2_CPU_BASE] =3D 0x4400, }; =20 +static const int pcie_offset_bcm33940[] =3D { + [RGR1_SW_INIT_1] =3D 0x9210, + [EXT_CFG_INDEX] =3D 0x9000, + [EXT_CFG_DATA] =3D 0x9004, + [PCIE_HARD_DEBUG] =3D 0x4304, + [PCIE_INTR2_CPU_BASE] =3D 0x4400 +}; + static const struct pcie_cfg_data generic_cfg =3D { .offsets =3D pcie_offsets, .soc_base =3D GENERIC, @@ -1765,6 +1847,30 @@ static const struct pcie_cfg_data bcm2712_cfg =3D { .num_inbound_wins =3D 10, }; =20 +static const struct pcie_cfg_data bcm3162_cfg =3D { + .offsets =3D pcie_offset_bcm3162, + .soc_base =3D BCM3162, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, +}; + +static const struct pcie_cfg_data bcm3392_cfg =3D { + .offsets =3D pcie_offset_bcm33940, + .soc_base =3D BCM3392, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 10, +}; + +static const struct pcie_cfg_data bcm3390_cfg =3D { + .offsets =3D pcie_offsets, + .soc_base =3D BCM3390, + .perst_set =3D brcm_pcie_perst_set_generic, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 3, +}; + static const struct pcie_cfg_data bcm4908_cfg =3D { .offsets =3D pcie_offsets, .soc_base =3D BCM4908, @@ -1814,9 +1920,20 @@ static const struct pcie_cfg_data bcm7712_cfg =3D { .num_inbound_wins =3D 10, }; =20 +static const struct pcie_cfg_data bcm33940_cfg =3D { + .offsets =3D pcie_offset_bcm33940, + .soc_base =3D BCM33940, + .perst_set =3D brcm_pcie_perst_set_7278, + .bridge_sw_init_set =3D brcm_pcie_bridge_sw_init_set_generic, + .num_inbound_wins =3D 10, +}; + static const struct of_device_id brcm_pcie_match[] =3D { { .compatible =3D "brcm,bcm2711-pcie", .data =3D &bcm2711_cfg }, { .compatible =3D "brcm,bcm2712-pcie", .data =3D &bcm2712_cfg }, + { .compatible =3D "brcm,bcm3162-pcie", .data =3D &bcm3162_cfg }, + { .compatible =3D "brcm,bcm3390-pcie", .data =3D &bcm3390_cfg }, + { .compatible =3D "brcm,bcm3392-pcie", .data =3D &bcm3392_cfg }, { .compatible =3D "brcm,bcm4908-pcie", .data =3D &bcm4908_cfg }, { .compatible =3D "brcm,bcm7211-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7216-pcie", .data =3D &bcm7216_cfg }, @@ -1825,6 +1942,7 @@ static const struct of_device_id brcm_pcie_match[] = =3D { { .compatible =3D "brcm,bcm7435-pcie", .data =3D &bcm7435_cfg }, { .compatible =3D "brcm,bcm7445-pcie", .data =3D &generic_cfg }, { .compatible =3D "brcm,bcm7712-pcie", .data =3D &bcm7712_cfg }, + { .compatible =3D "brcm,bcm33940-pcie", .data =3D &bcm33940_cfg }, {}, }; =20 --=20 2.43.0