From nobody Sun Feb 8 03:30:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80726223DC7; Mon, 9 Jun 2025 21:55:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749506108; cv=none; b=aGi7gRSnnPm0SDMyuw4dyeOr6j1LzFTL77UxLUTf8LHBDuPhMBPVWnN+XyxqRYOBapJzdOe12ktWFjFMtsuP6aT0fidqXwUVQUuMjDJTWmD6GtNyGfUIlKnzGmVZVYgrmFsmm23CeYotvTXeo2BDKN7wxmwiYZAanMBgvmQG/OY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749506108; c=relaxed/simple; bh=ttAImCmMUiZa42qLOdbBpMNlTYXYgg2QF6vqlW3LybQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cDOuJDKu9AJNDm88B4YlBsBaXV54cv4SY6OusoqTxWc/CsbH9WnpEWsZqmDG4KEkXctpyVXOsWTsUuLq8x5KJyrR4vRhqc1x5JSJO/Us7UQfkCs+moYw6mlhSW1/6E2XQWYSNIaOAB3BLUIYDWu5TW4Z7PLPJhPNEfnwA26Jgeg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HqUaVlSL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HqUaVlSL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC08EC4CEF3; Mon, 9 Jun 2025 21:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749506108; bh=ttAImCmMUiZa42qLOdbBpMNlTYXYgg2QF6vqlW3LybQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HqUaVlSLGqox2BCS7PcJFaI0NkOu9scsN9bc2w3cHU2Cc1wDoPbAOsftEVticUhef PHLgu8FkDXyfSYJ1qgiC4jk43RnAIGm/ANwYAswUrHfa0je+0qmbGM90sw02ColpUy 2G/R86fCPuk3kYRBzHA1sV9Fblkm1BQu9VcvqdWvHo6HxLgkw2YTtUoJ6qXvxrPLzh TZbWosMnrEmzmYpXwKt1v0tcevkQpGiP8Fw8S/O9C9E4+/kRpYYdgWlHKUOtgaVNMq Lw61cIczqH3wHl7R4GgntLgX7fku/esLaquvhMLyj56PiDhcQiaLVXpUq/sm1gNZZb qYnR8eSxjbHhg== From: "Rob Herring (Arm)" Date: Mon, 09 Jun 2025 16:54:56 -0500 Subject: [PATCH 1/2] arm64: dts: lg: Refactor common LG1312 and LG1313 parts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250609-dt-lg-fixes-v1-1-e210e797c2d7@kernel.org> References: <20250609-dt-lg-fixes-v1-0-e210e797c2d7@kernel.org> In-Reply-To: <20250609-dt-lg-fixes-v1-0-e210e797c2d7@kernel.org> To: soc@kernel.org, Chanho Min , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15-dev The LG1312 and LG1313 DT are almost identical with the exception of the ethernet node. Refactor the common parts into a separate .dtsi file and include it. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/lg/lg1312.dtsi | 324 +--------------------------------= --- arch/arm64/boot/dts/lg/lg1313.dtsi | 324 +--------------------------------= --- arch/arm64/boot/dts/lg/lg131x.dtsi | 333 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 337 insertions(+), 644 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg= 1312.dtsi index bb0bcc6875dc..e83fdc92621e 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -5,103 +5,12 @@ * Copyright (C) 2016, LG Electronics */ =20 -#include #include =20 -/ { - #address-cells =3D <2>; - #size-cells =3D <2>; +#include "lg131x.dtsi" =20 +/ { compatible =3D "lge,lg1312"; - interrupt-parent =3D <&gic>; - - cpus { - #address-cells =3D <2>; - #size-cells =3D <0>; - - cpu0: cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x0>; - next-level-cache =3D <&L2_0>; - }; - cpu1: cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x1>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - cpu2: cpu@2 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x2>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - cpu3: cpu@3 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x3>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - L2_0: l2-cache0 { - compatible =3D "cache"; - cache-level =3D <2>; - cache-unified; - }; - }; - - psci { - compatible =3D "arm,psci-0.2", "arm,psci"; - method =3D "smc"; - cpu_suspend =3D <0x84000001>; - cpu_off =3D <0x84000002>; - cpu_on =3D <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells =3D <3>; - compatible =3D "arm,gic-400"; - interrupt-controller; - reg =3D <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D , - , - , - ; - interrupt-affinity =3D <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells =3D <0>; - - compatible =3D "fixed-clock"; - clock-frequency =3D <198000000>; - clock-output-names =3D "BUSCLK"; - }; =20 soc { #address-cells =3D <2>; @@ -122,233 +31,4 @@ eth0: ethernet@c1b00000 { mac-address =3D [ 00 00 00 00 00 00 ]; }; }; - - amba { - #address-cells =3D <2>; - #size-cells =3D <1>; - - compatible =3D "simple-bus"; - interrupt-parent =3D <&gic>; - ranges; - - timers: timer@fd100000 { - compatible =3D "arm,sp804", "arm,primecell"; - reg =3D <0x0 0xfd100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>, <&clk_bus>; - clock-names =3D "timer0clk", "timer1clk", "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible =3D "arm,sp805", "arm,primecell"; - reg =3D <0x0 0xfd200000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "wdog_clk", "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe000000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - uart1: serial@fe100000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - uart2: serial@fe200000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe200000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - spi0: spi@fe800000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xfe800000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "sspclk", "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xfe900000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "sspclk", "apb_pclk"; - }; - dmac0: dma-controller@c1128000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0xc1128000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - #dma-cells =3D <1>; - }; - gpio0: gpio@fd400000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd400000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd410000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd420000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd430000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd440000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd450000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd460000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd470000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd480000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd490000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4a0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4b0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4c0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4d0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4e0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4f0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd500000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd510000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - }; }; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg= 1313.dtsi index c07d670bc465..92fa5694cad1 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -5,103 +5,12 @@ * Copyright (C) 2016, LG Electronics */ =20 -#include #include =20 -/ { - #address-cells =3D <2>; - #size-cells =3D <2>; +#include "lg131x.dtsi" =20 +/ { compatible =3D "lge,lg1313"; - interrupt-parent =3D <&gic>; - - cpus { - #address-cells =3D <2>; - #size-cells =3D <0>; - - cpu0: cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x0>; - next-level-cache =3D <&L2_0>; - }; - cpu1: cpu@1 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x1>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - cpu2: cpu@2 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x2>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - cpu3: cpu@3 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a53"; - reg =3D <0x0 0x3>; - enable-method =3D "psci"; - next-level-cache =3D <&L2_0>; - }; - L2_0: l2-cache0 { - compatible =3D "cache"; - cache-level =3D <2>; - cache-unified; - }; - }; - - psci { - compatible =3D "arm,psci-0.2", "arm,psci"; - method =3D "smc"; - cpu_suspend =3D <0x84000001>; - cpu_off =3D <0x84000002>; - cpu_on =3D <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells =3D <3>; - compatible =3D "arm,gic-400"; - interrupt-controller; - reg =3D <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D , - , - , - ; - interrupt-affinity =3D <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells =3D <0>; - - compatible =3D "fixed-clock"; - clock-frequency =3D <198000000>; - clock-output-names =3D "BUSCLK"; - }; =20 soc { #address-cells =3D <2>; @@ -122,233 +31,4 @@ eth0: ethernet@c3700000 { mac-address =3D [ 00 00 00 00 00 00 ]; }; }; - - amba { - #address-cells =3D <2>; - #size-cells =3D <1>; - - compatible =3D "simple-bus"; - interrupt-parent =3D <&gic>; - ranges; - - timers: timer@fd100000 { - compatible =3D "arm,sp804", "arm,primecell"; - reg =3D <0x0 0xfd100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>, <&clk_bus>; - clock-names =3D "timer0clk", "timer1clk", "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible =3D "arm,sp805", "arm,primecell"; - reg =3D <0x0 0xfd200000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "wdog_clk", "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe000000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - uart1: serial@fe100000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - uart2: serial@fe200000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xfe200000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - spi0: spi@fe800000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xfe800000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "sspclk", "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xfe900000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>, <&clk_bus>; - clock-names =3D "sspclk", "apb_pclk"; - }; - dmac0: dma-controller@c1128000 { - compatible =3D "arm,pl330", "arm,primecell"; - reg =3D <0x0 0xc1128000 0x1000>; - interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - #dma-cells =3D <1>; - }; - gpio0: gpio@fd400000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd400000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd410000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd420000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd430000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd440000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd450000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd460000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd470000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd480000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd490000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4a0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4b0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4c0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4d0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4e0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd4f0000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd500000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - status =3D "disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells =3D <2>; - compatible =3D "arm,pl061", "arm,primecell"; - gpio-controller; - reg =3D <0x0 0xfd510000 0x1000>; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; - }; - }; }; diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg= 131x.dtsi new file mode 100644 index 000000000000..dc4229bd9ebb --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg131x.dtsi @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for lg131x SoCs + * + * Copyright (C) 2016, LG Electronics + */ + +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + next-level-cache =3D <&L2_0>; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + }; + L2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-0.2", "arm,psci"; + method =3D "smc"; + cpu_suspend =3D <0x84000001>; + cpu_off =3D <0x84000002>; + cpu_on =3D <0x84000003>; + }; + + gic: interrupt-controller@c0001000 { + #interrupt-cells =3D <3>; + compatible =3D "arm,gic-400"; + interrupt-controller; + reg =3D <0x0 0xc0001000 0x1000>, + <0x0 0xc0002000 0x2000>, + <0x0 0xc0004000 0x2000>, + <0x0 0xc0006000 0x2000>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + clk_bus: clk_bus { + #clock-cells =3D <0>; + + compatible =3D "fixed-clock"; + clock-frequency =3D <198000000>; + clock-output-names =3D "BUSCLK"; + }; + + amba { + #address-cells =3D <2>; + #size-cells =3D <1>; + + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + timers: timer@fd100000 { + compatible =3D "arm,sp804", "arm,primecell"; + reg =3D <0x0 0xfd100000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>, <&clk_bus>; + clock-names =3D "timer0clk", "timer1clk", "apb_pclk"; + }; + wdog: watchdog@fd200000 { + compatible =3D "arm,sp805", "arm,primecell"; + reg =3D <0x0 0xfd200000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "wdog_clk", "apb_pclk"; + }; + uart0: serial@fe000000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe000000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + uart1: serial@fe100000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe100000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + uart2: serial@fe200000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe200000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + spi0: spi@fe800000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0xfe800000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; + }; + spi1: spi@fe900000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0xfe900000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "sspclk", "apb_pclk"; + }; + dmac0: dma-controller@c1128000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x0 0xc1128000 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + #dma-cells =3D <1>; + }; + gpio0: gpio@fd400000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd400000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio1: gpio@fd410000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd410000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio2: gpio@fd420000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd420000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio3: gpio@fd430000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd430000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + }; + gpio4: gpio@fd440000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd440000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio5: gpio@fd450000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd450000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio6: gpio@fd460000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd460000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio7: gpio@fd470000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd470000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio8: gpio@fd480000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd480000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio9: gpio@fd490000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd490000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio10: gpio@fd4a0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4a0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio11: gpio@fd4b0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4b0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + }; + gpio12: gpio@fd4c0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4c0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio13: gpio@fd4d0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4d0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio14: gpio@fd4e0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4e0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio15: gpio@fd4f0000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd4f0000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio16: gpio@fd500000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd500000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + status =3D "disabled"; + }; + gpio17: gpio@fd510000 { + #gpio-cells =3D <2>; + compatible =3D "arm,pl061", "arm,primecell"; + gpio-controller; + reg =3D <0x0 0xfd510000 0x1000>; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + }; + }; +}; --=20 2.47.2 From nobody Sun Feb 8 03:30:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7320A2248AB; Mon, 9 Jun 2025 21:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749506109; cv=none; b=B0fQfxkEzZCnpnAq/Rb6yPqitHTjw5W1ie9PXgbqe40O5sDi9Zg2hQbSa/4POTRF9gUU9SoFimkj/lKfnYqZ3rZIhiyW+FIVEP3DCYJy9BS+ex48CH0T9UqswmEkEYNqT3hOfuRHT4JMYdYmuIPbm1ubwP4eeiDjKkC6AS3+YL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749506109; c=relaxed/simple; bh=sFe34T4JjO0tAEnsFjcwuygXkVXQNdWJSnqO77GzWWo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qRg4h8057onc1P0GJd48Os2BVxFj+692roDaUksaiSHwR2AqvEfTtHvetI0ZmS/R7HqvFy/3gkrjoAYNxNxghAOvxpV4GZhyxJgESiQG0MWZV/r0Z+ae5El0sr7+gI2WPeZj1n6uvG7a82G+OJMyFQSCXJUQZYgc97liDpBdFuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o/rAG/5i; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o/rAG/5i" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D0CEC4CEED; Mon, 9 Jun 2025 21:55:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749506109; bh=sFe34T4JjO0tAEnsFjcwuygXkVXQNdWJSnqO77GzWWo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=o/rAG/5i/F3cxZt7Ep2Dw3ZU885oM6P0+eYjhhqobJan1bcBdUfzydkKF78XoKu3S rRn15rGPhLyornEE1hbZFu+2W3N3DwYmUlrocFEndjiOGWiCrHfpRwC01nfgcxaUt7 t/6FK0s0yv8nTh2Mf6JuIGyHTD28r0SQZu78xY8RNXFxfyfC6QWOst0Iu9PkiyVnfZ 1nkxDIpSz5Yytb9WuhpiZrQbQELFLnCt/Fq9C/81T5T1lePxTRZtREVzzymRN3lfZA 2gW1CTCCx6E3HLiy4luWd3TZoh6EveLRlGuNOr/kl8j8EdFWsoxumRzwbDhewe1lmR 9eeUM4tZ59a1A== From: "Rob Herring (Arm)" Date: Mon, 09 Jun 2025 16:54:57 -0500 Subject: [PATCH 2/2] arm64: dts: lg: Add missing PL011 "uartclk" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org> References: <20250609-dt-lg-fixes-v1-0-e210e797c2d7@kernel.org> In-Reply-To: <20250609-dt-lg-fixes-v1-0-e210e797c2d7@kernel.org> To: soc@kernel.org, Chanho Min , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15-dev The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The LG131x SoCs are missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) --- arch/arm64/boot/dts/lg/lg131x.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg= 131x.dtsi index dc4229bd9ebb..4cb1e4510897 100644 --- a/arch/arm64/boot/dts/lg/lg131x.dtsi +++ b/arch/arm64/boot/dts/lg/lg131x.dtsi @@ -128,24 +128,24 @@ uart0: serial@fe000000 { compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0x0 0xfe000000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; status =3D "disabled"; }; uart1: serial@fe100000 { compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0x0 0xfe100000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; status =3D "disabled"; }; uart2: serial@fe200000 { compatible =3D "arm,pl011", "arm,primecell"; reg =3D <0x0 0xfe200000 0x1000>; interrupts =3D ; - clocks =3D <&clk_bus>; - clock-names =3D "apb_pclk"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; status =3D "disabled"; }; spi0: spi@fe800000 { --=20 2.47.2