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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH 01/10] dt-bindings: arm: fsl: support Engicam MicroGEA BMM board Date: Sat, 7 Jun 2025 11:33:13 +0200 Message-ID: <20250607093342.2248695-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA BMM board based on the Engicam MicroGEA SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index d3b5e6923e41..5feb62611e53 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -769,6 +769,13 @@ properties: - const: dh,imx6ull-dhcor-som - const: fsl,imx6ull =20 + - description: i.MX6ULL Engicam MicroGEA SoM based boards + items: + - enum: + - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A1B220E6E4 for ; Sat, 7 Jun 2025 09:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288833; cv=none; b=nLe59AmwPqKtRy78wjLcIboABUuYw5riQfWyx8exEMtTAKIRX7URG5UxEqNPcznJI1wDitaOcYoG6AEQrchAwc9CKeFcYp5FrlaqokEt8gQynbQ6v8++eMD4dlOWweDkyuMeUMceddfITdyMAIu5MYAWdE36L59hQA+1OFlHpzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288833; c=relaxed/simple; bh=nlwe7h7r3/BITiv4q+dzdvB5lKnHkIgxhj7FM6I1jnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NWzKHSzm4Mpd9VZdR/wXdC5YO5iU0hHx7N4q9WkyHJg4J+OTWOKz3YJn6XrEbyGN7cjGftGZCQHYv5tR0HqnLLm77tTOmAkp68feKxLEUBq3ilreVddd6nXY3SK9EJ8O+CSXIjPDGL9pQjvc63L5zAnftZ8nIJDt4wlvF/Y/6Ho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Mnu60MMC; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Mnu60MMC" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-604f26055c6so7803950a12.1 for ; Sat, 07 Jun 2025 02:33:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749288830; x=1749893630; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cYXpxglNlRn6ZF9PKdL5/2uCcX5/hamtbwOWk6+JISM=; b=Mnu60MMC9Ew9JCQaXtCWIYBHvwD0Mq2bgrsRlstvDNk2aqNENCUjPwAch0TC0o7HAd lUdVbL5c1x6RS4w8Adg6TmCHOv2nAe/pa2MCmsSySUPfJOpiUPqnODpprsZHscYoe5sf 0RCqiDxbmT2+d7DJQeI8Zo8JfLG3MuM5g8OY0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749288830; x=1749893630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cYXpxglNlRn6ZF9PKdL5/2uCcX5/hamtbwOWk6+JISM=; b=XRo07knSMLZXkjLsiuIlEhijSO03agpCeLP40ESCUmFAkHPs7QFVGIWBsI4yao+zsv f8JTt4LvDbklekCSHh6g/HlqqwIWCb/44fc7JjLysIW0+C3d7PkuABj0FKLSgYiR0srF 07bqK/8+DHHplEeAfueX1h4ZA9aW3QwHqyah+SS1221BikwM+UPuyisWBPOoG0rkbz4E sT88hX4Q1teoTpqqjqGrX4JngDacdXTrh7FymVIHf7v0YY7/MaiAOeYjr1SnXkbtJa9U ZnkJhJQ7jCblKEyLRnI3+m6I+Vq7foe5Pe49ynDSdfRVyaZ2ULcEKJkiAaMTQAVMK3uJ aG2g== X-Gm-Message-State: AOJu0YzxwDZzzDxTcuEIJ1RcxzLge4HtGWZgMY+nvCUkbaN3KXROBKYD SoHFEGouIX7lVu6da7tbSU4olyg1TZYvut7u+do1x4JWY+kv7nKIKs57ST9W0Yhl5UJnYjg/AHF x6Mcb X-Gm-Gg: ASbGncuSOJafIqESM4uiUvL7JIHEvJ+rIxNMdK7R2cUIC62BNmcMqf2Uw8peIM8z+J5 7d7q4WIYETZUwJfRFdaKNoybrB1i0ph8ch+s+26ExlktqwzLuNLpqPnL1tQmAviaJnz3o7XyJUm sr6YKuqMlmFm6GVE20zAAhNztyHV6nCkWPOqrEsF41EMCoPONwdxeSxBoz4s6GmUN5V0ykv+Krv xchlN5Pb9l61BdotuR0Revcxq2mVUqRUWSyPvdit1LkkCWGHr3tCmp5eT4bvJwlcTeVpQMZ70kz YoK/AfJFIhkkv7pgyjvR+eIpGv1m5mTy4bwmF+DS7+JkjG90KFAwSaUfaYSxz0Xe1nX22D2H2Sz vMrXAz1G2VI59G0cUoAXnBREnB9wO3bnZOWjz1rVzZr1LAldHd5hf91Ts0grYwiQz6O7nqZV/HZ kXNPL004h8uPVjJ9o+YURjnfU= X-Google-Smtp-Source: AGHT+IFwrSoT/bg84mvJeB5tJBoerkyokpFv/ZBrKGOCSANMJJ0LsqpRieQ9b6Ay4j+aF5bsl8WiDw== X-Received: by 2002:a17:907:6ea6:b0:ad8:9ca4:af7c with SMTP id a640c23a62f3a-ade076350e8mr993166366b.17.1749288830301; Sat, 07 Jun 2025 02:33:50 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-95-99.retail.telecomitalia.it. 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charset="utf-8" Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi --- .../dts/nxp/imx/imx6ull-engicam-microgea.dtsi | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch= /arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi new file mode 100644 index 000000000000..8588e9ad7b8f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + + #include "imx6ull.dtsi" + + / { + compatible =3D "engicam,microgea-imx6ull", "fsl,imx6ull"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x20000000>; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet1>, <&pinctrl_phy_reset>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + local-mac-address =3D [00 04 9F 01 1B B9]; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <4000>; + reset-deassert-us =3D <4000>; + }; + }; +}; + +/* NAND */ +&gpmi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpmi_nand>; + nand-ecc-mode =3D "hw"; + nand-ecc-strength =3D <0>; + nand-ecc-step-size =3D <0>; + nand-on-flash-bbt; + status =3D "okay"; +}; + +&iomuxc { + + pinctrl_enet1: enet1grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins =3D < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_phy_reset: phy-resetgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD28D211261 for ; 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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:51 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/10] ARM: dts: imx6ul: support Engicam MicroGEA BMM board Date: Sat, 7 Jun 2025 11:33:15 +0200 Message-ID: <20250607093342.2248695-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA BMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-bmm.dts | 306 ++++++++++++++++++ 2 files changed, 307 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 8b3abe817e12..57f185198217 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -356,6 +356,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-pdk2.dtb \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ + imx6ull-engicam-microgea-bmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts new file mode 100644 index 000000000000..5030bcc3b690 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-bmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-bmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: sgtl5000@a { + compatible =3D "fsl,sgtl5000"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clock-names =3D "mclk"; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&iomuxc { + + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x11008 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x000b0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x000b0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x000b0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x000b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; + +&iomuxc_snvs { + + pinctrl_reg_usb1: regusb1grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_reg_ext_pwr: reg-ext-pwrgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x17059 + >; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&tsc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tsc>; + measure-delay-time =3D <0x9ffff>; + pre-charge-time =3D <0xfff>; + xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "host"; 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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:52 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , "Martin K. Petersen" , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/10] ARM: imx_v6_v7_defconfig: cleanup mxs_defconfig Date: Sat, 7 Jun 2025 11:33:16 +0200 Message-ID: <20250607093342.2248695-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generate imx_v6_v7_defconfig by doing: make imx_v6_v7_defconfig make savedefconfig cp defconfig arch/arm/configs/imx_v6_v7_defconfig No functional change. The goal here is to cleanup imx_v6_v7_defconfig file to make easier and cleaner the addition of new entries. Signed-off-by: Dario Binacchi --- arch/arm/configs/imx_v6_v7_defconfig | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 062c1eb8dd60..d40ca9edd264 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_RELAY=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy CONFIG_PERF_EVENTS=3Dy +CONFIG_KEXEC=3Dy CONFIG_ARCH_MULTI_V6=3Dy CONFIG_ARCH_MXC=3Dy CONFIG_SOC_IMX31=3Dy @@ -32,7 +33,6 @@ CONFIG_ARM_PSCI=3Dy CONFIG_HIGHMEM=3Dy CONFIG_ARCH_FORCE_MAX_ORDER=3D13 CONFIG_CMDLINE=3D"noinitrd console=3Dttymxc0,115200" -CONFIG_KEXEC=3Dy CONFIG_CPU_FREQ=3Dy CONFIG_CPU_FREQ_STAT=3Dy CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=3Dy @@ -129,7 +129,6 @@ CONFIG_CS89x0_PLATFORM=3Dy CONFIG_QCA7000_SPI=3Dm # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=3Dy -CONFIG_SMC911X=3Dy CONFIG_SMSC911X=3Dy # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_MICREL_PHY=3Dy @@ -153,9 +152,7 @@ CONFIG_MWIFIEX_PCIE=3Dm CONFIG_WL12XX=3Dm CONFIG_WL18XX=3Dm CONFIG_WLCORE_SDIO=3Dm -# CONFIG_WILINK_PLATFORM_DATA is not set CONFIG_INPUT_EVDEV=3Dy -CONFIG_INPUT_EVBUG=3Dm CONFIG_KEYBOARD_GPIO=3Dy CONFIG_KEYBOARD_SNVS_PWRKEY=3Dy CONFIG_KEYBOARD_IMX=3Dy @@ -190,9 +187,7 @@ CONFIG_SERIAL_IMX_CONSOLE=3Dy CONFIG_SERIAL_FSL_LPUART=3Dy CONFIG_SERIAL_FSL_LPUART_CONSOLE=3Dy CONFIG_SERIAL_DEV_BUS=3Dy -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=3Dy -CONFIG_I2C_MUX=3Dy CONFIG_I2C_MUX_GPIO=3Dy # CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_ALGOPCF=3Dm @@ -204,14 +199,9 @@ CONFIG_SPI_FSL_QUADSPI=3Dy CONFIG_SPI_GPIO=3Dy CONFIG_SPI_IMX=3Dy CONFIG_SPI_FSL_DSPI=3Dy -CONFIG_PINCTRL_IMX8MM=3Dy -CONFIG_PINCTRL_IMX8MN=3Dy -CONFIG_PINCTRL_IMX8MP=3Dy -CONFIG_PINCTRL_IMX8MQ=3Dy CONFIG_GPIO_SYSFS=3Dy CONFIG_GPIO_MXC=3Dy CONFIG_GPIO_SIOX=3Dm -CONFIG_GPIO_VF610=3Dy CONFIG_GPIO_MAX732X=3Dy CONFIG_GPIO_PCA953X=3Dy CONFIG_GPIO_PCA953X_IRQ=3Dy @@ -225,7 +215,6 @@ CONFIG_W1_SLAVE_THERM=3Dm CONFIG_POWER_RESET=3Dy CONFIG_POWER_RESET_SYSCON=3Dy CONFIG_POWER_RESET_SYSCON_POWEROFF=3Dy -CONFIG_POWER_SUPPLY=3Dy CONFIG_RN5T618_POWER=3Dm CONFIG_SENSORS_MC13783_ADC=3Dy CONFIG_SENSORS_GPIO_FAN=3Dy @@ -283,13 +272,13 @@ CONFIG_VIDEO_OV5645=3Dm CONFIG_VIDEO_ADV7180=3Dm CONFIG_IMX_IPUV3_CORE=3Dy CONFIG_DRM=3Dy -CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_MSM=3Dy CONFIG_DRM_PANEL_LVDS=3Dy -CONFIG_DRM_PANEL_SIMPLE=3Dy -CONFIG_DRM_PANEL_EDP=3Dy CONFIG_DRM_PANEL_SEIKO_43WVF1G=3Dy +CONFIG_DRM_PANEL_EDP=3Dy +CONFIG_DRM_PANEL_SIMPLE=3Dy CONFIG_DRM_DISPLAY_CONNECTOR=3Dy +CONFIG_DRM_I2C_NXP_TDA998X=3Dy CONFIG_DRM_LVDS_CODEC=3Dm CONFIG_DRM_SII902X=3Dy CONFIG_DRM_TI_TFP410=3Dy @@ -310,7 +299,6 @@ CONFIG_LCD_PLATFORM=3Dy CONFIG_BACKLIGHT_CLASS_DEVICE=3Dy CONFIG_BACKLIGHT_PWM=3Dy CONFIG_BACKLIGHT_GPIO=3Dy -CONFIG_FRAMEBUFFER_CONSOLE=3Dy CONFIG_LOGO=3Dy CONFIG_SOUND=3Dy CONFIG_SND=3Dy @@ -380,11 +368,8 @@ CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy -CONFIG_NEW_LEDS=3Dy -CONFIG_LEDS_CLASS=3Dy CONFIG_LEDS_GPIO=3Dy CONFIG_LEDS_PWM=3Dy -CONFIG_LEDS_TRIGGERS=3Dy CONFIG_LEDS_TRIGGER_TIMER=3Dy CONFIG_LEDS_TRIGGER_ONESHOT=3Dy CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy @@ -453,7 +438,6 @@ CONFIG_EXT3_FS_POSIX_ACL=3Dy CONFIG_EXT3_FS_SECURITY=3Dy CONFIG_QUOTA=3Dy CONFIG_QUOTA_NETLINK_INTERFACE=3Dy -# CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_AUTOFS_FS=3Dy CONFIG_FUSE_FS=3Dy CONFIG_ISO9660_FS=3Dm @@ -490,5 +474,4 @@ CONFIG_PRINTK_TIME=3Dy CONFIG_MAGIC_SYSRQ=3Dy CONFIG_DEBUG_FS=3Dy # CONFIG_SLUB_DEBUG is not set -# CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CEC215773 for ; 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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:54 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Eric Biggers , Fabio Estevam , "Martin K. Petersen" , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/10] ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER Date: Sat, 7 Jun 2025 11:33:17 +0200 Message-ID: <20250607093342.2248695-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA BMM board. Signed-off-by: Dario Binacchi --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index d40ca9edd264..917bc8a27794 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -180,6 +180,7 @@ CONFIG_TOUCHSCREEN_COLIBRI_VF50=3Dy CONFIG_INPUT_MISC=3Dy CONFIG_INPUT_MMA8450=3Dy CONFIG_INPUT_GPIO_BEEPER=3Dm +CONFIG_INPUT_PWM_BEEPER=3Dy CONFIG_SERIO_SERPORT=3Dm # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=3Dy --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5100921B908 for ; Sat, 7 Jun 2025 09:33:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288839; cv=none; b=UMELwxxK0ytZcqxYMwhKsB4N6U8geqW4MI/88I7Lyg7fT2ww/jmJNt0y+XZzVzo54jmuUBQm3i2ryta6HaG5SGarPsfRUZc4N7Tq1eFhbVfbG6zqIptFfD8X3SFdRpbwZTqcKTz8ieoBjM03WT4FtDhxZ6Za5mkBV1UEPZyq3Lg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288839; c=relaxed/simple; bh=hzT3vNgL1vWDpYVWZ4Vv9VCYguwOggONSy8Bpm6xvOg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HQjVBVRt2VQTCFRkjKg9v1lSg4PpDUBZfy98w9eD17ep3YrqmHLxoUm1bZlASQCQiOPIHYU5rIIMua+xcO09a3gjdOjb5DT3peKcAD1fn9Nprp6bHXvjNkrMCnBkyLjqVEgYHJotI+JgyDqLHPxFz4V6KnRdzKOoFzwuO9iIMAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=I1ejNc55; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="I1ejNc55" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-60179d8e65fso516959a12.0 for ; Sat, 07 Jun 2025 02:33:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749288836; x=1749893636; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5MR+dZbWYo4do6lj7ERY9jZ9tLxOFZiirseEEryjRVE=; b=I1ejNc55IVc7Cxdz5arB+XZ+Yp1SIwPmCSSjNtUbwEkHIQkPJuDemkUtG9Mc3VN1mc QikAM4LI8POOd4dUjueeX+NQX9MqECnR+Pzw0IaiMVbILvxEKN8snNH/ZPd0SG7qG+wG mXZmcptviJjR/lA979j4QieqTqkYo/ek0E2M8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749288836; x=1749893636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5MR+dZbWYo4do6lj7ERY9jZ9tLxOFZiirseEEryjRVE=; b=FkXlYvVxE/CAA+Q3mWd/4JUjvB3BIjpQ+rzj4KQ12YGUXP1nnoc4Eo1paINozafG7E Hm2jdfThTwtxiVwjD9Wi9nSc9nzZixiF7hv/9m8hUgAUgydjqx4vzNFqcmseMdikwput E5Pp/msRRAESxh59UVUpBMCldkICaFpU+qGpzFw/ZpEKGGrlDafKUMHhQo0Q5OE+jsCe laPBPMgv0PQUqj7vkicr8m7RmYRWrWsba2SPBEN+Dy0n8Lrqy7Qz99AWqJ6tBtGbldrL BynRpQTSxGCUTiZMKiT0rOnCUkK0KohdSKBl++I/EnoALtYmWU1SeVdK13Q5+dqzW2k2 FQ7A== X-Gm-Message-State: AOJu0YzgAny2mWicx8Omc1xFeUE8RTPUivLSA2bhcy2Ady1Hes3tyIL8 ZfmPFDV8sgIl0RuIpmRcEPrWMH7zLXA0QvUn8UadlzMOepx2j9u76lHwOKuxblUKL/seDHi+pfi uwbiI X-Gm-Gg: ASbGncu5IeWU3/a2531LVkpVAO5e3U7EKOphdYCBN00x9lYKicx9+vsCc/TokY74qhV GfanzPrQluNf/1UqdYh2cRhAjwRgUs3Mj3WR/AboZlZHucCFcuuG/gGVWma8241U7r4jL/cBMV7 +FObgQV70i0FbdPY65DWO5y9s8Ud7Wym9eis3XHW7/PDulNr9UEFznlmuz7SaluGH8tB3oLUFW5 nFan3sK8V5yFHrZOXpodoAh0TGKhMSiKZRyp6R4XLZu0wl6Z/QYX3Oh7/MNYw0NX2A/PJWW/d30 1RSfhH6qBkpkXzH8YNCwR3SMZxiYE96Tw4wyjRYF+EWzxvZlRgNh43GJ+Jc/XO4Gu+XC/xxlIks VKNZnuLIVJcEkHfXxJLctnA0ZNCGDP94+DSxSi3vME7gU5LctBrdLEhkeZNeDZaC8FR18tf79CW 7T/ELjhgfd9KZdrMGIVPvvmrg= X-Google-Smtp-Source: AGHT+IFlHwQClNktEW9rU11ODeYPn4LafvV12ThMJYdILr+sWuVhLFbv21t3KR4w5K99ahlUqfYzBw== X-Received: by 2002:a17:906:4fc7:b0:ad8:89c7:2735 with SMTP id a640c23a62f3a-ade1aa0fbaemr593115766b.58.1749288836475; Sat, 07 Jun 2025 02:33:56 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-95-99.retail.telecomitalia.it. [87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:56 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH 06/10] dt-bindings: arm: fsl: support Engicam MicroGEA RMM board Date: Sat, 7 Jun 2025 11:33:18 +0200 Message-ID: <20250607093342.2248695-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA RMM board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5feb62611e53..58492b1cd468 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull =20 --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBF7C220687 for ; Sat, 7 Jun 2025 09:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288841; cv=none; b=WaunQ/8gQQsxzRMp+8SoGHE4vXTJ1s+X7Cto3zS31/ibH0sivvSx9ULqDcpROXCvsBG3Uf0+6IJ354YgiV6qi8ZFEadjkcLkWMLcwaMIAtJheQidfEta9mm/AVLHPBnXEevAdrnpyhHQ5sF1Q9DC36C7beI5kDrwXYQRcvTiPDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288841; c=relaxed/simple; bh=QQVXB5zQ+KFi2GJWTIBvsasEYSKaxNKE8bJI/43qL0k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oV8VVscAetHjdK+SCKUut8Xdj+XU8Uwg2EBN4j00JB9ag/pi00apSs/I2ueR1/dyqbssYe1lmLlGVXs7ghno9jjmIZKlqtv3wC237yz327wVenpRTFexzj6HZKV+MMXXwBg7OIg5QlhK4aL8Wd26ITTt521WgjY0ZwJDxgrVEFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=cOnsFBtz; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="cOnsFBtz" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-606ddbda275so5264737a12.1 for ; Sat, 07 Jun 2025 02:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749288838; x=1749893638; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kWHmRwxHIl7SqIOMEN3OX1Ie9AcQJY6iSkcNImx/CKU=; b=cOnsFBtz3fMk5rzupHlpyy9oKZ8EBccagiAuNVMrpvqScRLn1TDjm2drZCMg9gzxzk AgzPpcpeCTjqBG5+0mmdOCtgAQRaC5vUi6/4pf0mB2fTf3cB5fFgirFBGKG5z7nxli1n Sb5zsR+jNcDfRQqiHBQ+AfFMFVv9P4a5mX4YY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749288838; x=1749893638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kWHmRwxHIl7SqIOMEN3OX1Ie9AcQJY6iSkcNImx/CKU=; b=hnYNhJuxFcHv6v9EXNIRrnRRTs79E8xofsXaEQdHV2R7PXQD3A+tuOlG+Dqfi45jaF oOAifQGdxVUAXEIRfbqObK8qobKivZRQB323Vx0VeGbr0tDSqWd+uzpWiY33q4eXcmOG O8EtdOQSvwNfO8xFiNcuX5p7GaKtlWVorMKxGr8IhXjmDarpEsShQwiREauQOEloXwyF 1f2WLIP6DHAbuTJmVlPTBz1acSGeifUsiNWEfHXOrUQ0KuLBn43f54Jur43lqFERduTi EhqlxAwIrwjwjKqB47hE0G4jLzkRHw2TKO1QHtqRTeMZaceMNZPSJcGA6C02nsmze9EP at2Q== X-Gm-Message-State: AOJu0YzxXR36MIbksU05SbFB3B952D4SV4oVkTjiIi2GnOYwvEe0WmGj 0Eh+tTaIlRHPiqqiaiaV+AWjrkG6kiu4hManf/6C9oJZ4fVZekHphut/z7pgV40659vxbjIuN3t xKVwF X-Gm-Gg: ASbGnctYUIwh8XJuK9AKm9h9SOOV4zaU3iRl77xI46i8qEWGogJjRrFezs93T4YCbJx hMdupp6SaKusO5T5ETT0DqDyqeVcMUv9fOjhNVHdh7AGVMblE+V9CvVd3ipq7gj9QpXCYr0V7l9 +2BCEt+UaYu0BbTHNxoL+8bUt/bFe679PtV1S/tdat5aW6qpSGf2pLHW0mxATVy1AkLRoQZ8DsE M16NuZ/FuoC44bBj73V5UIcEfSRiEjwqeEikJps7CoLN7qgB2Cm1W3DHZTts50drh4d3IvGtXbq ic3s4xnIj8IvIiB1EW1B/69K7nrJa9s4R8ESOsKCTce6xnLB/2SUaCDg7luvG/FZPqZdsXxZRlz uf6Yt6WGmPC5LgOyFXjjRrm0+OLmobZlZM7jYCqVHZ0Wa+BcvULjSjZi5Ju3pA1pgiG6i8lhpmF 5hT1Jl/3tOI+8WSuAZfk1L8y4= X-Google-Smtp-Source: AGHT+IGfxdzySMdHC+jUgayg+tKS4+MR6GwFQlW3UpxyXKi0fTllbYekQhz3SIQEHKF/UUjDGAxeGw== X-Received: by 2002:a17:907:84c:b0:adb:2a81:46ba with SMTP id a640c23a62f3a-ade1a978c48mr510832266b.34.1749288837910; Sat, 07 Jun 2025 02:33:57 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-95-99.retail.telecomitalia.it. [87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:57 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/10] ARM: dts: imx6ul: support Engicam MicroGEA RMM board Date: Sat, 7 Jun 2025 11:33:19 +0200 Message-ID: <20250607093342.2248695-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-rmm.dts | 362 ++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 57f185198217..32dfd69b8d8b 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..ebde581b090f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-rmm", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL BMM Board"; + + backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm8 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1>; + regulator-name =3D "usb1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2>; + regulator-name =3D "usbotg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_ext_pwr>; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio5 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "imx6ull-microgea-rmm-sgtl5000"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,widgets =3D + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing =3D + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai =3D <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>; + + led-0 { + gpios =3D <&gpio2 10 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpio2 11 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <100000>; + status =3D "okay"; + + touchscreen: touchscreen@38 { + compatible =3D"edt,edt-ft5306"; + reg =3D <0x38>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_touchscreen>; + interrupt-parent =3D <&gpio2>; + interrupts =3D <8 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio2 14 GPIO_ACTIVE_LOW>; + report-rate-hz =3D <6>; + /* settings valid only for Hycon touchscreen */ + touchscreen-size-x =3D <1280>; + touchscreen-size-y =3D <800>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + codec: sgtl5000@a { + compatible =3D "fsl,sgtl5000"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mclk>; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&clks IMX6UL_CLK_CKO>; + assigned-clocks =3D <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>, + <&clks IMX6UL_CLK_CKO>; + assigned-clock-parents =3D <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_CKO2_SEL>, + <&clks IMX6UL_CLK_CKO2_PODF>, + <&clks IMX6UL_CLK_CKO2>; + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + }; +}; + +&iomuxc { + + pinctrl_can: can-grp { + fsl,pins =3D < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x130b0 + >; + }; + + pinctrl_mclk: mclkgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x13009 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins =3D < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_touchscreen: touchgrp { + fsl,pins =3D < + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x17059 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +}; + +&iomuxc_snvs { + + pinctrl_reg_usb1: regusb1grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_reg_ext_pwr: reg-ext-pwrgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x17059 + >; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +&pwm8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm8>; + status =3D "okay"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; 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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:33:59 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Conor Dooley , Fabio Estevam , Francesco Dolcini , Frieder Schrempf , Krzysztof Kozlowski , Marek Vasut , Markus Niebel , Max Merchel , Michael Walle , Peng Fan , Primoz Fiser , Rob Herring , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH 08/10] dt-bindings: arm: fsl: support Engicam MicroGEA GTW board Date: Sat, 7 Jun 2025 11:33:20 +0200 Message-ID: <20250607093342.2248695-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA GTW board based on the Engicam MicroGEA SoM (System-on-Module). Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 58492b1cd468..99ff7c78544b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -773,6 +773,7 @@ properties: items: - enum: - engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam Micr= oGEA BMM Board + - engicam,microgea-imx6ull-gtw # i.MX6ULL Engicam Micr= oGEA GTW Board - engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam Micr= oGEA RMM Board - const: engicam,microgea-imx6ull # i.MX6ULL Engicam Micr= oGEA SoM - const: fsl,imx6ull --=20 2.43.0 From nobody Fri Dec 19 07:52:02 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC2CE20C492 for ; Sat, 7 Jun 2025 09:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288844; cv=none; b=IJ4DANkJxxJ+lOX/LHVYv8N6TLLtafCl6VC8ENCScSoaRH7LKXJDqSf4odU2FsRxB94DxL6AZbl/HpVmGMw3ExlwnllcWlSX1Ngt59z3ZqPpMMs+Jutypc8kBIRN3CVq9xwUN0m4PSEa8RCKQkgfNHWeIbx07crGoCPgUjtIDPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749288844; c=relaxed/simple; bh=EnaaBSVIHASN/VvhxdKxZE1FQofT/VReabBoLiuFpnQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ElMpAOoeax+wJQyaoMlt9u4GlQ49eZvVpPdontBiLINGYYnSImo16oUK4E3/GTmH+PMabGL660yksS//BVDVOmApsWuIxUFKPtqjSREZAAAhjd3UyglN+brw97uyPztf68cNkFBmchUKGavN56xP5eOLnADrxzS8A2+TWwtXnIM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=n/NLTqi8; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="n/NLTqi8" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-ad89ee255easo510835066b.3 for ; Sat, 07 Jun 2025 02:34:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1749288841; x=1749893641; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BY5a2j93oXGkMU8803msBPZC+Hhuefek8iCrsedNGL4=; b=n/NLTqi8v9f7AOCjY4GwR8GESyZkUtHcjXvwt83GQRJzE/dzTkNjBZFcs20xkaIldO fS9NHeVXAoZifLoavMYQ68uXmqBdvFQX8yggw+sSU4UNbURaLeQK1Ndn4+bTPf/rSdy9 pKQ9WdfxXO3AjBDuBFEd9H+iDhyxT4/hjhZjw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749288841; x=1749893641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BY5a2j93oXGkMU8803msBPZC+Hhuefek8iCrsedNGL4=; b=Qx9+6Idk5FeNgqvc4ty2sYrLVXLRYId9CbYp3b9uaAe9RFCs0w65hmCeNFvn+baF/p Oh62SHXLaibX64aIsScHMylaTu1Db0XN/x04sr93hiZC6dr8lvryiBghhChZXFq++5NP VeaxchXYHXT2utL259yduQK3b7ZkPO8pKkDASbyOJXc+GGx0AUptrlBZ0Ods0UFfruED iIso40SdxMwCQvR0JfrPq6GrYVasz5XGdBH06Tgd+9z0Cp4BOXXkplwpIgAHLRkBp9wg wf4iKlUZmP1nzKRDXpelubFAoMhCOxfIejUQacUjPM1KmhFehoGkK6Pufnz807YMlRdn 1piQ== X-Gm-Message-State: AOJu0YzHYQnGD4kONb6ln1ErfoZEp4pfKzoNFyRMTBy3M75pXdiRRqd1 yrRQOiWyybroK+7wfpG4Wu8H1iN172/4REpHlBV4G/xgUKndwuBaxTejgRxTAcKmsDwlHdtp/aA xIAz5 X-Gm-Gg: ASbGncsGVsIntv7Cc7eaDHDuBrsTmau0UVh0RwATkDJeWZ2RxR932r1Kvivoh+gwsDg K5ZeU6JYqlkHuljYaV2jfMtt9++FzWeTe3abq0Nu8HYphflSKVxzPWWiuiWCx81gZdVQDv7ARwn 8I4/VYTx7veMzMn321oRrtuaJ18ox4tBM964nB+XCCszHqR8kXOxpM+FD+LlfHHZ9wfTBCe2MRy wGH7xI2wKF+y1CGThC/JY5MPgoqY4aePzKTIGcsmEfMzgry0zdJzCYcXlLEaqrE5JImOFXe0k4Q slfnAzMSxNr7+SgIEr2B3JK4b/SoaW/PU9RyppgKMVetWui3wnT8P3CbDXIdtf8DRJAvPF9Fu1J vfOI1Mxd20oK/Mhe8xH5NgBl6j8T3vjMIl/bfXaA+LzNOdZV8bCscOfwzRTTUOIktpxMAyGKf3j 8sz6bwq2nhCQl8 X-Google-Smtp-Source: AGHT+IH+nnLe4nhY/KmC1nxcHmSMY3MeJ1Ohpe9/3X5P0YmlpM51ucnPzgCI+0Whb6pU1/wD56roKQ== X-Received: by 2002:a17:907:970c:b0:ad8:a935:b905 with SMTP id a640c23a62f3a-ade1a905ae2mr485259166b.22.1749288840892; Sat, 07 Jun 2025 02:34:00 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-95-99.retail.telecomitalia.it. [87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:34:00 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/10] ARM: dts: imx6ul: support Engicam MicroGEA GTW board Date: Sat, 7 Jun 2025 11:33:21 +0200 Message-ID: <20250607093342.2248695-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../nxp/imx/imx6ull-engicam-microgea-gtw.dts | 164 ++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.= dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx= /Makefile index 32dfd69b8d8b..de4142e8f3ce 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -357,6 +357,7 @@ dtb-$(CONFIG_SOC_IMX6UL) +=3D \ imx6ull-dhcom-picoitx.dtb \ imx6ull-dhcor-maveo-box.dtb \ imx6ull-engicam-microgea-bmm.dtb \ + imx6ull-engicam-microgea-gtw.dtb \ imx6ull-engicam-microgea-rmm.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts new file mode 100644 index 000000000000..1c82ac08bfb4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-gtw.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * Copyright (C) 2025 Engicam srl + */ + +/dts-v1/; + +#include "imx6ull-engicam-microgea.dtsi" + +/ { + compatible =3D "engicam,microgea-imx6ull-gtw", + "engicam,microgea-imx6ull", "fsl,imx6ull"; + model =3D "Engicam MicroGEA i.MX6ULL GTW Board"; + + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_keys>; + + user-button { + label =3D "User button"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_leds>, <&pinctrl_pwrled>; + + led-0 { + gpios =3D <&gpio5 7 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + led-1 { + gpios =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + gpios =3D <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios =3D <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + usb_hub: usb-hub { + compatible =3D "smsc,usb3503a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_hub>; + reset-gpios =3D <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins =3D < + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x130b0 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x130b0 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&usbotg1 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbotg2 { + dr_mode =3D "host"; + disable-over-current; + status =3D "okay"; +}; + +/* MicroSD */ +&usdhc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + vmmc-supply =3D <®_3v3>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; +}; + +&iomuxc_snvs { + pinctrl_pwrled: ledsgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x130b0 + >; + }; + + pinctrl_usb_hub: usb_hubgrp { + fsl,pins =3D < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x17059 + >; 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[87.5.95.99]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc1c316sm251541066b.98.2025.06.07.02.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jun 2025 02:34:02 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Matteo Lisi , linux-amarula@amarulasolutions.com, Dario Binacchi , Alexander Stein , Andreas Kemnade , Ard Biesheuvel , Dmitry Baryshkov , Elinor Montmasson , Eric Biggers , Fabio Estevam , Pengutronix Kernel Team , Russell King , Sascha Hauer , Shawn Guo , Stefan Eichenberger , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/10] ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503 Date: Sat, 7 Jun 2025 11:33:22 +0200 Message-ID: <20250607093342.2248695-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> References: <20250607093342.2248695-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver is required by the Engicam MicroGEA GTW board. Signed-off-by: Dario Binacchi --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6= _v7_defconfig index 917bc8a27794..3181775a214d 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -335,6 +335,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=3Dm CONFIG_USB_SERIAL_OPTION=3Dm CONFIG_USB_TEST=3Dm CONFIG_USB_EHSET_TEST_FIXTURE=3Dm +CONFIG_USB_HSIC_USB3503=3Dy CONFIG_USB_ONBOARD_DEV=3Dy CONFIG_NOP_USB_XCEIV=3Dy CONFIG_USB_MXS_PHY=3Dy --=20 2.43.0