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Sat, 7 Jun 2025 08:43:58 -0400 (EDT) From: Jiaxun Yang Date: Sat, 07 Jun 2025 13:43:56 +0100 Subject: [PATCH v2] MIPS: mm: tlb-r4k: Uniquify TLB entries on init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250607-tlb-fix-v2-1-6751eccd86f1@flygoat.com> X-B4-Tracking: v=1; b=H4sIAAs0RGgC/2WMSw7CIBQAr9K8tRggfNSV9zBdAD5akloMEGLTc HexW5czmcwOGVPADLdhh4Q15BDXDvw0gJvNOiEJz87AKZdUUUnKYokPHyL1xRqnLUqhoNfvhF0 fp8fYeQ65xLQd48p+9v9RGWFEGC+uyjNtub/7ZZuiKWcXXzC21r4qNXlioAAAAA== X-Change-ID: 20250605-tlb-fix-578bac7be546 To: Thomas Bogendoerfer Cc: "Maciej W. Rozycki" , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, stable@kernel.org, Jiaxun Yang X-Mailer: b4 0.14.2 Hardware or bootloader will initialize TLB entries to any value, which may collide with kernel's UNIQUE_ENTRYHI value. On MIPS microAptiv/M5150 family of cores this will trigger machine check exception and cause boot failure. On M5150 simulation this could happen 7 times out of 1000 boots. Replace local_flush_tlb_all() with r4k_tlb_uniquify() which probes each TLB ENTRIHI unique value for collisions before it's written, and in case of collision try a different ASID. Cc: stable@kernel.org Signed-off-by: Jiaxun Yang --- Changes in v2: - Cycle ASID instead of ENTRYHI index in case of collison. - Avoid int over flow UB (Maciej) - Link to v1: https://lore.kernel.org/r/20250605-tlb-fix-v1-1-4af496f17b2f@= flygoat.com --- arch/mips/mm/tlb-r4k.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 76f3b9c0a9f0ce60c42e4a9ea8025e1283678bd1..347126dc010dd59904820d9d9e3= 4cdeeb011832f 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -508,6 +508,60 @@ static int __init set_ntlb(char *str) =20 __setup("ntlb=3D", set_ntlb); =20 +/* Initialise all TLB entries with unique values */ +static void r4k_tlb_uniquify(void) +{ + int entry =3D num_wired_entries(); + + htw_stop(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + + while (entry < current_cpu_data.tlbsize) { + unsigned long asid_mask =3D cpu_asid_mask(¤t_cpu_data); + unsigned long asid =3D 0; + int idx; + + /* Skip wired MMID to make ginvt_mmid work */ + if (cpu_has_mmid) + asid =3D MMID_KERNEL_WIRED + 1; + + /* Check for match before using UNIQUE_ENTRYHI */ + do { + if (cpu_has_mmid) { + write_c0_memorymapid(asid); + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); + } else { + write_c0_entryhi(UNIQUE_ENTRYHI(entry) | asid); + } + mtc0_tlbw_hazard(); + tlb_probe(); + tlb_probe_hazard(); + idx =3D read_c0_index(); + /* No match or match is on current entry */ + if (idx < 0 || idx =3D=3D entry) + break; + /* + * If we hit a match, we need to try again with + * a different ASID. + */ + asid++; + } while (asid < asid_mask); + + if (idx >=3D 0 && idx !=3D entry) + panic("Unable to uniquify TLB entry %d", idx); + + write_c0_index(entry); + mtc0_tlbw_hazard(); + tlb_write_indexed(); + entry++; + } + + tlbw_use_hazard(); + htw_start(); + flush_micro_tlb(); +} + /* * Configure TLB (for init or after a CPU has been powered off). */ @@ -547,7 +601,7 @@ static void r4k_tlb_configure(void) temp_tlb_entry =3D current_cpu_data.tlbsize - 1; =20 /* From this point on the ARC firmware is dead. */ - local_flush_tlb_all(); + r4k_tlb_uniquify(); =20 /* Did I tell you that ARC SUCKS? */ } --- base-commit: 911483b25612c8bc32a706ba940738cc43299496 change-id: 20250605-tlb-fix-578bac7be546 Best regards, --=20 Jiaxun Yang