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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-452730b9b27sm30951595e9.23.2025.06.06.12.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 12:22:40 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] dt-bindings: phy: airoha: Document support for AN7583 PCIe PHY Date: Fri, 6 Jun 2025 21:22:04 +0200 Message-ID: <20250606192208.26465-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606192208.26465-1-ansuelsmth@gmail.com> References: <20250606192208.26465-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port work. Add the rwquired register to configure the PCIe PHY and provide an example for it. Signed-off-by: Christian Marangi --- .../bindings/phy/airoha,an7583-pcie-phy.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pci= e-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.y= aml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml new file mode 100644 index 000000000000..93252092c2e3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 PCI-Express PHY + +maintainers: + - Christian Marangi + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 po= rt. + +properties: + compatible: + const: airoha,an7583-pcie-phy + + reg: + items: + - description: PCIE G3 analog base address + - description: PCIE G3 PMA base address + - description: PCIE QPhy analog base address + - description: PCIE QPhy PMA base address + - description: PCIE QPhy diagnostic base address + - description: PCIE detection time base address + - description: PCIE Rx AEQ base address + + reg-names: + items: + - const: g3-ana + - const: g3-pma + - const: qp-ana + - const: qp-pma + - const: qp-dig + - const: xr-dtime + - const: rx-aeq + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + phy@11e80000 { + compatible =3D "airoha,an7583-pcie-phy"; + #phy-cells =3D <0>; + reg =3D <0x0 0x1fc7f000 0x0 0xfff>, + <0x0 0x1fc7e000 0x0 0xfff>, + <0x0 0x1fa5f000 0x0 0xff>, + <0x0 0x1fa5e000 0x0 0x8ff>, + <0x0 0x1fa5a000 0x0 0x3ff>, + <0x0 0x1fc30044 0x0 0x4>, + <0x0 0x1fc35030 0x0 0x4>; + reg-names =3D "g3-ana", "g3-pma", + "qp-ana", "qp-pma", "qp-dig", + "xr-dtime", "rx-aeq"; + }; + }; --=20 2.48.1