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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-452730b9b27sm30951595e9.23.2025.06.06.12.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 12:22:37 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] phy: move Airoha PCIe PHY driver to dedicated directory Date: Fri, 6 Jun 2025 21:22:02 +0200 Message-ID: <20250606192208.26465-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606192208.26465-1-ansuelsmth@gmail.com> References: <20250606192208.26465-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for additional PHY driver for different Airoha SoC, move the current PCIe PHY driver in a dedicated directory. Signed-off-by: Christian Marangi --- MAINTAINERS | 4 ++-- drivers/phy/Kconfig | 11 +---------- drivers/phy/Makefile | 4 ++-- drivers/phy/airoha/Kconfig | 13 +++++++++++++ drivers/phy/airoha/Makefile | 2 ++ drivers/phy/{ =3D> airoha}/phy-airoha-pcie-regs.h | 0 drivers/phy/{ =3D> airoha}/phy-airoha-pcie.c | 0 7 files changed, 20 insertions(+), 14 deletions(-) create mode 100644 drivers/phy/airoha/Kconfig create mode 100644 drivers/phy/airoha/Makefile rename drivers/phy/{ =3D> airoha}/phy-airoha-pcie-regs.h (100%) rename drivers/phy/{ =3D> airoha}/phy-airoha-pcie.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 6dbdf02d6b0c..2f30432916a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -735,8 +735,8 @@ M: Lorenzo Bianconi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml -F: drivers/phy/phy-airoha-pcie-regs.h -F: drivers/phy/phy-airoha-pcie.c +F: drivers/phy/airoha/phy-airoha-pcie-regs.h +F: drivers/phy/airoha/phy-airoha-pcie.c =20 AIROHA SPI SNFI DRIVER M: Lorenzo Bianconi diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 8d58efe998ec..7f9f5b786643 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -72,16 +72,6 @@ config PHY_CAN_TRANSCEIVER functional modes using gpios and sets the attribute max link rate, for CAN drivers. =20 -config PHY_AIROHA_PCIE - tristate "Airoha PCIe-PHY Driver" - depends on ARCH_AIROHA || COMPILE_TEST - depends on OF - select GENERIC_PHY - help - Say Y here to add support for Airoha PCIe PHY driver. - This driver create the basic PHY instance and provides initialize - callback for PCIe GEN3 port. - config PHY_NXP_PTN3222 tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver" depends on I2C @@ -93,6 +83,7 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +source "drivers/phy/airoha/Kconfig" source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index e281442acc75..0ad0e5309493 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -10,9 +10,9 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) +=3D phy-lpc18xx-usb-ot= g.o obj-$(CONFIG_PHY_XGENE) +=3D phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) +=3D phy-pistachio-usb.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o -obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o -obj-y +=3D allwinner/ \ +obj-y +=3D airoha/ \ + allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig new file mode 100644 index 000000000000..1674134ea664 --- /dev/null +++ b/drivers/phy/airoha/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Airoha platforms +# +config PHY_AIROHA_PCIE + tristate "Airoha PCIe-PHY Driver" + depends on ARCH_AIROHA || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Say Y here to add support for Airoha PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN3 port. diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile new file mode 100644 index 000000000000..616dc96302af --- /dev/null +++ b/drivers/phy/airoha/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o diff --git a/drivers/phy/phy-airoha-pcie-regs.h b/drivers/phy/airoha/phy-ai= roha-pcie-regs.h similarity index 100% rename from drivers/phy/phy-airoha-pcie-regs.h rename to drivers/phy/airoha/phy-airoha-pcie-regs.h diff --git a/drivers/phy/phy-airoha-pcie.c b/drivers/phy/airoha/phy-airoha-= pcie.c similarity index 100% rename from drivers/phy/phy-airoha-pcie.c rename to drivers/phy/airoha/phy-airoha-pcie.c --=20 2.48.1 From nobody Fri Dec 19 07:32:34 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0399420FA90; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-452730b9b27sm30951595e9.23.2025.06.06.12.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 12:22:38 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] phy: airoha: add EN7581 tag to PCIe PHY driver Date: Fri, 6 Jun 2025 21:22:03 +0200 Message-ID: <20250606192208.26465-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606192208.26465-1-ansuelsmth@gmail.com> References: <20250606192208.26465-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for support of Airoha AN7583 PCIe PHY driver, add EN7581 tag to PCIe PHY driver and register header. This is needed to better differentiate the 2 driver and 2 register header between EN7581 and AN7583 that require a very different setup process to make the PCIe port work. Signed-off-by: Christian Marangi --- MAINTAINERS | 6 +++--- drivers/phy/airoha/Kconfig | 6 +++--- drivers/phy/airoha/Makefile | 2 +- ...phy-airoha-pcie-regs.h =3D> phy-airoha-en7581-pcie-regs.h} | 0 .../airoha/{phy-airoha-pcie.c =3D> phy-airoha-en7581-pcie.c} | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) rename drivers/phy/airoha/{phy-airoha-pcie-regs.h =3D> phy-airoha-en7581-p= cie-regs.h} (100%) rename drivers/phy/airoha/{phy-airoha-pcie.c =3D> phy-airoha-en7581-pcie.c= } (99%) diff --git a/MAINTAINERS b/MAINTAINERS index 2f30432916a3..2ea56cd21c8a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -730,13 +730,13 @@ S: Maintained F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml F: drivers/net/ethernet/airoha/ =20 -AIROHA PCIE PHY DRIVER +AIROHA EN7581 PCIE PHY DRIVER M: Lorenzo Bianconi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml -F: drivers/phy/airoha/phy-airoha-pcie-regs.h -F: drivers/phy/airoha/phy-airoha-pcie.c +F: drivers/phy/airoha/phy-airoha-en7581-pcie-regs.h +F: drivers/phy/airoha/phy-airoha-en7581-pcie.c =20 AIROHA SPI SNFI DRIVER M: Lorenzo Bianconi diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig index 1674134ea664..08cc1fe4a11c 100644 --- a/drivers/phy/airoha/Kconfig +++ b/drivers/phy/airoha/Kconfig @@ -2,12 +2,12 @@ # # Phy drivers for Airoha platforms # -config PHY_AIROHA_PCIE - tristate "Airoha PCIe-PHY Driver" +config PHY_AIROHA_EN7581_PCIE + tristate "Airoha EN7581 PCIe-PHY Driver" depends on ARCH_AIROHA || COMPILE_TEST depends on OF select GENERIC_PHY help - Say Y here to add support for Airoha PCIe PHY driver. + Say Y here to add support for Airoha EN7581 PCIe PHY driver. This driver create the basic PHY instance and provides initialize callback for PCIe GEN3 port. diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile index 616dc96302af..f8949a291486 100644 --- a/drivers/phy/airoha/Makefile +++ b/drivers/phy/airoha/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o +obj-$(CONFIG_PHY_AIROHA_EN7581_PCIE) +=3D phy-airoha-en7581-pcie.o diff --git a/drivers/phy/airoha/phy-airoha-pcie-regs.h b/drivers/phy/airoha= /phy-airoha-en7581-pcie-regs.h similarity index 100% rename from drivers/phy/airoha/phy-airoha-pcie-regs.h rename to drivers/phy/airoha/phy-airoha-en7581-pcie-regs.h diff --git a/drivers/phy/airoha/phy-airoha-pcie.c b/drivers/phy/airoha/phy-= airoha-en7581-pcie.c similarity index 99% rename from drivers/phy/airoha/phy-airoha-pcie.c rename to drivers/phy/airoha/phy-airoha-en7581-pcie.c index 56e9ade8a9fd..ea448cdf9ae0 100644 --- a/drivers/phy/airoha/phy-airoha-pcie.c +++ b/drivers/phy/airoha/phy-airoha-en7581-pcie.c @@ -13,7 +13,7 @@ #include #include =20 -#include "phy-airoha-pcie-regs.h" +#include "phy-airoha-en7581-pcie-regs.h" =20 #define LEQ_LEN_CTRL_MAX_VAL 7 #define FREQ_LOCK_MAX_ATTEMPT 10 @@ -1279,12 +1279,12 @@ MODULE_DEVICE_TABLE(of, airoha_pcie_phy_of_match); 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-452730b9b27sm30951595e9.23.2025.06.06.12.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 12:22:40 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] dt-bindings: phy: airoha: Document support for AN7583 PCIe PHY Date: Fri, 6 Jun 2025 21:22:04 +0200 Message-ID: <20250606192208.26465-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606192208.26465-1-ansuelsmth@gmail.com> References: <20250606192208.26465-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port work. Add the rwquired register to configure the PCIe PHY and provide an example for it. Signed-off-by: Christian Marangi --- .../bindings/phy/airoha,an7583-pcie-phy.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pci= e-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.y= aml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml new file mode 100644 index 000000000000..93252092c2e3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 PCI-Express PHY + +maintainers: + - Christian Marangi + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 po= rt. + +properties: + compatible: + const: airoha,an7583-pcie-phy + + reg: + items: + - description: PCIE G3 analog base address + - description: PCIE G3 PMA base address + - description: PCIE QPhy analog base address + - description: PCIE QPhy PMA base address + - description: PCIE QPhy diagnostic base address + - description: PCIE detection time base address + - description: PCIE Rx AEQ base address + + reg-names: + items: + - const: g3-ana + - const: g3-pma + - const: qp-ana + - const: qp-pma + - const: qp-dig + - const: xr-dtime + - const: rx-aeq + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; 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[93.34.88.225]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-452730b9b27sm30951595e9.23.2025.06.06.12.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 12:22:42 -0700 (PDT) From: Christian Marangi To: Christian Marangi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Bianconi , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] phy: airoha: add support for AN7583 PCIe PHY driver Date: Fri, 6 Jun 2025 21:22:05 +0200 Message-ID: <20250606192208.26465-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606192208.26465-1-ansuelsmth@gmail.com> References: <20250606192208.26465-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for AN7583 PCIe PHY driver. This is required to make the Gen3 PCIe port present on the Airoha AN7583 SoC correctly work. A different setup is needed compared to Airoha EN7581 where the calibration process and the register map greatly changed. Signed-off-by: Christian Marangi --- MAINTAINERS | 8 + drivers/phy/airoha/Kconfig | 10 + drivers/phy/airoha/Makefile | 1 + .../phy/airoha/phy-airoha-an7583-pcie-regs.h | 550 +++++++++ drivers/phy/airoha/phy-airoha-an7583-pcie.c | 1069 +++++++++++++++++ 5 files changed, 1638 insertions(+) create mode 100644 drivers/phy/airoha/phy-airoha-an7583-pcie-regs.h create mode 100644 drivers/phy/airoha/phy-airoha-an7583-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index 2ea56cd21c8a..3af266dd93ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -738,6 +738,14 @@ F: Documentation/devicetree/bindings/phy/airoha,en7581= -pcie-phy.yaml F: drivers/phy/airoha/phy-airoha-en7581-pcie-regs.h F: drivers/phy/airoha/phy-airoha-en7581-pcie.c =20 +AIROHA AN7583 PCIE PHY DRIVER +M: Christian Marangi +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml +F: drivers/phy/airoha/phy-airoha-an7583-pcie-regs.h +F: drivers/phy/airoha/phy-airoha-an7583-pcie.c + AIROHA SPI SNFI DRIVER M: Lorenzo Bianconi M: Ray Liu diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig index 08cc1fe4a11c..5fbfc94fd4b7 100644 --- a/drivers/phy/airoha/Kconfig +++ b/drivers/phy/airoha/Kconfig @@ -11,3 +11,13 @@ config PHY_AIROHA_EN7581_PCIE Say Y here to add support for Airoha EN7581 PCIe PHY driver. This driver create the basic PHY instance and provides initialize callback for PCIe GEN3 port. + +config PHY_AIROHA_AN7583_PCIE + tristate "Airoha AN7583 PCIe-PHY Driver" + depends on ARCH_AIROHA || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Say Y here to add support for Airoha AN7583 PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN3 port. diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile index f8949a291486..3efb4438e8f2 100644 --- a/drivers/phy/airoha/Makefile +++ b/drivers/phy/airoha/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_AIROHA_EN7581_PCIE) +=3D phy-airoha-en7581-pcie.o +obj-$(CONFIG_PHY_AIROHA_AN7583_PCIE) +=3D phy-airoha-an7583-pcie.o diff --git a/drivers/phy/airoha/phy-airoha-an7583-pcie-regs.h b/drivers/phy= /airoha/phy-airoha-an7583-pcie-regs.h new file mode 100644 index 000000000000..5a243fe4484c --- /dev/null +++ b/drivers/phy/airoha/phy-airoha-an7583-pcie-regs.h @@ -0,0 +1,550 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 AIROHA Inc + * Author: Christian Marangi + */ + +#ifndef _PHY_AIROHA_PCIE_H +#define _PHY_AIROHA_PCIE_H + +/* QPhy ANA */ +#define REG_QP_RXAFE_RESERVE 0x4 +#define QP_ANA_QP_CDR_PD_10B_EN BIT(11) +#define QP_ANA_QP_CDR_PD_EDGE_DIS BIT(10) + +#define REG_QP_CDR_LPF_MJV_LIM 0xc +#define QP_ANA_QP_CDR_LPF_RATIO GENMASK(5, 4) + +#define REG_QP_CDR_PR_CKREF_DIV1 0x18 +#define QP_ANA_QP_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define QP_ANA_QP_CDR_PR_DAC_BAND GENMASK(12, 8) + +#define REG_QP_CDR_PR_KBAND_DIV_PCIE 0x1c +#define QP_ANA_QP_CDR_PR_XFICK_EN BIT(30) +#define QP_ANA_QP_CDR_PR_KBAND_PCIE_MODE BIT(6) +#define QP_ANA_QP_CDR_PR_KBAND_DIV_PCIE GENMASK(5, 0) + +#define REG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x20 +#define QP_ANA_QP_CDR_PHYCK_RSTB BIT(13) + +#define REG_QP_TX_MODE_16B_EN 0x28 +#define QP_ANA_QP_TX_RESERVE_8 BIT(24) + +#define REG_QP_RXLBTX_EN 0x2c +#define QP_ANA_QP_TX_DMEDGEGEN_EN BIT(27) +#define QP_ANA_QP_TX_RXDET_METHOD BIT(25) + +#define REG_QP_BGR_EN 0x30 +#define QP_ANA_QP_BIAS_V2V_CAL GENMASK(26, 21) +#define QP_ANA_QP_BG_DIV GENMASK(3, 2) + +#define REG_PCIE_CLKDRV_IMPSEL 0x34 +#define QP_ANA_PCIE_CLKDRV_AMP GENMASK(27, 25) +#define QP_ANA_PCIE_CLKDRV_FORCEIN GENMASK(24, 23) +#define QP_ANA_PCIE_CLKDRV_HZ BIT(14) +#define QP_ANA_PCIE_CLKDRV_RP GENMASK(13, 9) +#define QP_ANA_PCIE_CLKDRV_IMPSEL GENMASK(4, 0) + +#define REG_QP_TDC_FT_CK_EN 0x38 +#define QP_ANA_QP_PLL_DEBUG_SEL BIT(19) + +#define REG_QP_PLL_IPLL_DIG_PWR_SEL 0x3c +#define QP_ANA_QP_PLL_PREDIV GENMASK(26, 25) +#define QP_ANA_QP_PLL_MON_LDO_SEL GENMASK(18, 16) +#define QP_ANA_QP_PLL_OSCAL_ENB BIT(19) +#define QP_ANA_QP_PLL_MONVC_EN BIT(14) +#define QP_ANA_QP_PLL_LDOLPF_VSEL GENMASK(6, 5) + +#define REG_QP_PLL_SDM_ORD 0x40 +#define QP_ANA_QP_PLL_SSC_PHASE_INI BIT(3) +#define QP_ANA_QP_PLL_SSC_TRI_EN BIT(4) + +/* QPhy PMA */ +#define REG_QP_TX_DA_CTRL_0 0x0 +#define QP_PMA_RXDET_RD_WAIT_TIMER GENMASK(15, 12) +#define QP_PMA_RXDET_EN_WINDOW GENMASK(9, 4) + +#define REG_QP_TX_DA_CTRL_3 0xc +#define QP_PMA_TX_DATA_RATE_SEL GENMASK(30, 28) + +#define REG_PON_RXFEDIG_CTRL_0 0x100 +#define QP_PMA_QP_EQ_RX500M_CK_SEL BIT(12) + +#define REG_SS_LCPLL_PWCTL_SETTING_2 0x208 +#define QP_PMA_NCPO_ANA_MSB GENMASK(17, 16) + +#define REG_SS_LCPLL_TDC_FLT_2 0x230 +#define QP_PMA_LCPLL_NCPO_VALUE GENMASK(30, 0) + +#define REG_SS_LCPLL_TDC_PCW_1 0x248 +#define QP_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) + +#define REG_INTF_CTRL_6 0x318 +#define QP_PMA_DA_QP_TX_DATA_EN_SEL BIT(13) +#define QP_PMA_DA_QP_TX_DATA_EN_FORCE BIT(12) + +#define REG_INTF_CTRL_7 0x31c +#define QP_PMA_DA_QP_PLL_EN_SEL BIT(5) +#define QP_PMA_DA_QP_PLL_EN_FORCE BIT(4) + +#define REG_INTF_CTRL_8 0x320 +#define QP_PMA_DA_QP_XTAL_EXT_EN_SEL BIT(13) +#define QP_PMA_DA_QP_XTAL_EXT_EN_FORCE GENMASK(12, 11) + +#define REG_INTF_STS_9 0x364 +#define QP_PMA_ADDR_INTF_STS_PLL_VCOCAL GENMASK(23, 16) + +#define REG_PLL_CTRL_0 0x400 +#define QP_PMA_PHYA_AUTO_INIT BIT(0) + +#define REG_PLL_CTRL_1 0x404 +#define QP_PMA_QP_PLL_SSC_EN BIT(30) + +#define REG_PLL_CTRL_2 0x408 +#define QP_PMA_DA_QP_PLL_SDM_IFM_INTF BIT(30) +#define QP_PMA_DA_QP_PLL_RICO_SEL_INTF BIT(29) +#define QP_PMA_DA_QP_PLL_PHY_CK_EN_INTF BIT(27) +#define QP_PMA_DA_QP_PLL_PCK_SEL_INTF BIT(22) +#define QP_PMA_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20) +#define QP_PMA_DA_QP_PLL_IR_INTF GENMASK(19, 16) +#define QP_PMA_DA_QP_PLL_ICOIQ_EN_INTF BIT(14) +#define QP_PMA_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12) +#define QP_PMA_DA_QP_PLL_BPB_INTF GENMASK(7, 6) +#define QP_PMA_DA_QP_PLL_BPA_INTF GENMASK(4, 2) +#define QP_PMA_DA_QP_PLL_BC_INTF GENMASK(1, 0) + +#define REG_PLL_CTRL_3 0x40c +#define QP_PMA_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16) +#define QP_PMA_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0) + +#define REG_PLL_CTRL_4 0x410 +#define QP_PMA_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3) +#define QP_PMA_DA_QP_PLL_ICOLP_EN_INTF BIT(2) + +#define REG_PLL_CK_CTRL_0 0x414 +#define QP_PMA_DA_PCIE_CLKTX_EN_INTF BIT(5) +#define QP_PMA_DA_PCIE_CLKRX_EN_INTF BIT(4) + +#define REG_PLL_CK_CTRL_1 0x418 +#define QP_PMA_PLL_FORCE_UNSTABLE BIT(19) +#define QP_PMA_PLL_FORCE_STABLE BIT(18) + +#define REG_PLL_CK_CTRL_2 0x41c +#define QP_PMA_PCIE_MODE_PLL_AUTO_OFF_EN BIT(2) +#define QP_PMA_PCIE_MODE_PLL_AUTO_ON_EN BIT(1) +#define QP_PMA_PCIE_MODE_PLL_AUTO_EN BIT(0) + +#define REG_RX_DLY_0 0x614 +#define QP_PMA_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0) + +#define REG_RX_CTRL_2 0x630 +#define QP_PMA_QP_RX_EQ_EN_H_DLY GENMASK(28, 16) + +#define REG_RX_CTRL_5 0x63c +#define QP_PMA_FREDET_CHK_CYCLE GENMASK(29, 10) + +#define REG_RX_CTRL_6 0x640 +#define QP_PMA_FREDET_GOLDEN_CYCLE GENMASK(19, 0) + +#define REG_RX_CTRL_7 0x644 +#define QP_PMA_FREDET_TOLERATE_CYCLE GENMASK(19, 0) + +#define REG_RX_CTRL_10 0x650 +#define QP_PMA_QP_CRSDET_RSTB BIT(1) + +#define REG_RX_CTRL_11 0x654 +#define QP_PMA_QP_FORCE_SIGDET_5G BIT(19) + +#define REG_RX_CTRL_36 0x6b8 +#define QP_PMA_QP_PCIE_USB_SYSTEM BIT(26) +#define QP_PMA_QP_LCK2DATA_DLY_TIME_9_0 GENMASK(25, 16) + +#define REG_RX_CTRL_45 0x6dc +#define QP_PMA_QP_EQ_EN_DLY GENMASK(12, 0) + +#define REG_RX_CTRL_46 0x6e0 +#define QP_PMA_QP_PCIE_USB_BYPASS_EQ_P1_TO_P0_EN BIT(27) +#define QP_PMA_REBACK_P0_LCK2REF_EN BIT(26) + +#define REG_RX_CTRL_50 0x6f0 +#define QP_PMA_QP_EQ_EN_DLY_SHORT GENMASK(25, 13) +#define QP_PMA_QP_RX_EQ_EN_H_DLY_SHORT GENMASK(12, 0) + +/* QPhy DIG */ +#define REG_QP_CK_RST_CTRL_3 0x30c +#define QP_DIG_NS_CK_DIV_SEL BIT(25) +#define QP_DIG_US_CK_DIV_SEL BIT(24) + +#define REG_QP_CK_RST_CTRL_7 0x340 +#define QP_DIG_MULTI_PHY_USB2P5_EN BIT(26) +#define QP_DIG_MULTI_PHY_USB5_EN BIT(25) +#define QP_DIG_MULTI_PHY_USB_MODE_EN BIT(24) + +/* G3 ANA */ +#define REG_PXP_CMN_EN 0x0 +#define G3_ANA_PXP_CMN_TRIM GENMASK(28, 24) +#define G3_ANA_PXP_CMN_EN BIT(0) + +#define REG_PXP_JCPLL_IB_EXT_EN 0x4 +#define G3_ANA_PXP_JCPLL_CHP_IOFST GENMASK(29, 24) +#define G3_ANA_PXP_JCPLL_CHP_IBIAS GENMASK(21, 16) +#define G3_ANA_PXP_JCPLL_LPF_SHCK_EN BIT(8) + +#define REG_PXP_JCPLL_LPF_BR 0x8 +#define G3_ANA_PXP_JCPLL_LPF_BWR GENMASK(28, 24) +#define G3_ANA_PXP_JCPLL_LPF_BP GENMASK(20, 16) +#define G3_ANA_PXP_JCPLL_LPF_BC GENMASK(12, 8) +#define G3_ANA_PXP_JCPLL_LPF_BR GENMASK(4, 0) + +#define REG_PXP_JCPLL_LPF_BWC 0xc +#define G3_ANA_PXP_JCPLL_KBAND_DIV GENMASK(26, 24) +#define G3_ANA_PXP_JCPLL_KBAND_CODE GENMASK(23, 16) +#define G3_ANA_PXP_JCPLL_LPF_BWC GENMASK(4, 0) + +#define REG_PXP_JCPLL_KBAND_KFC 0x10 +#define G3_ANA_PXP_JCPLL_POSTDIV_EN BIT(24) +#define G3_ANA_PXP_JCPLL_KBAND_KS GENMASK(17, 16) +#define G3_ANA_PXP_JCPLL_KBAND_KF GENMASK(9, 8) +#define G3_ANA_PXP_JCPLL_KBAND_KFC GENMASK(1, 0) + +#define REG_PXP_JCPLL_MMD_PREDIV_MODE 0x14 +#define G3_ANA_PXP_JCPLL_POSTDIV_D5 BIT(24) +#define G3_ANA_PXP_JCPLL_POSTDIV_D2 BIT(16) +#define G3_ANA_PXP_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) + +#define REG_PXP_JCPLL_MONCK_EN 0x18 +#define G3_ANA_PXP_JCPLL_REFIN_DIV GENMASK(25, 24) + +#define REG_PXP_JCPLL_RST_DLY 0x1c +#define G3_ANA_PXP_JCPLL_SDM_DI_LS GENMASK(25, 24) +#define G3_ANA_PXP_JCPLL_SDM_DI_EN BIT(16) +#define G3_ANA_PXP_JCPLL_PLL_RSTB BIT(8) +#define G3_ANA_PXP_JCPLL_RST_DLY GENMASK(2, 0) + +#define REG_PXP_JCPLL_SDM_IFM 0x20 +#define G3_ANA_PXP_JCPLL_SDM_IFM BIT(0) + +#define REG_PXP_JCPLL_SDM_HREN 0x24 +#define G3_ANA_PXP_JCPLL_TCL_AMP_VREF GENMASK(28, 24) +#define G3_ANA_PXP_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) +#define G3_ANA_PXP_JCPLL_TCL_AMP_EN BIT(8) +#define G3_ANA_PXP_JCPLL_SDM_HREN BIT(0) + +#define REG_PXP_JCPLL_TCL_CMP_EN 0x28 +#define G3_ANA_PXP_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define G3_ANA_PXP_JCPLL_TCL_LPF_EN BIT(16) + +#define REG_PXP_JCPLL_VCODIV 0x2c +#define G3_ANA_PXP_JCPLL_VCO_SCAPWR GENMASK(26, 24) +#define G3_ANA_PXP_JCPLL_VCO_HALFLSB_EN BIT(16) +#define G3_ANA_PXP_JCPLL_VCO_CFIX GENMASK(9, 8) + +#define REG_PXP_JCPLL_VCO_TCLVAR 0x30 +#define G3_ANA_PXP_JCPLL_SSC_PHASE_INI BIT(17) +#define G3_ANA_PXP_JCPLL_SSC_EN BIT(16) +#define G3_ANA_PXP_JCPLL_VCO_TCLVAR GENMASK(2, 0) + +#define REG_PXP_JCPLL_SSC_TRI_EN 0x34 +#define G3_ANA_PXP_JCPLL_SSC_DELTA1 GENMASK(23, 8) +#define G3_ANA_PXP_JCPLL_SSC_TRI_EN BIT(0) + +#define REG_PXP_JCPLL_SSC_DELTA 0x38 +#define G3_ANA_PXP_JCPLL_SSC_PERIOD GENMASK(31, 16) +#define G3_ANA_PXP_JCPLL_SSC_DELTA GENMASK(15, 0) + +#define REG_PXP_JCPLL_SPARE_H 0x48 +#define G3_ANA_PXP_JCPLL_TCL_KBAND_VREF GENMASK(20, 16) +#define G3_ANA_PXP_JCPLL_SPARE_L GENMASK(15, 8) + +#define REG_PXP_JCPLL_FREQ_MEAS_EN 0x4c +#define G3_ANA_PXP_TXPLL_LPF_SHCK_EN BIT(25) +#define G3_ANA_PXP_JCPLL_VCO_KBAND_MEAS_EN BIT(8) + +#define REG_PXP_TXPLL_CHP_IBIAS 0x50 +#define G3_ANA_PXP_TXPLL_LPF_BC GENMASK(28, 24) +#define G3_ANA_PXP_TXPLL_LPF_BR GENMASK(20, 16) +#define G3_ANA_PXP_TXPLL_CHP_IOFST GENMASK(13, 8) +#define G3_ANA_PXP_TXPLL_CHP_IBIAS GENMASK(5, 0) + +#define REG_PXP_TXPLL_LPF_BP 0x54 +#define G3_ANA_PXP_TXPLL_LPF_BWC GENMASK(20, 16) +#define G3_ANA_PXP_TXPLL_LPF_BWR GENMASK(12, 8) +#define G3_ANA_PXP_TXPLL_LPF_BP GENMASK(4, 0) + +#define REG_PXP_TXPLL_KBAND_CODE 0x58 +#define G3_ANA_PXP_TXPLL_KBAND_KF GENMASK(25, 24) +#define G3_ANA_PXP_TXPLL_KBAND_KFC GENMASK(17, 16) +#define G3_ANA_PXP_TXPLL_KBAND_DIV GENMASK(10, 8) +#define G3_ANA_PXP_TXPLL_KBAND_CODE GENMASK(7, 0) + +#define REG_PXP_TXPLL_KBAND_KS 0x5c +#define G3_ANA_PXP_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16) +#define G3_ANA_PXP_TXPLL_POSTDIV_EN BIT(8) +#define G3_ANA_PXP_TXPLL_KBAND_KS GENMASK(1, 0) + +#define REG_PXP_TXPLL_PHY_CK1_EN 0x60 +#define G3_ANA_PXP_TXPLL_PHY_CK1_EN BIT(0) + +#define REG_PXP_TXPLL_REFIN_INTERNAL 0x64 +#define G3_ANA_PXP_TXPLL_PLL_RSTB BIT(24) +#define G3_ANA_PXP_TXPLL_RST_DLY GENMASK(18, 16) +#define G3_ANA_PXP_TXPLL_REFIN_DIV GENMASK(9, 8) +#define G3_ANA_PXP_TXPLL_REFIN_INTERNAL BIT(0) + +#define REG_PXP_TXPLL_SDM_DI_EN 0x68 +#define G3_ANA_PXP_TXPLL_SDM_IFM BIT(16) +#define G3_ANA_PXP_TXPLL_SDM_DI_LS GENMASK(9, 8) + +#define REG_PXP_TXPLL_SDM_ORD 0x6c +#define G3_ANA_PXP_TXPLL_TCL_AMP_EN BIT(24) +#define G3_ANA_PXP_TXPLL_SDM_ORD GENMASK(1, 0) + +#define REG_PXP_TXPLL_TCL_AMP_GAIN 0x70 +#define G3_ANA_PXP_TXPLL_TCL_AMP_VREF GENMASK(12, 8) +#define G3_ANA_PXP_TXPLL_TCL_AMP_GAIN GENMASK(2, 0) + +#define REG_PXP_TXPLL_TCL_LPF_EN 0x74 +#define G3_ANA_PXP_TXPLL_VCO_CFIX GENMASK(25, 24) +#define G3_ANA_PXP_TXPLL_TCL_LPF_BW GENMASK(10, 8) +#define G3_ANA_PXP_TXPLL_TCL_LPF_EN BIT(0) + +#define REG_PXP_TXPLL_VCO_HALFLSB_EN 0x78 +#define G3_ANA_PXP_TXPLL_VCO_SCAPWR GENMASK(10, 8) +#define G3_ANA_PXP_TXPLL_VCO_HALFLSB_EN BIT(0) + +#define REG_PXP_TXPLL_SSC_EN 0x7c +#define G3_ANA_PXP_TXPLL_SSC_PHASE_INI BIT(8) +#define G3_ANA_PXP_TXPLL_SSC_EN BIT(0) + +#define REG_PXP_TXPLL_SSC_DELTA1 0x80 +#define G3_ANA_PXP_TXPLL_SSC_DELTA GENMASK(31, 16) +#define G3_ANA_PXP_TXPLL_SSC_DELTA1 GENMASK(15, 0) + +#define REG_PXP_TXPLL_SSC_PERIOD 0x84 +#define G3_ANA_PXP_TXPLL_SSC_PERIOD GENMASK(15, 0) + +#define REG_PXP_TXPLL_VTP_EN 0x88 +#define G3_ANA_PXP_TXPLL_VTP_EN BIT(0) + +#define REG_PXP_TXPLL_TCL_VTP_EN 0x90 +#define G3_ANA_PXP_TXPLL_SPARE_L GENMASK(31, 24) + +#define REG_PXP_TXPLL_TCL_KBAND_VREF 0x94 +#define G3_ANA_PXP_TXPLL_VCO_KBAND_MEAS_EN BIT(24) +#define G3_ANA_PXP_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) + +#define REG_PCIE_CLKTX0_AMP 0x98 +#define G3_ANA_PXP_PCIE_CLKTX0_IMP_SEL GENMASK(31, 27) +#define G3_ANA_PXP_PCIE_CLKTX0_HZ BIT(26) +#define G3_ANA_PCIE_CLKTX0_SR GENMASK(17, 16) +#define G3_ANA_PCIE_CLKTX0_OFFSET GENMASK(9, 8) +#define G3_ANA_PCIE_CLKTX0_AMP GENMASK(2, 0) + +#define REG_PXP_PLL_MONCLK_SEL 0xa0 +#define G3_ANA_PXP_PLL_CMN_RESERVE0 GENMASK(15, 8) + +#define REG_PXP_TX_CKLDO_EN 0xc4 +#define G3_ANA_PXP_TX_DMEDGEGEN_EN BIT(24) +#define G3_ANA_PXP_TX_CKLDO_EN BIT(0) + +#define REG_PXP_RX_REV_0 0xd4 +#define G3_ANA_PXP_RX_REV_1_10_8 GENMASK(26, 24) +#define G3_ANA_PXP_RX_REV_1_6_4 GENMASK(22, 20) +#define G3_ANA_PXP_RX_REV_1_3_2 GENMASK(19, 18) + +#define REG_PXP_RX_PHYCK_DIV 0xd8 +#define G3_ANA_PXP_RX_TDC_CK_SEL BIT(24) +#define G3_ANA_PXP_RX_PHYCK_RSTB BIT(16) +#define G3_ANA_PXP_RX_PHYCK_SEL GENMASK(9, 8) + +#define REG_PXP_CDR_PD_PICAL_CKD8_INV 0xdc +#define G3_ANA_PXP_CDR_PD_EDGE_DIS BIT(8) + +#define REG_PXP_CDR_LPF_RATIO 0xe8 +#define G3_ANA_PXP_CDR_LPF_TOP_LIM GENMASK(26, 8) + +#define REG_PXP_CDR_PR_BETA_DAC 0xf8 +#define G3_ANA_PXP_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define G3_ANA_PXP_CDR_PR_BETA_SEL GENMASK(19, 16) + +#define REG_PXP_CDR_PR_VREG_IBAND_VAL 0xfc +#define G3_ANA_PXP_CDR_PR_VREG_CKBUF_VAL_2_0 GENMASK(10, 8) +#define G3_ANA_PXP_CDR_PR_VREG_IBAND_VAL_2_0 GENMASK(2, 0) + +#define REG_PXP_CDR_PR_CKREF_DIV 0x100 +#define G3_ANA_PXP_CDR_PR_CKREF_DIV_1_0 GENMASK(1, 0) + +#define REG_PXP_CDR_PR_TDC_REF_SEL 0x108 +#define G3_ANA_PXP_CDR_PR_CKREF_DIV1_1_0 GENMASK(25, 24) +#define G3_ANA_PXP_CDR_PR_LDO_FORCE_ON BIT(16) + +#define REG_PXP_CDR_PR_MONPR_EN 0x10c +#define G3_ANA_PXP_CDR_PR_XFICK_EN BIT(2) + +#define REG_PXP_RX_DAC_RANGE 0x110 +#define G3_ANA_PXP_RX_SIGDET_LPF_CTRL GENMASK(25, 24) + +#define REG_PXP_CDR_PR_MONCK_EN 0x104 +#define G3_ANA_PXP_CDR_PR_MONCK_EN BIT(0) +#define G3_ANA_PXP_CDR_PR_RESERVE0 GENMASK(19, 16) + +#define REG_PXP_RX_SIGDET_NOVTH 0x114 +#define G3_ANA_PXP_RX_FE_50OHMS_SEL GENMASK(25, 24) +#define G3_ANA_PXP_RX_SIGDET_VTH_SEL_4_0 GENMASK(20, 16) +#define G3_ANA_PXP_RX_SIGDET_PEAK_1_0 GENMASK(9, 8) + +#define REG_PXP_RX_FE_EQ_HZEN 0x118 +#define G3_ANA_PXP_RX_FE_VB_EQ3_EN BIT(24) +#define G3_ANA_PXP_RX_FE_VB_EQ2_EN BIT(16) +#define G3_ANA_PXP_RX_FE_VB_EQ1_EN BIT(8) + +#define REG_PXP_RX_FE_VCM_GEN_PWDB 0x11c +#define G3_ANA_PXP_RX_FE_VCM_GEN_PWDB BIT(0) + +#define REG_PXP_RX_OSCAL_CTLE2IOS 0x128 +#define G3_ANA_PXP_RX_OSCAL_VGA1VOS GENMASK(29, 24) +#define G3_ANA_PXP_RX_OSCAL_VGA1IOS GENMASK(21, 16) + +#define REG_PXP_RX_OSCAL_VGA2IOS 0x12c +#define G3_ANA_PXP_RX_OSCAL_VGA2IOS GENMASK(5, 0) + +/* G3 PMA */ +#define REG_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c +#define G3_PMA_DISB_RX_SDCAL_EN BIT(0) + +#define REG_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114 +#define G3_PMA_FORCE_RX_SDCAL_EN BIT(0) + +#define REG_SS_RX_CAL_2 0x164 +#define G3_PMA_CAL_OUT_OS GENMASK(11, 8) + +#define REG_SS_RX_SIGDET_0 0x168 +#define G3_PMA_SIGDET_WIN_NONVLD_TIMES GENMASK(28, 24) + +#define REG_SS_TX_RST_B 0x260 +#define G3_PMA_TXCALIB_RST_B BIT(8) +#define G3_PMA_TX_TOP_RST_B BIT(0) + +#define REG_RX_FORCE_MODE_0 0x294 +#define G3_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0) + +#define REG_SS_DA_XPON_PWDB_0 0x34c +#define G3_PMA_DA_XPON_CDR_PR_PWDB BIT(8) + +#define REG_SW_RST_SET 0x460 +#define G3_PMA_SW_XFI_RXPCS_RST_N BIT(8) +#define G3_PMA_SW_TX_FIFO_RST_N BIT(6) +#define G3_PMA_SW_REF_RST_N BIT(5) +#define G3_PMA_SW_ALLPCS_RST_N BIT(4) +#define G3_PMA_SW_PMA_RST_N BIT(3) +#define G3_PMA_SW_TX_RST_N BIT(2) +#define G3_PMA_SW_RX_RST_N BIT(1) +#define G3_PMA_SW_RX_FIFO_RST_N BIT(0) + +#define REG_FORCE_DA_PXP_TX_TERM_SEL 0x77c +#define G3_PMA_FORCE_SEL_DA_PXP_TX_TERM_SEL BIT(8) +#define G3_PMA_FORCE_DA_PXP_TX_TERM_SEL GENMASK(2, 0) + +#define REG_FORCE_DA_PXP_CDR_PR_FLL_COR 0x790 +#define G3_PMA_FORCE_SEL_DA_PXP_RX_DAC_EYE BIT(24) +#define G3_PMA_FORCE_DA_PXP_RX_DAC_EYE GENMASK(22, 16) + +#define REG_FORCE_DA_PXP_CDR_PR_IDAC 0x794 +#define G3_PMA_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW BIT(24) + +#define REG_FORCE_DA_PXP_TXPLL_SDM_PCW 0x798 +#define G3_PMA_FORCE_DA_PXP_TXPLL_SDM_PCW GENMASK(30, 0) + +#define REG_FORCE_DA_PXP_RX_FE_VOS 0x79c +#define G3_PMA_FORCE_SEL_DA_PXP_JCPLL_SDM_PCW BIT(16) + +#define REG_FORCE_DA_PXP_JCPLL_SDM_PCW 0x800 +#define G3_PMA_FORCE_DA_PXP_JCPLL_SDM_PCW GENMASK(30, 0) + +#define REG_FORCE_DA_PXP_CDR_PD_PWDB 0x81c +#define G3_PMA_FORCE_SEL_DA_PXP_CDR_PD_PWDB BIT(8) +#define G3_PMA_FORCE_DA_PXP_CDR_PD_PWDB BIT(0) + +#define REG_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB 0x824 +#define G3_PMA_FORCE_SEL_DA_PXP_CDR_PR_PIEYE_PWDB BIT(8) +#define G3_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB BIT(0) + +#define REG_FORCE_DA_PXP_JCPLL_CKOUT_EN 0x828 +#define G3_PMA_FORCE_SEL_DA_PXP_JCPLL_EN BIT(24) +#define G3_PMA_FORCE_DA_PXP_JCPLL_EN BIT(16) +#define G3_PMA_FORCE_SEL_DA_PXP_JCPLL_CKOUT_EN BIT(8) +#define G3_PMA_FORCE_DA_PXP_JCPLL_CKOUT_EN BIT(0) + +#define REG_FORCE_DA_PXP_RX_SCAN_RST_B 0x84c +#define G3_PMA_FORCE_SEL_DA_PXP_RX_SIGDET_PWDB BIT(24) +#define G3_PMA_FORCE_DA_PXP_RX_SIGDET_PWDB BIT(16) + +#define REG_FORCE_DA_PXP_TXPLL_CKOUT_EN 0x854 +#define G3_PMA_FORCE_SEL_DA_PXP_TXPLL_EN BIT(24) +#define G3_PMA_FORCE_DA_PXP_TXPLL_EN BIT(16) +#define G3_PMA_FORCE_SEL_DA_PXP_TXPLL_CKOUT_EN BIT(8) +#define G3_PMA_FORCE_DA_PXP_TXPLL_CKOUT_EN BIT(0) + +#define REG_SCAN_MODE 0x884 +#define G3_PMA_FORCE_SEL_DA_PXP_JCPLL_KBAND_LOAD_EN BIT(8) +#define G3_PMA_FORCE_DA_PXP_JCPLL_KBAND_LOAD_EN BIT(0) + +#define REG_FORCE_DA_PXP_RX_FE_GAIN_CTRL 0x88c +#define G3_PMA_FORCE_SEL_DA_PXP_RX_FE_GAIN_CTRL BIT(8) +#define G3_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL GENMASK(1, 0) + +#define REG_FORCE_DA_PXP_RX_FE_PWDB 0x894 +#define G3_PMA_FORCE_SEL_DA_PXP_RX_FE_PWDB BIT(8) +#define G3_PMA_FORCE_DA_PXP_RX_FE_PWDB BIT(0) + +#define REG_ADD_DIG_RESERVE_12 0x8b8 +#define G3_PMA_DIG_RESERVE_12_8_8 BIT(8) + +#define REG_ADD_DIG_RESERVE_27 0x908 +#define G3_PMA_DIG_RESERVE_27_16_16 BIT(16) + +#define REG_ADD_DIG_RESERVE_30 0x914 +#define G3_PMA_DIG_RESERVE_30 GENMASK(31, 0) + +#define REG_ADD_DIG_RESERVE_31 0x918 +#define G3_PMA_DIG_RESERVE_31_20_16 GENMASK(20, 16) +#define G3_PMA_DIG_RESERVE_31_12_8 GENMASK(12, 8) +#define G3_PMA_DIG_RESERVE_31_4_0 GENMASK(4, 0) + +#define REG_ADD_DIG_RESERVE_32 0x91c +#define G3_PMA_DIG_RESERVE_32_31_16 GENMASK(31, 16) + +#define REG_ADD_DIG_RESERVE_33 0x920 +#define G3_PMA_DIG_RESERVE_33_31_16 GENMASK(31, 16) +#define G3_PMA_DIG_RESERVE_33_15_0 GENMASK(15, 0) + +#define REG_ADD_DIG_RESERVE_34 0x924 +#define G3_PMA_DIG_RESERVE_34 GENMASK(31, 0) + +#define REG_ADD_DIG_RESERVE_35 0x928 +#define G3_PMA_DIG_RESERVE_35 GENMASK(31, 0) + +#define REG_ADD_DIG_RESERVE_40 0x93c +#define G3_PMA_DIG_RESERVE_40 GENMASK(31, 0) + +#define REG_ADD_DIG_RESERVE_43 0x948 +#define G3_PMA_DIG_RESERVE_43_18_16 GENMASK(18, 16) +#define G3_PMA_DIG_RESERVE_43_14_12 GENMASK(14, 12) +#define G3_PMA_DIG_RESERVE_43_10_8 GENMASK(10, 8) + +/* DTIME */ +#define REG_PCIE_PEXTP_DIG_GLB44 0x0 +#define PCIE_XTP_RXDET_LATCH_STB_T_SEL GENMASK(31, 29) +#define PCIE_XTP_TXPD_RXDET_DONE_CDT BIT(28) +#define PCIE_XTP_TXPD_TX_DATA_EN_DLY GENMASK(27, 24) +#define PCIE_XTP_RXDET_FINISH_STB_T_SEL GENMASK(23, 16) +#define PCIE_XTP_RXDET_EN_STB_T_SEL GENMASK(15, 8) +#define PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL GENMASK(7, 0) + +/* RX AEQ */ +#define REG_PCIE_PEXTP_DIG_LN_RX30 0x0 +#define PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT GENMASK(31, 16) +#define PCIE_XTP_LN_RX_PDOWN_T2RLB_DIG_EN BIT(8) +#define PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT GENMASK(7, 0) + +#endif /* _PHY_AIROHA_PCIE_H */ diff --git a/drivers/phy/airoha/phy-airoha-an7583-pcie.c b/drivers/phy/airo= ha/phy-airoha-an7583-pcie.c new file mode 100644 index 000000000000..ebdab8db9262 --- /dev/null +++ b/drivers/phy/airoha/phy-airoha-an7583-pcie.c @@ -0,0 +1,1069 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 AIROHA Inc + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-airoha-an7583-pcie-regs.h" + +#define FREQ_LOCK_MAX_ATTEMPT 50 + +/* PCIe-PHY initialization time in ms needed by the hw to complete */ +#define PHY_HW_INIT_TIME_MS 30 + +enum an7583_pcie_port_gen { + PCIE_PORT_GEN1 =3D 1, + PCIE_PORT_GEN2, + PCIE_PORT_GEN3, +}; + +/** + * struct an7583_pcie_phy - PCIe phy driver main structure + * @dev: pointer to device + * @phy: pointer to generic phy + * @g3_ana: IO mapped register base address of G3 Analog + * @g3_pma: IO mapped register base address of G3 PMA + * @qp_ana: IO mapped register base address of QPhy Analogc + * @qp_pma: IO mapped register base address of QPhy PMA + * @qp_dig: IO mapped register base address of QPhy Diagnostic + * @xr_dtime: IO mapped register base address of Tx-Rx detection time + * @rx_aeq: IO mapped register base address of Rx AEQ training + */ +struct an7583_pcie_phy { + struct device *dev; + struct phy *phy; + + void __iomem *g3_ana; + void __iomem *g3_pma; + + void __iomem *qp_ana; + void __iomem *qp_pma; + void __iomem *qp_dig; + + void __iomem *xr_dtime; + void __iomem *rx_aeq; +}; + +static void airoha_phy_clear_bits(void __iomem *reg, u32 mask) +{ + u32 val =3D readl(reg) & ~mask; + + writel(val, reg); +} + +static void airoha_phy_set_bits(void __iomem *reg, u32 mask) +{ + u32 val =3D readl(reg) | mask; + + writel(val, reg); +} + +static void airoha_phy_update_bits(void __iomem *reg, u32 mask, u32 val) +{ + u32 tmp =3D readl(reg); + + tmp &=3D ~mask; + tmp |=3D val & mask; + writel(tmp, reg); +} + +#define airoha_phy_update_field(reg, mask, val) \ + do { \ + BUILD_BUG_ON_MSG(!__builtin_constant_p((mask)), \ + "mask is not constant"); \ + airoha_phy_update_bits((reg), (mask), \ + FIELD_PREP((mask), (val))); \ + } while (0) + +#define airoha_g3_ana_clear_bits(pcie_phy, reg, mask) \ + airoha_phy_clear_bits((pcie_phy)->g3_ana + (reg), (mask)) +#define airoha_g3_ana_set_bits(pcie_phy, reg, mask) \ + airoha_phy_set_bits((pcie_phy)->g3_ana + (reg), (mask)) +#define airoha_g3_ana_update_field(pcie_phy, reg, mask, val) \ + airoha_phy_update_field((pcie_phy)->g3_ana + (reg), (mask), (val)) + +#define airoha_g3_pma_write(pcie_phy, reg, val) \ + writel((val), (pcie_phy)->g3_pma + (reg)) +#define airoha_g3_pma_clear_bits(pcie_phy, reg, mask) \ + airoha_phy_clear_bits((pcie_phy)->g3_pma + (reg), (mask)) +#define airoha_g3_pma_set_bits(pcie_phy, reg, mask) \ + airoha_phy_set_bits((pcie_phy)->g3_pma + (reg), (mask)) +#define airoha_g3_pma_update_field(pcie_phy, reg, mask, val) \ + airoha_phy_update_field((pcie_phy)->g3_pma + (reg), (mask), (val)) + +#define airoha_qphy_ana_clear_bits(pcie_phy, reg, mask) \ + airoha_phy_clear_bits((pcie_phy)->qp_ana + (reg), (mask)) +#define airoha_qphy_ana_set_bits(pcie_phy, reg, mask) \ + airoha_phy_set_bits((pcie_phy)->qp_ana + (reg), (mask)) +#define airoha_qphy_ana_update_field(pcie_phy, reg, mask, val) \ + airoha_phy_update_field((pcie_phy)->qp_ana + (reg), (mask), (val)) + +#define airoha_qphy_pma_read(pcie_phy, reg) \ + readl((pcie_phy)->qp_pma + (reg)) +#define airoha_qphy_pma_clear_bits(pcie_phy, reg, mask) \ + airoha_phy_clear_bits((pcie_phy)->qp_pma + (reg), (mask)) +#define airoha_qphy_pma_set_bits(pcie_phy, reg, mask) \ + airoha_phy_set_bits((pcie_phy)->qp_pma + (reg), (mask)) +#define airoha_qphy_pma_update_field(pcie_phy, reg, mask, val) \ + airoha_phy_update_field((pcie_phy)->qp_pma + (reg), (mask), (val)) + +#define airoha_qphy_dig_clear_bits(pcie_phy, reg, mask) \ + airoha_phy_clear_bits((pcie_phy)->qp_dig + (reg), (mask)) +#define airoha_qphy_dig_set_bits(pcie_phy, reg, mask) \ + airoha_phy_set_bits((pcie_phy)->qp_dig + (reg), (mask)) +#define airoha_qphy_dig_update_field(pcie_phy, reg, mask, val) \ + airoha_phy_update_field((pcie_phy)->qp_dig + (reg), (mask), (val)) + +static void an7583_pcie_phy_init_default(struct an7583_pcie_phy *pcie_phy) +{ + /* Load E-Fuse */ + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CMN_EN, + G3_ANA_PXP_CMN_TRIM, 0x10); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TX_TERM_SEL, + G3_PMA_FORCE_SEL_DA_PXP_TX_TERM_SEL); + airoha_g3_pma_update_field(pcie_phy, REG_FORCE_DA_PXP_TX_TERM_SEL, + G3_PMA_FORCE_DA_PXP_TX_TERM_SEL, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_SIGDET_NOVTH, + G3_ANA_PXP_RX_FE_50OHMS_SEL, 0x1); + + /* Default Init */ + airoha_g3_pma_set_bits(pcie_phy, REG_ADD_DIG_RESERVE_12, + G3_PMA_DIG_RESERVE_12_8_8); + airoha_g3_pma_clear_bits(pcie_phy, REG_ADD_DIG_RESERVE_27, + G3_PMA_DIG_RESERVE_27_16_16); + airoha_g3_pma_write(pcie_phy, REG_ADD_DIG_RESERVE_34, 0xcccbcccb); + airoha_g3_pma_write(pcie_phy, REG_ADD_DIG_RESERVE_35, 0xcccb); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_CMN_EN, + G3_ANA_PXP_CMN_EN); +} + +static void an7583_pcie_phy_init_clk_out(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_ana_update_field(pcie_phy, REG_PCIE_CLKTX0_AMP, + G3_ANA_PCIE_CLKTX0_AMP, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PCIE_CLKTX0_AMP, + G3_ANA_PCIE_CLKTX0_OFFSET, 0x2); + airoha_g3_ana_clear_bits(pcie_phy, REG_PCIE_CLKTX0_AMP, + G3_ANA_PXP_PCIE_CLKTX0_HZ); + airoha_g3_ana_update_field(pcie_phy, REG_PCIE_CLKTX0_AMP, + G3_ANA_PXP_PCIE_CLKTX0_IMP_SEL, 0x12); + airoha_g3_ana_update_field(pcie_phy, REG_PCIE_CLKTX0_AMP, + G3_ANA_PCIE_CLKTX0_SR, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_PLL_MONCLK_SEL, + G3_ANA_PXP_PLL_CMN_RESERVE0, 0xD); +} + +static void an7583_pcie_phy_init_ana(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_XFI_RXPCS_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_REF_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_RX_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SS_TX_RST_B, + G3_PMA_TXCALIB_RST_B); + airoha_g3_pma_set_bits(pcie_phy, REG_SS_TX_RST_B, + G3_PMA_TX_TOP_RST_B); +} + +static void an7583_pcie_phy_init_rx(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_write(pcie_phy, REG_ADD_DIG_RESERVE_30, 0x2a00090b); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_CDR_PR_MONPR_EN, + G3_ANA_PXP_CDR_PR_XFICK_EN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_CDR_PD_PICAL_CKD8_INV, + G3_ANA_PXP_CDR_PD_EDGE_DIS); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_PHYCK_DIV, + G3_ANA_PXP_RX_PHYCK_SEL, 0x1); +} + +static void an7583_pcie_phy_init_jcpll(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_EN); + airoha_g3_pma_clear_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_JCPLL_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SPARE_H, + G3_ANA_PXP_JCPLL_SPARE_L, 0x20); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_RST_DLY, + G3_ANA_PXP_JCPLL_PLL_RSTB); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_DELTA, + G3_ANA_PXP_JCPLL_SSC_DELTA, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_TRI_EN, + G3_ANA_PXP_JCPLL_SSC_DELTA1, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_DELTA, + G3_ANA_PXP_JCPLL_SSC_PERIOD, 0x0); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_VCO_TCLVAR, + G3_ANA_PXP_JCPLL_SSC_PHASE_INI); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_SSC_TRI_EN, + G3_ANA_PXP_JCPLL_SSC_TRI_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BR, + G3_ANA_PXP_JCPLL_LPF_BR, 0xA); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BR, + G3_ANA_PXP_JCPLL_LPF_BP, 0xC); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BR, + G3_ANA_PXP_JCPLL_LPF_BC, 0x1F); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BWC, + G3_ANA_PXP_JCPLL_LPF_BWC, 0x1E); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BR, + G3_ANA_PXP_JCPLL_LPF_BWR, 0xA); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_MMD_PREDIV_MODE, + G3_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_MONCK_EN, + G3_ANA_PXP_JCPLL_REFIN_DIV, 0x0); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_FE_VOS, + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_SDM_PCW); + airoha_g3_pma_update_field(pcie_phy, REG_FORCE_DA_PXP_JCPLL_SDM_PCW, + G3_PMA_FORCE_DA_PXP_JCPLL_SDM_PCW, 0x50000000); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_MMD_PREDIV_MODE, + G3_ANA_PXP_JCPLL_POSTDIV_D5); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_MMD_PREDIV_MODE, + G3_ANA_PXP_JCPLL_POSTDIV_D2); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_RST_DLY, + G3_ANA_PXP_JCPLL_RST_DLY, 0x4); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_RST_DLY, + G3_ANA_PXP_JCPLL_SDM_DI_LS, 0x0); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_FREQ_MEAS_EN, + G3_ANA_PXP_JCPLL_VCO_KBAND_MEAS_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_IB_EXT_EN, + G3_ANA_PXP_JCPLL_CHP_IOFST, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_IB_EXT_EN, + G3_ANA_PXP_JCPLL_CHP_IBIAS, 0xC); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_MMD_PREDIV_MODE, + G3_ANA_PXP_JCPLL_MMD_PREDIV_MODE, 0x1); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_VCODIV, + G3_ANA_PXP_JCPLL_VCO_HALFLSB_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_VCODIV, + G3_ANA_PXP_JCPLL_VCO_CFIX, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_VCODIV, + G3_ANA_PXP_JCPLL_VCO_SCAPWR, 0x4); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_IB_EXT_EN, + G3_ANA_PXP_JCPLL_LPF_SHCK_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_KBAND_KFC, + G3_ANA_PXP_JCPLL_POSTDIV_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_KBAND_KFC, + G3_ANA_PXP_JCPLL_KBAND_KFC, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_KBAND_KFC, + G3_ANA_PXP_JCPLL_KBAND_KF, 0x3); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_KBAND_KFC, + G3_ANA_PXP_JCPLL_KBAND_KS, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BWC, + G3_ANA_PXP_JCPLL_KBAND_DIV, 0x1); + airoha_g3_pma_set_bits(pcie_phy, REG_SCAN_MODE, + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_KBAND_LOAD_EN); + airoha_g3_pma_clear_bits(pcie_phy, REG_SCAN_MODE, + G3_PMA_FORCE_DA_PXP_JCPLL_KBAND_LOAD_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_LPF_BWC, + G3_ANA_PXP_JCPLL_KBAND_CODE, 0xE4); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_SDM_HREN, + G3_ANA_PXP_JCPLL_TCL_AMP_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_TCL_CMP_EN, + G3_ANA_PXP_JCPLL_TCL_LPF_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SPARE_H, + G3_ANA_PXP_JCPLL_TCL_KBAND_VREF, 0xF); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SDM_HREN, + G3_ANA_PXP_JCPLL_TCL_AMP_GAIN, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SDM_HREN, + G3_ANA_PXP_JCPLL_TCL_AMP_VREF, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_TCL_CMP_EN, + G3_ANA_PXP_JCPLL_TCL_LPF_BW, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_VCO_TCLVAR, + G3_ANA_PXP_JCPLL_VCO_TCLVAR, 0x3); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_CKOUT_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_JCPLL_CKOUT_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_JCPLL_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_JCPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_JCPLL_EN); +} + +static void an7583_pcie_phy_txpll(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_EN); + airoha_g3_pma_clear_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_TXPLL_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_PLL_RSTB); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SSC_DELTA1, + G3_ANA_PXP_TXPLL_SSC_DELTA, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SSC_DELTA1, + G3_ANA_PXP_TXPLL_SSC_DELTA1, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SSC_PERIOD, + G3_ANA_PXP_TXPLL_SSC_PERIOD, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_CHP_IOFST, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_CHP_IBIAS, 0x2D); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_REFIN_DIV, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_LPF_EN, + G3_ANA_PXP_TXPLL_VCO_CFIX, 0x3); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_IDAC, + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW); + airoha_g3_pma_update_field(pcie_phy, REG_FORCE_DA_PXP_TXPLL_SDM_PCW, + G3_PMA_FORCE_DA_PXP_TXPLL_SDM_PCW, 0xC800000); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_SDM_DI_EN, + G3_ANA_PXP_TXPLL_SDM_IFM); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_SSC_EN, + G3_ANA_PXP_TXPLL_SSC_PHASE_INI); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_RST_DLY, 0x4); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SDM_DI_EN, + G3_ANA_PXP_TXPLL_SDM_DI_LS, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SDM_ORD, + G3_ANA_PXP_TXPLL_SDM_ORD, 0x3); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_TCL_KBAND_VREF, + G3_ANA_PXP_TXPLL_VCO_KBAND_MEAS_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SSC_DELTA1, + G3_ANA_PXP_TXPLL_SSC_DELTA, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_SSC_DELTA1, + G3_ANA_PXP_TXPLL_SSC_DELTA1, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_LPF_BP, + G3_ANA_PXP_TXPLL_LPF_BP, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_LPF_BC, 0x18); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_LPF_BR, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_CHP_IOFST, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_CHP_IBIAS, + G3_ANA_PXP_TXPLL_CHP_IBIAS, 0x2D); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_VTP_EN, + G3_ANA_PXP_TXPLL_SPARE_L, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_LPF_BP, + G3_ANA_PXP_TXPLL_LPF_BWC, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_KS, + G3_ANA_PXP_TXPLL_MMD_PREDIV_MODE, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_REFIN_DIV, 0x0); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_VCO_HALFLSB_EN, + G3_ANA_PXP_TXPLL_VCO_HALFLSB_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_VCO_HALFLSB_EN, + G3_ANA_PXP_TXPLL_VCO_SCAPWR, 0x7); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_LPF_EN, + G3_ANA_PXP_TXPLL_VCO_CFIX, 0x3); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_IDAC, + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_SDM_PCW); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_SSC_EN, + G3_ANA_PXP_TXPLL_SSC_PHASE_INI); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_LPF_BP, + G3_ANA_PXP_TXPLL_LPF_BWR, 0x0); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_REFIN_INTERNAL); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_TCL_KBAND_VREF, + G3_ANA_PXP_TXPLL_VCO_KBAND_MEAS_EN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_VTP_EN, + G3_ANA_PXP_TXPLL_VTP_EN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_PHY_CK1_EN, + G3_ANA_PXP_TXPLL_PHY_CK1_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_REFIN_INTERNAL, + G3_ANA_PXP_TXPLL_REFIN_INTERNAL); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_SSC_EN, + G3_ANA_PXP_TXPLL_SSC_EN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_FREQ_MEAS_EN, + G3_ANA_PXP_TXPLL_LPF_SHCK_EN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_TXPLL_KBAND_KS, + G3_ANA_PXP_TXPLL_POSTDIV_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_CODE, + G3_ANA_PXP_TXPLL_KBAND_KFC, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_CODE, + G3_ANA_PXP_TXPLL_KBAND_KF, 0x3); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_KS, + G3_ANA_PXP_TXPLL_KBAND_KS, 0x1); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_CODE, + G3_ANA_PXP_TXPLL_KBAND_DIV, 0x4); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_KBAND_CODE, + G3_ANA_PXP_TXPLL_KBAND_CODE, 0xE4); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_SDM_ORD, + G3_ANA_PXP_TXPLL_TCL_AMP_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TXPLL_TCL_LPF_EN, + G3_ANA_PXP_TXPLL_TCL_LPF_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_KBAND_VREF, + G3_ANA_PXP_TXPLL_TCL_KBAND_VREF, 0xF); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_AMP_GAIN, + G3_ANA_PXP_TXPLL_TCL_AMP_GAIN, 0x3); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_AMP_GAIN, + G3_ANA_PXP_TXPLL_TCL_AMP_VREF, 0xB); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_TXPLL_TCL_LPF_EN, + G3_ANA_PXP_TXPLL_TCL_LPF_BW, 0x3); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_CKOUT_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_TXPLL_CKOUT_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_SEL_DA_PXP_TXPLL_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_TXPLL_CKOUT_EN, + G3_PMA_FORCE_DA_PXP_TXPLL_EN); +} + +static void an7583_pcie_phy_init_ssc_jcpll(struct an7583_pcie_phy *pcie_ph= y) +{ + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_DELTA, + G3_ANA_PXP_JCPLL_SSC_DELTA, 0x106); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_TRI_EN, + G3_ANA_PXP_JCPLL_SSC_DELTA1, 0x106); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_JCPLL_SSC_DELTA, + G3_ANA_PXP_JCPLL_SSC_PERIOD, 0x31B); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_VCO_TCLVAR, + G3_ANA_PXP_JCPLL_SSC_PHASE_INI); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_VCO_TCLVAR, + G3_ANA_PXP_JCPLL_SSC_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_SDM_IFM, + G3_ANA_PXP_JCPLL_SDM_IFM); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_SDM_HREN, + G3_ANA_PXP_JCPLL_SDM_HREN); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_JCPLL_RST_DLY, + G3_ANA_PXP_JCPLL_SDM_DI_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_JCPLL_SSC_TRI_EN, + G3_ANA_PXP_JCPLL_SSC_TRI_EN); +} + +static void +an7583_pcie_phy_set_rxlan0_signal_detect(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_CDR_PR_TDC_REF_SEL, + G3_ANA_PXP_CDR_PR_LDO_FORCE_ON); + usleep_range(10, 110); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_32, + G3_PMA_DIG_RESERVE_32_31_16, 0x18B0); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_33, + G3_PMA_DIG_RESERVE_33_15_0, 0x18B0); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_33, + G3_PMA_DIG_RESERVE_33_31_16, 0x1030); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_SIGDET_NOVTH, + G3_ANA_PXP_RX_SIGDET_PEAK_1_0, 0x2); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_SIGDET_NOVTH, + G3_ANA_PXP_RX_SIGDET_VTH_SEL_4_0, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_REV_0, + G3_ANA_PXP_RX_REV_1_3_2, 0x2); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_DAC_RANGE, + G3_ANA_PXP_RX_SIGDET_LPF_CTRL, 0x1); + airoha_g3_pma_update_field(pcie_phy, REG_SS_RX_CAL_2, + G3_PMA_CAL_OUT_OS, 0x0); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_FE_VCM_GEN_PWDB, + G3_ANA_PXP_RX_FE_VCM_GEN_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_FE_GAIN_CTRL, + G3_PMA_FORCE_SEL_DA_PXP_RX_FE_GAIN_CTRL); + airoha_g3_pma_update_field(pcie_phy, REG_FORCE_DA_PXP_RX_FE_GAIN_CTRL, + G3_PMA_FORCE_DA_PXP_RX_FE_GAIN_CTRL, 0x3); + airoha_g3_pma_update_field(pcie_phy, REG_RX_FORCE_MODE_0, + G3_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL, 0x1); + airoha_g3_pma_update_field(pcie_phy, REG_SS_RX_SIGDET_0, + G3_PMA_SIGDET_WIN_NONVLD_TIMES, 0x3); + airoha_g3_pma_clear_bits(pcie_phy, REG_RX_CTRL_SEQUENCE_DISB_CTRL_1, + G3_PMA_DISB_RX_SDCAL_EN); + airoha_g3_pma_set_bits(pcie_phy, REG_RX_CTRL_SEQUENCE_FORCE_CTRL_1, + G3_PMA_FORCE_RX_SDCAL_EN); + usleep_range(100, 200); + airoha_g3_pma_clear_bits(pcie_phy, REG_RX_CTRL_SEQUENCE_FORCE_CTRL_1, + G3_PMA_FORCE_RX_SDCAL_EN); +} + +static void an7583_pcie_phy_set_rxflow(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_SCAN_RST_B, + G3_PMA_FORCE_SEL_DA_PXP_RX_SIGDET_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_SCAN_RST_B, + G3_PMA_FORCE_DA_PXP_RX_SIGDET_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PD_PWDB, + G3_PMA_FORCE_SEL_DA_PXP_CDR_PD_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PD_PWDB, + G3_PMA_FORCE_DA_PXP_CDR_PD_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_FE_PWDB, + G3_PMA_FORCE_SEL_DA_PXP_RX_FE_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_RX_FE_PWDB, + G3_PMA_FORCE_DA_PXP_RX_FE_PWDB); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_PHYCK_DIV, + G3_ANA_PXP_RX_TDC_CK_SEL); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_PHYCK_DIV, + G3_ANA_PXP_RX_PHYCK_RSTB); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_TX_FIFO_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_ALLPCS_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_PMA_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_TX_RST_N); + airoha_g3_pma_set_bits(pcie_phy, REG_SW_RST_SET, + G3_PMA_SW_RX_FIFO_RST_N); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_FE_EQ_HZEN, + G3_ANA_PXP_RX_FE_VB_EQ3_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_FE_EQ_HZEN, + G3_ANA_PXP_RX_FE_VB_EQ2_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_RX_FE_EQ_HZEN, + G3_ANA_PXP_RX_FE_VB_EQ1_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_REV_0, + G3_ANA_PXP_RX_REV_1_6_4, 0x4); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_REV_0, + G3_ANA_PXP_RX_REV_1_10_8, 0x4); +} + +static void an7583_pcie_phy_set_pr(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_VREG_IBAND_VAL, + G3_ANA_PXP_CDR_PR_VREG_IBAND_VAL_2_0, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_VREG_IBAND_VAL, + G3_ANA_PXP_CDR_PR_VREG_CKBUF_VAL_2_0, 0x5); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_CKREF_DIV, + G3_ANA_PXP_CDR_PR_CKREF_DIV_1_0, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_TDC_REF_SEL, + G3_ANA_PXP_CDR_PR_CKREF_DIV1_1_0, 0x0); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_LPF_RATIO, + G3_ANA_PXP_CDR_LPF_TOP_LIM, 0x20000); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_BETA_DAC, + G3_ANA_PXP_CDR_PR_BETA_SEL, 0x2); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_BETA_DAC, + G3_ANA_PXP_CDR_PR_KBAND_DIV, 0x4); +} + +static void an7583_pcie_phy_set_txflow(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TX_CKLDO_EN, + G3_ANA_PXP_TX_CKLDO_EN); + airoha_g3_ana_set_bits(pcie_phy, REG_PXP_TX_CKLDO_EN, + G3_ANA_PXP_TX_DMEDGEGEN_EN); +} + +static void an7583_pcie_phy_set_rx_mode(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_write(pcie_phy, REG_ADD_DIG_RESERVE_40, 0x804000); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_31, + G3_PMA_DIG_RESERVE_31_4_0, 0x5); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_31, + G3_PMA_DIG_RESERVE_31_12_8, 0x5); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_31, + G3_PMA_DIG_RESERVE_31_20_16, 0x5); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_43, + G3_PMA_DIG_RESERVE_43_10_8, 0x7); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_43, + G3_PMA_DIG_RESERVE_43_14_12, 0x7); + airoha_g3_pma_update_field(pcie_phy, REG_ADD_DIG_RESERVE_43, + G3_PMA_DIG_RESERVE_43_18_16, 0x7); + airoha_g3_ana_clear_bits(pcie_phy, REG_PXP_CDR_PR_MONCK_EN, + G3_ANA_PXP_CDR_PR_MONCK_EN); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_CDR_PR_MONCK_EN, + G3_ANA_PXP_CDR_PR_RESERVE0, 0x2); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_OSCAL_CTLE2IOS, + G3_ANA_PXP_RX_OSCAL_VGA1IOS, 0x19); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_OSCAL_CTLE2IOS, + G3_ANA_PXP_RX_OSCAL_VGA1VOS, 0x19); + airoha_g3_ana_update_field(pcie_phy, REG_PXP_RX_OSCAL_VGA2IOS, + G3_ANA_PXP_RX_OSCAL_VGA2IOS, 0x14); +} + +static void an7583_pcie_phy_set_eye_scan(struct an7583_pcie_phy *pcie_phy) +{ + airoha_g3_pma_update_field(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_FLL_COR, + G3_PMA_FORCE_DA_PXP_RX_DAC_EYE, 0x0); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_FLL_COR, + G3_PMA_FORCE_SEL_DA_PXP_RX_DAC_EYE); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB, + G3_PMA_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB); + airoha_g3_pma_set_bits(pcie_phy, REG_FORCE_DA_PXP_CDR_PR_PIEYE_PWDB, + G3_PMA_FORCE_SEL_DA_PXP_CDR_PR_PIEYE_PWDB); + airoha_g3_pma_clear_bits(pcie_phy, REG_SS_DA_XPON_PWDB_0, + G3_PMA_DA_XPON_CDR_PR_PWDB); +} + +static void an7583_pcie_phy_tx_pll_disable(struct an7583_pcie_phy *pcie_ph= y) +{ + /* TX Force Disable */ + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_6, + QP_PMA_DA_QP_TX_DATA_EN_FORCE); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_6, + QP_PMA_DA_QP_TX_DATA_EN_SEL); + + /* PLL Force Unstable (For PMA) */ + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_1, + QP_PMA_PLL_FORCE_UNSTABLE); + + /* PLL Disable */ + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_0, + QP_PMA_PHYA_AUTO_INIT); + usleep_range(1000, 2000); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_0, + QP_PMA_PHYA_AUTO_INIT); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_FORCE); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_SEL); +} + +static void an7583_pcie_phy_tx_pll_enable(struct an7583_pcie_phy *pcie_phy) +{ + /* PLL Reset to default */ + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_MONVC_EN); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_MON_LDO_SEL, 0x0); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_SEL); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_FORCE); + + /* PLL Auto Mode (For PMA) */ + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_1, + QP_PMA_PLL_FORCE_UNSTABLE); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_1, + QP_PMA_PLL_FORCE_STABLE); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CK_CTRL_1, + QP_PMA_PLL_FORCE_UNSTABLE); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CK_CTRL_1, + QP_PMA_PLL_FORCE_STABLE); + + /* TX Auto Mode */ + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_6, + QP_PMA_DA_QP_TX_DATA_EN_FORCE); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_6, + QP_PMA_DA_QP_TX_DATA_EN_SEL); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_6, + QP_PMA_DA_QP_TX_DATA_EN_FORCE); +} + +static void an7583_pcie_phy_init_pll_kband_flow(struct an7583_pcie_phy *pc= ie_phy) +{ + airoha_qphy_pma_set_bits(pcie_phy, REG_RX_CTRL_36, + QP_PMA_QP_PCIE_USB_SYSTEM); + + /* 50Mhz XTAL */ + airoha_qphy_ana_update_field(pcie_phy, REG_QP_BGR_EN, + QP_ANA_QP_BG_DIV, 0x1); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_PREDIV, 0x1); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_4, + QP_PMA_DA_QP_PLL_ICOLP_EN_INTF); + airoha_qphy_dig_clear_bits(pcie_phy, REG_QP_CK_RST_CTRL_7, + QP_DIG_MULTI_PHY_USB5_EN); + airoha_qphy_dig_clear_bits(pcie_phy, REG_QP_CK_RST_CTRL_7, + QP_DIG_MULTI_PHY_USB2P5_EN); + airoha_qphy_dig_set_bits(pcie_phy, REG_QP_CK_RST_CTRL_7, + QP_DIG_MULTI_PHY_USB_MODE_EN); + airoha_qphy_dig_set_bits(pcie_phy, REG_QP_CK_RST_CTRL_7, + QP_DIG_MULTI_PHY_USB5_EN); + airoha_qphy_dig_set_bits(pcie_phy, REG_QP_CK_RST_CTRL_7, + QP_DIG_MULTI_PHY_USB2P5_EN); + + /* PLL RG */ + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_PCK_SEL_INTF); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_IR_INTF, 0x4); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_FBKSEL_INTF, 0x0); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_KBAND_PREDIV_INTF, 0x0); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_BC_INTF, 0x3); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_BPA_INTF, 0x5); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_BPB_INTF, 0x1); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_ICOIQ_EN_INTF); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_PHY_CK_EN_INTF); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_4, + QP_PMA_DA_QP_PLL_SDM_HREN_INTF, 0x1); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_SDM_IFM_INTF); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_3, + QP_PMA_DA_QP_PLL_SSC_DELTA_INTF, 0x1FD); + airoha_qphy_pma_update_field(pcie_phy, REG_PLL_CTRL_3, + QP_PMA_DA_QP_PLL_SSC_PERIOD_INTF, 0x19C); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_1, + QP_PMA_QP_PLL_SSC_EN); + airoha_qphy_pma_update_field(pcie_phy, REG_SS_LCPLL_TDC_PCW_1, + QP_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON, 0x48000000); + airoha_qphy_pma_update_field(pcie_phy, REG_SS_LCPLL_PWCTL_SETTING_2, + QP_PMA_NCPO_ANA_MSB, 0x1); + airoha_qphy_pma_update_field(pcie_phy, REG_SS_LCPLL_TDC_FLT_2, + QP_PMA_LCPLL_NCPO_VALUE, 0x48000000); + + /* RX RG */ + airoha_qphy_ana_update_field(pcie_phy, REG_QP_CDR_LPF_MJV_LIM, + QP_ANA_QP_CDR_LPF_RATIO, 0x1); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_RXAFE_RESERVE, + QP_ANA_QP_CDR_PD_10B_EN); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_CDR_PR_CKREF_DIV1, + QP_ANA_QP_CDR_PR_DAC_BAND, 0xC); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_CDR_FORCE_IBANDLPF_R_OFF, + QP_ANA_QP_CDR_PHYCK_RSTB); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_CDR_PR_KBAND_DIV_PCIE, + QP_ANA_QP_CDR_PR_XFICK_EN); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_CDR_PR_KBAND_DIV_PCIE, + QP_ANA_QP_CDR_PR_KBAND_PCIE_MODE); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_CDR_PR_CKREF_DIV1, + QP_ANA_QP_CDR_PR_KBAND_DIV, 0x3); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_CDR_PR_KBAND_DIV_PCIE, + QP_ANA_QP_CDR_PR_KBAND_DIV_PCIE, 0x19); + + /* Init L0/L0S U0/U1 */ + airoha_qphy_pma_set_bits(pcie_phy, REG_RX_CTRL_46, + QP_PMA_QP_PCIE_USB_BYPASS_EQ_P1_TO_P0_EN); + airoha_qphy_pma_set_bits(pcie_phy, REG_RX_CTRL_46, + QP_PMA_REBACK_P0_LCK2REF_EN); + airoha_qphy_pma_set_bits(pcie_phy, REG_RX_CTRL_11, + QP_PMA_QP_FORCE_SIGDET_5G); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_36, + QP_PMA_QP_LCK2DATA_DLY_TIME_9_0, 0x2); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_RXAFE_RESERVE, + QP_ANA_QP_CDR_PD_EDGE_DIS); + + /* PI Calibration */ + airoha_qphy_pma_update_field(pcie_phy, REG_RX_DLY_0, + QP_PMA_QP_RX_PI_CAL_EN_H_DLY, 0x10); + + /* CRS detect and CLK TRX Control */ + airoha_qphy_pma_set_bits(pcie_phy, REG_RX_CTRL_10, + QP_PMA_QP_CRSDET_RSTB); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_PLL_SDM_ORD, + QP_ANA_QP_PLL_SSC_PHASE_INI); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_PLL_SDM_ORD, + QP_ANA_QP_PLL_SSC_TRI_EN); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CK_CTRL_0, + QP_PMA_DA_PCIE_CLKRX_EN_INTF); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_0, + QP_PMA_DA_PCIE_CLKTX_EN_INTF); + airoha_qphy_ana_clear_bits(pcie_phy, REG_PCIE_CLKDRV_IMPSEL, + QP_ANA_PCIE_CLKDRV_HZ); + airoha_qphy_ana_update_field(pcie_phy, REG_PCIE_CLKDRV_IMPSEL, + QP_ANA_PCIE_CLKDRV_AMP, 0x4); + airoha_qphy_ana_update_field(pcie_phy, REG_PCIE_CLKDRV_IMPSEL, + QP_ANA_PCIE_CLKDRV_FORCEIN, 0x1); + airoha_qphy_ana_update_field(pcie_phy, REG_PCIE_CLKDRV_IMPSEL, + QP_ANA_PCIE_CLKDRV_IMPSEL, 0x12); + airoha_qphy_ana_update_field(pcie_phy, REG_PCIE_CLKDRV_IMPSEL, + QP_ANA_PCIE_CLKDRV_RP, 0xC); + airoha_qphy_pma_update_field(pcie_phy, REG_QP_TX_DA_CTRL_3, + QP_PMA_TX_DATA_RATE_SEL, 0x1); + + /* Common Setting */ + airoha_qphy_dig_set_bits(pcie_phy, REG_QP_CK_RST_CTRL_3, + QP_DIG_US_CK_DIV_SEL); + airoha_qphy_dig_set_bits(pcie_phy, REG_QP_CK_RST_CTRL_3, + QP_DIG_NS_CK_DIV_SEL); + airoha_qphy_pma_update_field(pcie_phy, REG_QP_TX_DA_CTRL_0, + QP_PMA_RXDET_EN_WINDOW, 0xA); + airoha_qphy_pma_update_field(pcie_phy, REG_QP_TX_DA_CTRL_0, + QP_PMA_RXDET_RD_WAIT_TIMER, 0x4); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_RXLBTX_EN, + QP_ANA_QP_TX_RXDET_METHOD); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_RXLBTX_EN, + QP_ANA_QP_TX_DMEDGEGEN_EN); + + /* PLL auto ON/OFF at L2/U3 state */ + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_2, + QP_PMA_PCIE_MODE_PLL_AUTO_EN); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_2, + QP_PMA_PCIE_MODE_PLL_AUTO_ON_EN); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CK_CTRL_2, + QP_PMA_PCIE_MODE_PLL_AUTO_OFF_EN); + + /* RX speed up */ + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_5, + QP_PMA_FREDET_CHK_CYCLE, 0x28); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_6, + QP_PMA_FREDET_GOLDEN_CYCLE, 0x64); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_7, + QP_PMA_FREDET_TOLERATE_CYCLE, 0x2710); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_2, + QP_PMA_QP_RX_EQ_EN_H_DLY, 0x9C4); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_45, + QP_PMA_QP_EQ_EN_DLY, 0x9C4); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_50, + QP_PMA_QP_RX_EQ_EN_H_DLY_SHORT, 0x9C4); + airoha_qphy_pma_update_field(pcie_phy, REG_RX_CTRL_50, + QP_PMA_QP_EQ_EN_DLY_SHORT, 0x9C4); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_TX_MODE_16B_EN, + QP_ANA_QP_TX_RESERVE_8); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PON_RXFEDIG_CTRL_0, + QP_PMA_QP_EQ_RX500M_CK_SEL); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_0, + QP_PMA_PHYA_AUTO_INIT); + + /* Select PLL_EN to Force mode */ + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_FORCE); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_SEL); +} + +static bool an7583_pcie_phy_kband_is_calibrated(struct an7583_pcie_phy *pc= ie_phy) +{ + u32 val, res; + + mdelay(50); /* TODO */ + + /* Read PLL KBand Code */ + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_4, + QP_PMA_DA_QP_PLL_ICOLP_EN_INTF); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_BGR_EN, + QP_ANA_QP_BIAS_V2V_CAL, 0x15); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_LDOLPF_VSEL, 0x1); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_OSCAL_ENB); + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_RICO_SEL_INTF); + airoha_qphy_pma_update_field(pcie_phy, REG_INTF_CTRL_8, + QP_PMA_DA_QP_XTAL_EXT_EN_FORCE, 0x0); + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_8, + QP_PMA_DA_QP_XTAL_EXT_EN_SEL); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_ICOIQ_EN_INTF); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_TDC_FT_CK_EN, + QP_ANA_QP_PLL_DEBUG_SEL); + + mdelay(5); /* TODO */ + + val =3D airoha_qphy_pma_read(pcie_phy, REG_INTF_STS_9); + res =3D FIELD_GET(QP_PMA_ADDR_INTF_STS_PLL_VCOCAL, val) << 4; + + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_TDC_FT_CK_EN, + QP_ANA_QP_PLL_DEBUG_SEL); + + mdelay(5); /* TODO */ + + val =3D airoha_qphy_pma_read(pcie_phy, REG_INTF_STS_9); + res |=3D val; + + /* + * KBand is calibrated if KBand Code is NOT 0xfff and + * KBand Done is set. + */ + return res !=3D 0xfff && res & 0x800; +} + +static void an7583_pcie_phy_kband_calibrate(struct an7583_pcie_phy *pcie_p= hy) +{ + /* PLL Disable */ + airoha_qphy_pma_clear_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_FORCE); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_SEL); + + /* PLL Config for CPR */ + airoha_qphy_pma_set_bits(pcie_phy, REG_PLL_CTRL_4, + QP_PMA_DA_QP_PLL_ICOLP_EN_INTF); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_BGR_EN, + QP_ANA_QP_BIAS_V2V_CAL, 0x0); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_LDOLPF_VSEL, 0x3); + airoha_qphy_ana_clear_bits(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_OSCAL_ENB); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_RICO_SEL_INTF); + airoha_qphy_pma_update_field(pcie_phy, REG_INTF_CTRL_8, + QP_PMA_DA_QP_XTAL_EXT_EN_FORCE, 0x3); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_8, + QP_PMA_DA_QP_XTAL_EXT_EN_SEL); + airoha_qphy_pma_clear_bits(pcie_phy, REG_PLL_CTRL_2, + QP_PMA_DA_QP_PLL_ICOIQ_EN_INTF); + airoha_qphy_ana_set_bits(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_MONVC_EN); + airoha_qphy_ana_update_field(pcie_phy, REG_QP_PLL_IPLL_DIG_PWR_SEL, + QP_ANA_QP_PLL_MON_LDO_SEL, 0x3); + + /* PLL Enable */ + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_FORCE); + airoha_qphy_pma_set_bits(pcie_phy, REG_INTF_CTRL_7, + QP_PMA_DA_QP_PLL_EN_SEL); +} + +static void an7583_pcie_phy_init_qphy(struct an7583_pcie_phy *pcie_phy) +{ + int i; + + an7583_pcie_phy_tx_pll_disable(pcie_phy); + + an7583_pcie_phy_init_pll_kband_flow(pcie_phy); + + /* Try to calibrate KBand up to FREQ_LOCK_MAX_ATTEMPT times */ + for (i =3D 0; i < FREQ_LOCK_MAX_ATTEMPT; i++) { + /* Check if KBand is calibrated */ + if (an7583_pcie_phy_kband_is_calibrated(pcie_phy)) + break; + + /* Trigger KBand calibration */ + an7583_pcie_phy_kband_calibrate(pcie_phy); + } + + an7583_pcie_phy_tx_pll_enable(pcie_phy); +} + +static int an7583_pcie_phy_init(struct phy *phy) +{ + struct an7583_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + u32 val; + + /* Setup Tx-Rx detection time */ + val =3D FIELD_PREP(PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL, 0x33) | + FIELD_PREP(PCIE_XTP_RXDET_EN_STB_T_SEL, 0x1) | + FIELD_PREP(PCIE_XTP_RXDET_FINISH_STB_T_SEL, 0x2) | + FIELD_PREP(PCIE_XTP_TXPD_TX_DATA_EN_DLY, 0x3) | + FIELD_PREP(PCIE_XTP_RXDET_LATCH_STB_T_SEL, 0x1); + writel(val, pcie_phy->xr_dtime + REG_PCIE_PEXTP_DIG_GLB44); + + /* Setup Rx AEQ training time */ + val =3D FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT, 0x32) | + FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT, 0x5050); + writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30); + + an7583_pcie_phy_init_default(pcie_phy); + an7583_pcie_phy_init_clk_out(pcie_phy); + an7583_pcie_phy_init_ana(pcie_phy); + + usleep_range(50, 100); + + an7583_pcie_phy_init_rx(pcie_phy); + + /* phase 1, no ssc for K TXPLL */ + an7583_pcie_phy_init_jcpll(pcie_phy); + + usleep_range(200, 300); + + /* TX PLL settings */ + an7583_pcie_phy_txpll(pcie_phy); + + usleep_range(200, 300); + + /* SSC JCPLL setting */ + an7583_pcie_phy_init_ssc_jcpll(pcie_phy); + + usleep_range(30, 130); + + /* Rx lan0 signal detect */ + an7583_pcie_phy_set_rxlan0_signal_detect(pcie_phy); + + /* RX FLOW */ + an7583_pcie_phy_set_rxflow(pcie_phy); + + usleep_range(50, 200); + + an7583_pcie_phy_set_pr(pcie_phy); + + /* TX FLOW */ + an7583_pcie_phy_set_txflow(pcie_phy); + + usleep_range(50, 200); + + /* RX mode setting */ + an7583_pcie_phy_set_rx_mode(pcie_phy); + + an7583_pcie_phy_set_eye_scan(pcie_phy); + + usleep_range(50, 200); + + airoha_g3_pma_set_bits(pcie_phy, REG_SS_DA_XPON_PWDB_0, + G3_PMA_DA_XPON_CDR_PR_PWDB); + + usleep_range(100, 200); + + an7583_pcie_phy_init_qphy(pcie_phy); + + /* Wait for the PCIe PHY to complete initialization before returning */ + msleep(PHY_HW_INIT_TIME_MS); + + return 0; +} + +static const struct phy_ops an7583_pcie_phy_ops =3D { + .init =3D an7583_pcie_phy_init, + .owner =3D THIS_MODULE, +}; + +static int an7583_pcie_phy_probe(struct platform_device *pdev) +{ + struct an7583_pcie_phy *pcie_phy; + struct device *dev =3D &pdev->dev; + struct phy_provider *provider; + + pcie_phy =3D devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); + if (!pcie_phy) + return -ENOMEM; + + pcie_phy->g3_ana =3D devm_platform_ioremap_resource_byname(pdev, "g3-ana"= ); + if (IS_ERR(pcie_phy->g3_ana)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->g3_ana), + "Failed to map g3 ANA base\n"); + + pcie_phy->g3_pma =3D devm_platform_ioremap_resource_byname(pdev, "g3-pma"= ); + if (IS_ERR(pcie_phy->g3_pma)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->g3_pma), + "Failed to map g3 PMA base\n"); + + pcie_phy->qp_ana =3D devm_platform_ioremap_resource_byname(pdev, "qp-ana"= ); + if (IS_ERR(pcie_phy->qp_ana)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->qp_ana), + "Failed to map QP ANA base\n"); + + pcie_phy->qp_pma =3D devm_platform_ioremap_resource_byname(pdev, "qp-pma"= ); + if (IS_ERR(pcie_phy->qp_pma)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->qp_pma), + "Failed to map QP PMA base\n"); + + pcie_phy->qp_dig =3D devm_platform_ioremap_resource_byname(pdev, "qp-dig"= ); + if (IS_ERR(pcie_phy->qp_dig)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->qp_dig), + "Failed to map QP Dig base\n"); + + pcie_phy->phy =3D devm_phy_create(dev, dev->of_node, &an7583_pcie_phy_ops= ); + if (IS_ERR(pcie_phy->phy)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), + "Failed to create PCIe phy\n"); + + pcie_phy->xr_dtime =3D + devm_platform_ioremap_resource_byname(pdev, "xr-dtime"); + if (IS_ERR(pcie_phy->xr_dtime)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->xr_dtime), + "Failed to map Tx-Rx dtime base\n"); + + pcie_phy->rx_aeq =3D devm_platform_ioremap_resource_byname(pdev, "rx-aeq"= ); + if (IS_ERR(pcie_phy->rx_aeq)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq), + "Failed to map Rx AEQ base\n"); + + pcie_phy->dev =3D dev; + phy_set_drvdata(pcie_phy->phy, pcie_phy); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return dev_err_probe(dev, PTR_ERR(provider), + "PCIe phy probe failed\n"); + + return 0; +} + +static const struct of_device_id an7583_pcie_phy_of_match[] =3D { + { .compatible =3D "airoha,an7583-pcie-phy" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an7583_pcie_phy_of_match); + +static struct platform_driver an7583_pcie_phy_driver =3D { + .probe =3D an7583_pcie_phy_probe, + .driver =3D { + .name =3D "airoha-an7583-pcie-phy", + .of_match_table =3D an7583_pcie_phy_of_match, + }, +}; +module_platform_driver(an7583_pcie_phy_driver); + +MODULE_DESCRIPTION("Airoha AN7583 PCIe PHY driver"); +MODULE_AUTHOR("Christian Marangi "); +MODULE_LICENSE("GPL"); --=20 2.48.1