From nobody Fri Dec 19 20:55:28 2025 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AB1828AAE9; Fri, 6 Jun 2025 15:44:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749224688; cv=none; b=Hy9T9c0m5OCjlN4/WIFaZ8lCxpXAx9SISn6p+m5Jsl+QWG4rOwoya0AZd+d6o8Kzox/ZBkL46kPWhKAs/efJWQw+MVNiT0CxqJqyn6zyzYKgt0lhyPSzPHaPwFcnFBFRempftHAHHfNuLMJbgMJIYBbYzVGcZu9jqaDBZD+LV/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749224688; c=relaxed/simple; bh=bejcWE6MQotWr+1JFHVSPWJJJKLq7InC7Ch4izqVrXg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FNYuMeJTPOk3873knxMnDJgoafD08jV5UGxKAF3VcXSjUHvoX3Ud07hZOA4xfBX+qvAv1g4AX8PtpBUxa1SXGFaNPcAnLRTMpont8D1Qf1OcCguDGt8TBRYm3KToMceTsLOOrIklsrFk9kkjkOuPMsxS/loZbQUDO4QaZz8PaMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=ovxbnmE2; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="ovxbnmE2" Received: from isaac-ThinkPad-T16-Gen-2.localdomain (cpc90716-aztw32-2-0-cust408.18-1.cable.virginm.net [86.26.101.153]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id EE79B8DB; Fri, 6 Jun 2025 17:44:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1749224679; bh=bejcWE6MQotWr+1JFHVSPWJJJKLq7InC7Ch4izqVrXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ovxbnmE2VtCRNGFFn6Y/Y28e3TS0gul1iMWvBZ0oTl7cf9sUFP6M+uI4eLle45qJD vHIbnvVtJMTg79zG+VAXFXoq5ys84rNlNsoSH25B0ne0nApxLYHFTSILfc22ie+Bwg IwkOYYkr3ztwgBG/8xH20EflANXJ3CyfACzuTVo4= From: Isaac Scott To: laurent.pinchart@ideasonboard.com Cc: kieran.bingham@ideasonboard.com, rmfrfs@gmail.com, martink@posteo.de, kernel@puri.sm, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Isaac Scott Subject: [PATCH v2 1/2] media: platform: Refactor interrupt status registers Date: Fri, 6 Jun 2025 16:44:13 +0100 Message-ID: <20250606154414.540290-2-isaac.scott@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250606154414.540290-1-isaac.scott@ideasonboard.com> References: <20250606154414.540290-1-isaac.scott@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP i.MX 8 MP CSI-2 receiver features multiple interrupt and debug status sources which span multiple registers. The driver currently supports two interrupt source registers, and attributes the mipi_csis_event event entries to those registers through a boolean debug field that indicate if the event relates to the main interrupt status (false) or debug interrupt status (true) register. To make it easier to add new event fields, replace the debug bool with a 'status index' integer than indicates the index of the corresponding status register. Signed-off-by: Isaac Scott Reviewed-by: Laurent Pinchart Reviewed-by: Rui Miguel Silva --- Changes since v1: - Switched from magic numbers to enum. --- drivers/media/platform/nxp/imx-mipi-csis.c | 69 +++++++++++----------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index d060eadebc7a..394987d72c64 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -248,8 +248,13 @@ #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) =20 +enum mipi_csis_event_type { + MAIN =3D 0, + DEBUG =3D 1, +}; + struct mipi_csis_event { - bool debug; + enum mipi_csis_event_type status_index; u32 mask; const char * const name; unsigned int counter; @@ -257,30 +262,30 @@ struct mipi_csis_event { =20 static const struct mipi_csis_event mipi_csis_events[] =3D { /* Errors */ - { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, - { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, - { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" = }, - { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, - { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, - { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, - { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, - { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, + { MAIN, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error"}, + { MAIN, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported= "}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start"}, /* Non-image data receive events */ - { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even fram= e" }, - { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame"= }, - { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame"= }, - { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, + { MAIN, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even fram= e"}, + { MAIN, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame"= }, + { MAIN, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame"= }, + { MAIN, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame"}, /* Frame start/end */ - { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, - { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, - { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, - { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, + { MAIN, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start"}, + { MAIN, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge"}, + { DEBUG, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge"}, }; =20 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) @@ -765,32 +770,30 @@ static irqreturn_t mipi_csis_irq_handler(int irq, voi= d *dev_id) struct mipi_csis_device *csis =3D dev_id; unsigned long flags; unsigned int i; - u32 status; - u32 dbg_status; + u32 status[2]; =20 - status =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); - dbg_status =3D mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); + status[MAIN] =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); + status[DEBUG] =3D mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); =20 spin_lock_irqsave(&csis->slock, flags); =20 /* Update the event/error counters */ - if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { + if ((status[MAIN] & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { for (i =3D 0; i < MIPI_CSIS_NUM_EVENTS; i++) { struct mipi_csis_event *event =3D &csis->events[i]; =20 - if ((!event->debug && (status & event->mask)) || - (event->debug && (dbg_status & event->mask))) + if (status[event->status_index] & event->mask) event->counter++; } } =20 - if (status & MIPI_CSIS_INT_SRC_FRAME_START) + if (status[MAIN] & MIPI_CSIS_INT_SRC_FRAME_START) mipi_csis_queue_event_sof(csis); =20 spin_unlock_irqrestore(&csis->slock, flags); =20 - mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); - mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); + mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status[MAIN]); + mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, status[DEBUG]); =20 return IRQ_HANDLED; } --=20 2.43.0 From nobody Fri Dec 19 20:55:28 2025 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C6028DF3B; Fri, 6 Jun 2025 15:44:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749224690; cv=none; b=bg4VJtx8be1g9LHmYWVmiKLq8FU2EmsTO6eZsdpulo/sOTDobWxVIxGwBIM1ZGqIurEudYlNWMhxm2GhWrU6Dq+1cotlxObJ3G5xBoPxIX3DDmSqzuoXwTuswsVBdllzOnlM99jAB4ZLVB1f3ViiZNjC/pGHkIgSxNORJuWZUGQ= ARC-Message-Signature: i=1; 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Fri, 6 Jun 2025 17:44:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1749224683; bh=JufAzRLKwdF7p6LD7Zi2lXLBjYvC7TdfCa99ZsqFE1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d4cS8iDY9Vay0JBQwOMtv9K2pq35drIUecmkmGPsRZbivIF+wpunE7NXSyov4EQjD AIkzTQq1ToL7EFqzbkWKy3odfGc+FRfO2ByARpL/ZeJxdUwQxCZLzpCyjFEaMFCTu7 4TJ7w2ABB/PsNZuGGt5bJRy/N39iVKavOYNAnV2k= From: Isaac Scott To: laurent.pinchart@ideasonboard.com Cc: kieran.bingham@ideasonboard.com, rmfrfs@gmail.com, martink@posteo.de, kernel@puri.sm, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Isaac Scott Subject: [PATCH v2 2/2] media: platform: Add user line interrupt to imx-mipi-csis driver Date: Fri, 6 Jun 2025 16:44:14 +0100 Message-ID: <20250606154414.540290-3-isaac.scott@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250606154414.540290-1-isaac.scott@ideasonboard.com> References: <20250606154414.540290-1-isaac.scott@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP i.MX 8M Plus features an interrupt that triggers after the MIPI CSI receiver counts a user-configurable number of lines. This is useful for debugging, as it allows users to check if the amount of lines per frame equals what they are expecting. Add support for this interrupt in the driver, and an entry into debugfs to allow the user to configure whether the interrupt is enabled, as well as the number of lines after which to trigger the interrupt. This debugfs control can be altered while a stream is in progress, with 0 disabling the interrupt and >0 setting a new desired line count. Signed-off-by: Isaac Scott Reviewed-by: Rui Miguel Silva --- Changes since v1: - Moved from magic number to enum in status_index - Clear INT_MSK_1 in enable_interrupts() when on =3D=3D false - use local variable in set_params() as in the interrupt handler - move interrupt handling code outside of spinlock --- drivers/media/platform/nxp/imx-mipi-csis.c | 40 +++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/pla= tform/nxp/imx-mipi-csis.c index 394987d72c64..1b71f6c19fa8 100644 --- a/drivers/media/platform/nxp/imx-mipi-csis.c +++ b/drivers/media/platform/nxp/imx-mipi-csis.c @@ -88,6 +88,10 @@ #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) =20 +/* CSIS Interrupt mask 1 */ +#define MIPI_CSIS_INT_MSK_1 0x18 +#define MIPI_CSIS_INT_MSK_1_LINE_END BIT(0) + /* CSIS Interrupt source */ #define MIPI_CSIS_INT_SRC 0x14 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) @@ -109,6 +113,10 @@ #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff =20 +/* CSIS Interrupt source 1 */ +#define MIPI_CSIS_INT_SRC_1 0x1c +#define MIPI_CSIS_INT_SRC_1_LINE_END BIT(0) + /* D-PHY status control */ #define MIPI_CSIS_DPHY_STATUS 0x20 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) @@ -221,6 +229,7 @@ #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) =20 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) +#define MIPI_CSIS_LINE_INTERRUPT_RATIO(n) (0x0110 + (n) * 4) =20 /* Non-image packet data buffers */ #define MIPI_CSIS_PKTDATA_ODD 0x2000 @@ -251,6 +260,7 @@ enum mipi_csis_event_type { MAIN =3D 0, DEBUG =3D 1, + USER =3D 2, }; =20 struct mipi_csis_event { @@ -286,6 +296,8 @@ static const struct mipi_csis_event mipi_csis_events[] = =3D { { MAIN, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End"}, { DEBUG, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge"}, { DEBUG, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge"}, + /* User Line interrupt */ + { USER, MIPI_CSIS_INT_SRC_1_LINE_END, "Line End"} }; =20 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) @@ -338,11 +350,14 @@ struct mipi_csis_device { =20 spinlock_t slock; /* Protect events */ struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; + struct dentry *debugfs_root; struct { bool enable; u32 hs_settle; u32 clk_settle; + u32 int_line; + u32 last_int_line; } debug; }; =20 @@ -533,6 +548,8 @@ static void mipi_csis_enable_interrupts(struct mipi_csi= s_device *csis, bool on) { mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); + mipi_csis_write(csis, MIPI_CSIS_INT_MSK_1, + on ? MIPI_CSIS_INT_MSK_1_LINE_END : 0); } =20 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) @@ -655,6 +672,7 @@ static void mipi_csis_set_params(struct mipi_csis_devic= e *csis, const struct csis_pix_format *csis_fmt) { int lanes =3D csis->bus.num_data_lanes; + u32 int_lines; u32 val; =20 val =3D mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); @@ -691,6 +709,13 @@ static void mipi_csis_set_params(struct mipi_csis_devi= ce *csis, MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); =20 + int_lines =3D READ_ONCE(csis->debug.int_line); + if (int_lines > 0) + mipi_csis_write(csis, MIPI_CSIS_LINE_INTERRUPT_RATIO(0), + max(int_lines, 1U) - 1); + + csis->debug.last_int_line =3D int_lines; + /* Update the shadow register. */ val =3D mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, @@ -770,10 +795,12 @@ static irqreturn_t mipi_csis_irq_handler(int irq, voi= d *dev_id) struct mipi_csis_device *csis =3D dev_id; unsigned long flags; unsigned int i; - u32 status[2]; + u32 int_lines; + u32 status[3]; =20 status[MAIN] =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC); status[DEBUG] =3D mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); + status[USER] =3D mipi_csis_read(csis, MIPI_CSIS_INT_SRC_1); =20 spin_lock_irqsave(&csis->slock, flags); =20 @@ -792,8 +819,16 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void= *dev_id) =20 spin_unlock_irqrestore(&csis->slock, flags); =20 + int_lines =3D READ_ONCE(csis->debug.int_line); + if (int_lines !=3D csis->debug.last_int_line) { + mipi_csis_write(csis, MIPI_CSIS_LINE_INTERRUPT_RATIO(0), + max(int_lines, 1U) - 1); + csis->debug.last_int_line =3D int_lines; + } + mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status[MAIN]); mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, status[DEBUG]); + mipi_csis_write(csis, MIPI_CSIS_INT_SRC_1, status[USER]); =20 return IRQ_HANDLED; } @@ -933,6 +968,7 @@ static void mipi_csis_debugfs_init(struct mipi_csis_dev= ice *csis) { csis->debug.hs_settle =3D UINT_MAX; csis->debug.clk_settle =3D UINT_MAX; + csis->debug.int_line =3D 0; =20 csis->debugfs_root =3D debugfs_create_dir(dev_name(csis->dev), NULL); =20 @@ -944,6 +980,8 @@ static void mipi_csis_debugfs_init(struct mipi_csis_dev= ice *csis) &csis->debug.clk_settle); debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, &csis->debug.hs_settle); + debugfs_create_u32("int_line_0", 0600, csis->debugfs_root, + &csis->debug.int_line); } =20 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) --=20 2.43.0