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([140.113.216.168]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7482b0c1168sm1296798b3a.136.2025.06.06.06.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 06:48:12 -0700 (PDT) From: Kuan-Wei Chiu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, akpm@linux-foundation.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, jserv@ccns.ncku.edu.tw, Kuan-Wei Chiu , Yu-Chun Lin Subject: [PATCH v3 3/3] riscv: Optimize gcd() performance on RISC-V without Zbb extension Date: Fri, 6 Jun 2025 21:47:58 +0800 Message-Id: <20250606134758.1308400-4-visitorckw@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250606134758.1308400-1-visitorckw@gmail.com> References: <20250606134758.1308400-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The binary GCD implementation uses FFS (find first set), which benefits from hardware support for the ctz instruction, provided by the Zbb extension on RISC-V. Without Zbb, this results in slower software-emulated behavior. Previously, RISC-V always used the binary GCD, regardless of actual hardware support. This patch improves runtime efficiency by disabling the efficient_ffs_key static branch when Zbb is either not enabled in the kernel (config) or not supported on the executing CPU. This selects the odd-even GCD implementation, which is faster in the absence of efficient FFS. This change ensures the most suitable GCD algorithm is chosen dynamically based on actual hardware capabilities. Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Signed-off-by: Kuan-Wei Chiu Acked-by: Alexandre Ghiti --- arch/riscv/kernel/setup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index f7c9a1caa83e..785c7104fde7 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include =20 #include #include @@ -361,6 +363,9 @@ void __init setup_arch(char **cmdline_p) =20 riscv_user_isa_enable(); riscv_spinlock_init(); + + if (!IS_ENABLED(CONFIG_RISCV_ISA_ZBB) || !riscv_isa_extension_available(N= ULL, ZBB)) + static_branch_disable(&efficient_ffs_key); } =20 bool arch_cpu_is_hotpluggable(int cpu) --=20 2.34.1