From nobody Fri Dec 19 19:18:44 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAFC020330; Fri, 6 Jun 2025 13:10:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215438; cv=none; b=Dy53dWpL1MgQTZ6Cx8/BuQTOkalx3XAKx5gy4PBTYONIx0TR6HNuJrt9UxvZOfSii7VjsRaaKz0+PolGJ38/+u0zu/vKiSyZxQtkayqhh8zA7rMKbt5LsFJZSKZjUsG9r81UZHaPKZPJUdSfb8/ztuZIuv1qQ5rlZrLNYhGyfn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215438; c=relaxed/simple; bh=37z7SKqOfqgqoDLNZYBJd8RKrqH73AtwnVrwoq/OZNM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hOQfhx9FOBF2zt07ooRDFQjbivPz4WPH70CsI2RJMDXQnS+umZtg4xQ1PZf8P9Ou34xQehFxsMAPq8cbSpj8/B15cPT/G0dIdCgcR6BtOxV7+N5baYQrPalCjw6+yT5hBWfyEaxEe3f1CuVM2Gi772/5p0Cg6gTCabXigCyi8UY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan. (unknown [IPv6:2605:59c0:20f3:a400:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 9A0E2B4C4432; Fri, 6 Jun 2025 15:04:19 +0200 (CEST) From: E Shattow To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski , Rob Herring , Conor Dooley , E Shattow Subject: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC Date: Fri, 6 Jun 2025 06:02:36 -0700 Message-ID: <20250606130253.1105273-2-e@freeshell.de> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606130253.1105273-1-e@freeshell.de> References: <20250606130253.1105273-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document bindings for the JH7110 SoC DMC as implemented in downstream U-Boot driver starfive_ddr.c Signed-off-by: E Shattow --- .../starfive,jh7110-dmc.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/st= arfive,jh7110-dmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,= jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/star= five,jh7110-dmc.yaml new file mode 100644 index 000000000000..299c86893db1 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-= dmc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow + +description: + JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll1_out + + clock-frequency: + enum: [2133, 2800] + default: 2133 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - clock-frequency + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll1_out"; + clock-frequency =3D <2133>; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + }; --=20 2.49.0 From nobody Fri Dec 19 19:18:44 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7BF41E3787; Fri, 6 Jun 2025 13:04:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215071; cv=none; b=KkFb2lIjQ9n0wojPix2vfkeEx5I1fO1c0bTUZL59fWar969SG/E42QyXpviWPwBHnp0snlHyzoOeGL9nBxpWbySeo+Zz+EYJHY4toAGGqmYo4GGC/l/8QcdGsWzAZeJlDsQT1E+jZCJ91OYav90XW4oCrVms75RyzXlhhQ9jAlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215071; c=relaxed/simple; bh=qdo417o10JodKd/lScCqNLCBp2CwkQFotTyj/nq4oHQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cLLtLrFjQGj7OWIhWB4aRhg2yuyoAcOmVFKT8jc8RwsnWa2fF78oNNJqLVDSrCC1KN3EXAU7H0MFmn62LjdLI69WEXSesr24KTckvRNrj4AZK+C8gxXXTCLVFX1/aBdk9PlGibx0AN8Qmv/G1dNb3JBjJTdsKkrB+uzo/2IFTBg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan. (unknown [IPv6:2605:59c0:20f3:a400:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id DB8AAB4C4438; Fri, 6 Jun 2025 15:04:24 +0200 (CEST) From: E Shattow To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: E Shattow Subject: [PATCH v1 2/3] riscv: dts: starfive: jh7110: add memory controller node Date: Fri, 6 Jun 2025 06:02:37 -0700 Message-ID: <20250606130253.1105273-3-e@freeshell.de> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606130253.1105273-1-e@freeshell.de> References: <20250606130253.1105273-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" add memory controller node used downstream by U-Boot boot loader. Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 0ba74ef04679..6fdeac3e0aff 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -372,6 +372,19 @@ ccache: cache-controller@2010000 { cache-unified; }; =20 + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll1_out"; + clock-frequency =3D <2133>; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + plic: interrupt-controller@c000000 { compatible =3D "starfive,jh7110-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; --=20 2.49.0 From nobody Fri Dec 19 19:18:44 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C97931E3787; Fri, 6 Jun 2025 13:04:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215078; cv=none; b=kmFU6nd7D28dX5+8Ed6YNqLnL0aM2Tu1VuPdYdHGfQhX9KinhhMsRz7G9gH5XQHn+5hIvG7FZva58dmgUXfZzIiD/6iU1yym5L1+WJo3XqwFKkMyhxrw5/JhBMeUnDSKqB+bsOWiT1+qiQrSVrCAkmTL8TfY6udj7gcp6p4oRJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749215078; c=relaxed/simple; bh=jTSNMcwQcnd09ekHunIb6JTUWDhAjp5JQVTJVZEc7Gc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rnXmjoldg8ovEOXqJUxDCCNoqL2x8CTH4RnHeuiC3Iu6oasf2Myv9dUyjUYvHHP5yYJtYwMJsh0teyRrz4Nny+pD04pNh5rUaYWPCZ4f6eNCQJJu/rUfLJopIHqm0jQdJsvBAgEhoVXQsuXWMcp4r4qAbINz6+b10MtIVo0wNz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan. (unknown [IPv6:2605:59c0:20f3:a400:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 6810BB4C4439; Fri, 6 Jun 2025 15:04:31 +0200 (CEST) From: E Shattow To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: E Shattow Subject: [PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader Date: Fri, 6 Jun 2025 06:02:38 -0700 Message-ID: <20250606130253.1105273-4-e@freeshell.de> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250606130253.1105273-1-e@freeshell.de> References: <20250606130253.1105273-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - core local interrupt timer - DDR memory controller - oscillator - syscrg clock-controller Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 6fdeac3e0aff..8a56e8b91b61 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -35,6 +35,7 @@ S7_0: cpu@0 { =20 cpu0_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -68,6 +69,7 @@ U74_1: cpu@1 { =20 cpu1_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -101,6 +103,7 @@ U74_2: cpu@2 { =20 cpu2_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -134,6 +137,7 @@ U74_3: cpu@3 { =20 cpu3_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -167,6 +171,7 @@ U74_4: cpu@4 { =20 cpu4_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock { =20 osc: oscillator { compatible =3D "fixed-clock"; + bootph-pre-ram; clock-output-names =3D "osc"; #clock-cells =3D <0>; }; @@ -354,6 +360,7 @@ soc { clint: timer@2000000 { compatible =3D "starfive,jh7110-clint", "sifive,clint0"; reg =3D <0x0 0x2000000 0x0 0x10000>; + bootph-pre-ram; interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -376,6 +383,7 @@ memory-controller@15700000 { compatible =3D "starfive,jh7110-dmc"; reg =3D <0x0 0x15700000 0x0 0x10000>, <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names =3D "pll1_out"; clock-frequency =3D <2133>; @@ -893,6 +901,7 @@ qspi: spi@13010000 { syscrg: clock-controller@13020000 { compatible =3D "starfive,jh7110-syscrg"; reg =3D <0x0 0x13020000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, --=20 2.49.0