From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6F41288502 for ; Fri, 6 Jun 2025 12:05:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749211561; cv=none; b=iYWqfGHC0yTzC3LrZnyyiIavh77FMtKPQZrSsc86DVIy7ObeHsDfY9OJJ9hrHdINcn2CkZV1LR1lEKnim2qhq9x0OxjGm+ziKTqDWx17+eP32hWRT5pbcLwPI43KCzAo+qBlLj/HGzwu88Lw59gMyV2ezEfLGrXdqrSKUQPk78E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749211561; c=relaxed/simple; bh=ZyUHJK8E9KfN3/ahCH3y7p+3sEISjtxi7gtR12w3ZUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TwFvSnbNvUtej3+ptdnuOFYe7S7+n/svrHr8yOJfddti6SR4Zcjel8Z98dnGK2pvdBlin1lWFpbnxFp7uneXGiYbj9nKX4vCZ5yyzPMW3Es6wnW7JwU2IiVetVqmmEBN6HLyKYrH1uccHFFWAqWL3y6xXDECEf7pxC3PTNEMEu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=EJICvPO+; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="EJICvPO+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749211558; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7zgUFcNjP45KVFN7fvEt+xKxva7ecAlvU3lfLilVE+Q=; b=EJICvPO+iybMkK+nB6Ub67ZgW3HlRNZk/JmBdJ4lZyaDQuJxgkC98Ys7BjrtZjdC0SOVtx 25oglDsxXWXZzTXayEYJMfiqtMrar2K2SauooPNGVlTDa/L+79IArt2C4eV+9oQzu58HcZ Bi28EtS6NNtOdqSlpVrYzEsBzhiAtfA= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-399-P-GhgdoFNSuMb05AmqCiKA-1; Fri, 06 Jun 2025 08:05:52 -0400 X-MC-Unique: P-GhgdoFNSuMb05AmqCiKA-1 X-Mimecast-MFC-AGG-ID: P-GhgdoFNSuMb05AmqCiKA_1749211549 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3B3B6180045B; Fri, 6 Jun 2025 12:05:49 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id BA96A18003FD; Fri, 6 Jun 2025 12:05:40 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 1/9] drm/i915/fbdev: Add intel_fbdev_get_map() Date: Fri, 6 Jun 2025 13:48:05 +0200 Message-ID: <20250606120519.753928-2-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" The vaddr of the fbdev framebuffer is private to the struct intel_fbdev, so this function is needed to access it for drm_panic. Also the struct i915_vma is different between i915 and xe, so it requires a few functions to access fbdev->vma->iomap. Signed-off-by: Jocelyn Falempe --- v2: * Add intel_fb_get_vaddr() and i915_vma_get_iomap() to build with Xe drive= r. =20 v4: * rename to get_map(), and return the struct iosys_map mapping. * implement the Xe variant. drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fb_pin.h | 2 ++ drivers/gpu/drm/i915/display/intel_fbdev.c | 5 +++++ drivers/gpu/drm/i915/display/intel_fbdev.h | 6 +++++- drivers/gpu/drm/i915/i915_vma.h | 5 +++++ drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++++ 6 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/= i915/display/intel_fb_pin.c index 98a61a7b0b93..b792e9b062d8 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -334,3 +334,8 @@ void intel_plane_unpin_fb(struct intel_plane_state *old= _plane_state) intel_dpt_unpin_from_ggtt(fb->dpt_vm); } } + +void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) +{ + iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma)); +} diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/= i915/display/intel_fb_pin.h index 01770dbba2e0..81ab79da1af7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -12,6 +12,7 @@ struct drm_framebuffer; struct i915_vma; struct intel_plane_state; struct i915_gtt_view; +struct iosys_map; =20 struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, @@ -27,5 +28,6 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned lo= ng flags); int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); +void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map); =20 #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i= 915/display/intel_fbdev.c index 2dc4029d71ed..7c4709d58aa3 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -512,3 +512,8 @@ struct i915_vma *intel_fbdev_vma_pointer(struct intel_f= bdev *fbdev) { return fbdev ? fbdev->vma : NULL; } + +void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map) +{ + intel_fb_get_map(fbdev->vma, map); +} diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i= 915/display/intel_fbdev.h index a15e3e222a0c..150cc5f45bb3 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -13,6 +13,7 @@ struct drm_fb_helper_surface_size; struct intel_display; struct intel_fbdev; struct intel_framebuffer; +struct iosys_map; =20 #ifdef CONFIG_DRM_FBDEV_EMULATION int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, @@ -22,7 +23,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *= helper, void intel_fbdev_setup(struct intel_display *display); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbde= v); struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); - +void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map); #else #define INTEL_FBDEV_DRIVER_OPS \ .fbdev_probe =3D NULL @@ -39,6 +40,9 @@ static inline struct i915_vma *intel_fbdev_vma_pointer(st= ruct intel_fbdev *fbdev return NULL; } =20 +static inline void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct i= osys_map *map) +{ +} #endif =20 #endif /* __INTEL_FBDEV_H__ */ diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vm= a.h index 6a6be8048aa8..4ae610927fa7 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -353,6 +353,11 @@ static inline bool i915_node_color_differs(const struc= t drm_mm_node *node, return drm_mm_node_allocated(node) && node->color !=3D color; } =20 +static inline void __iomem *i915_vma_get_iomap(struct i915_vma *vma) +{ + return READ_ONCE(vma->iomap); +} + /** * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the apert= ure * @vma: VMA to iomap diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/di= splay/xe_fb_pin.c index 461ecdfdb742..ac9a5ba363b2 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -465,3 +465,8 @@ u64 intel_dpt_offset(struct i915_vma *dpt_vma) { return 0; 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Fri, 6 Jun 2025 12:05:56 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 358D918002A5; Fri, 6 Jun 2025 12:05:49 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 2/9] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Fri, 6 Jun 2025 13:48:06 +0200 Message-ID: <20250606120519.753928-3-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index a2a6d52be0a5..b183270bf934 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -903,6 +903,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported_async =3D intel_plane_format_mod_supported_async, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct intel_display *display =3D to_intel_display(plane); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + u32 dspcntr; + u32 reg; + + dspcntr =3D intel_de_read_fw(display, DSPCNTR(display, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); + + if (DISPLAY_VER(display) >=3D 4) { + reg =3D intel_de_read_fw(display, DSPSURF(display, i9xx_plane)); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg); + + } else { + reg =3D intel_de_read_fw(display, DSPADDR(display, i9xx_plane)); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg); + } +} + struct intel_plane * intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { @@ -1045,6 +1066,8 @@ intel_primary_plane_create(struct intel_display *disp= lay, enum pipe pipe) } } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILIN= G_X); =20 if (DISPLAY_VER(display) >=3D 5 || display->platform.g4x) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index ed4d743fc7c5..3654d88e9c5f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1517,6 +1517,8 @@ struct intel_plane { bool async_flip); void (*enable_flip_done)(struct intel_plane *plane); void (*disable_flip_done)(struct intel_plane *plane); + /* For drm_panic */ + void (*disable_tiling)(struct intel_plane *plane); }; =20 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state= , base) --=20 2.49.0 From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29F0E288538 for ; Fri, 6 Jun 2025 12:06:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749211572; cv=none; b=ETKPmf+M65LlUG+kwx6QX60ReAn+tm0nUsK5v3u8MHA5HIsTNgNje2czUHBR9+kykBswXvN1EhKi0KcYzbZYUTvKx9QjC9OG9s3NDhJfPN9rUtwevT5HEzUop2F7fowYvOVEfbIMQMgfxy6ntuoGNl8N+BWnZl/9ge0TFj6w4wI= ARC-Message-Signature: i=1; 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Fri, 6 Jun 2025 12:06:02 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id EE2C318002A5; Fri, 6 Jun 2025 12:05:56 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 3/9] drm/i915/display: Add a disable_tiling() for skl planes Date: Fri, 6 Jun 2025 13:48:07 +0200 Message-ID: <20250606120519.753928-4-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index c7b336359a5e..ffcf50443c0c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2791,6 +2791,25 @@ static u8 tgl_plane_caps(struct intel_display *displ= ay, return caps; } =20 +static void skl_disable_tiling(struct intel_plane *plane) +{ + struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); + struct intel_display *display =3D to_intel_display(plane); + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + u32 plane_ctl; + + plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + + intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); + + intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), + skl_plane_surf(state, 0)); +} + struct intel_plane * skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) @@ -2837,6 +2856,7 @@ skl_universal_plane_create(struct intel_display *disp= lay, plane->max_height =3D skl_plane_max_height; plane->min_cdclk =3D skl_plane_min_cdclk; } + plane->disable_tiling =3D skl_disable_tiling; =20 if (DISPLAY_VER(display) >=3D 13) plane->max_stride =3D adl_plane_max_stride; --=20 2.49.0 From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D948288517 for ; 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charset="utf-8" If the ttm bo is backed by pages, then it's possible to safely kmap one page at a time, using kmap_try_from_panic(). Unfortunately there is no way to do the same with ioremap, so it only supports the kmap case. This is needed for proper drm_panic support with xe driver. Signed-off-by: Jocelyn Falempe --- v8: * Added in v8 drivers/gpu/drm/ttm/ttm_bo_util.c | 27 +++++++++++++++++++++++++++ include/drm/ttm/ttm_bo.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo= _util.c index 15cab9bda17f..9c3f3b379c2a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -377,6 +377,33 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *b= o, return (!map->virtual) ? -ENOMEM : 0; } =20 +/** + * + * ttm_bo_kmap_try_from_panic + * + * @bo: The buffer object + * @page: The page to map + * + * Sets up a kernel virtual mapping using kmap_local_page_try_from_panic(). + * This can safely be called from the panic handler, if you make sure the = bo + * is the one being displayed, so is properly allocated, and won't be modi= fied. + * + * Returns the vaddr, that you can use to write to the bo, and that you sh= ould + * pass to kunmap_local() when you're done with this page, or NULL if the = bo + * is in iomem. + */ +void *ttm_bo_kmap_try_from_panic(struct ttm_buffer_object *bo, unsigned lo= ng page) +{ + if (page + 1 > PFN_UP(bo->resource->size)) + return NULL; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Implement both functions for i915 and xe, they prepare the work for drm_panic support. They both use kmap_try_from_panic(), and map one page at a time, to write the panic screen on the framebuffer. Signed-off-by: Jocelyn Falempe --- v5: * Use iosys_map for intel_bo_panic_map(). v7: * Return int for i915_gem_object_panic_map() (Ville Syrj=C3=A4l=C3=A4) v8: * Complete rewrite, to use kmap_try_from_panic() which is safe to call from a panic handler drivers/gpu/drm/i915/display/intel_bo.c | 11 +++ drivers/gpu/drm/i915/display/intel_bo.h | 3 + drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 92 ++++++++++++++++++++++ drivers/gpu/drm/xe/display/intel_bo.c | 55 +++++++++++++ 5 files changed, 165 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915= /display/intel_bo.c index fbd16d7b58d9..83dbd8ae16fe 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT /* Copyright =C2=A9 2024 Intel Corporation */ =20 +#include #include "gem/i915_gem_mman.h" #include "gem/i915_gem_object.h" #include "gem/i915_gem_object_frontbuffer.h" @@ -57,3 +58,13 @@ void intel_bo_describe(struct seq_file *m, struct drm_ge= m_object *obj) { i915_debugfs_describe_obj(m, to_intel_bo(obj)); } + +int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb) +{ + return i915_gem_object_panic_setup(to_intel_bo(obj), sb); +} + +void intel_bo_panic_finish(struct drm_gem_object *obj) +{ + return i915_gem_object_panic_finish(to_intel_bo(obj)); +} diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915= /display/intel_bo.h index ea7a2253aaa5..9ac087ea275d 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -4,6 +4,7 @@ #ifndef __INTEL_BO__ #define __INTEL_BO__ =20 +#include #include =20 struct drm_gem_object; @@ -23,5 +24,7 @@ struct intel_frontbuffer *intel_bo_set_frontbuffer(struct= drm_gem_object *obj, struct intel_frontbuffer *front); =20 void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj); +int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb); +void intel_bo_panic_finish(struct drm_gem_object *obj); =20 #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index c34f41605b46..9a0c1019dcad 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include "intel_memory_region.h" #include "i915_gem_object_types.h" @@ -691,6 +692,9 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object = *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 +int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb); +void i915_gem_object_panic_finish(struct drm_i915_gem_object *obj); + /** * i915_gem_object_pin_map - return a contiguous mapping of the entire obj= ect * @obj: the object to map into kernel address space diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 7f83f8bdc8fb..9bdbac3d9433 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -3,6 +3,7 @@ * Copyright =C2=A9 2014-2016 Intel Corporation */ =20 +#include #include #include =20 @@ -354,6 +355,97 @@ static void *i915_gem_object_map_pfn(struct drm_i915_g= em_object *obj, return vaddr ?: ERR_PTR(-ENOMEM); } =20 +static struct page **i915_panic_pages; +static int i915_panic_page =3D -1; +static void *i915_panic_vaddr; + +static void i915_panic_kunmap(void) +{ + if (i915_panic_vaddr) { + drm_clflush_virt_range(i915_panic_vaddr, PAGE_SIZE); + kunmap_local(i915_panic_vaddr); + i915_panic_vaddr =3D NULL; + } +} + +static struct page **i915_gem_object_panic_pages(struct drm_i915_gem_objec= t *obj) +{ + unsigned long n_pages =3D obj->base.size >> PAGE_SHIFT, i; + struct page *page; + struct page **pages; + struct sgt_iter iter; + + pages =3D kvmalloc_array(n_pages, sizeof(*pages), GFP_ATOMIC); + if (!pages) + return NULL; + + i =3D 0; + for_each_sgt_page(page, iter, obj->mm.pages) + pages[i++] =3D page; + return pages; +} + +/* + * The scanout buffer pages are not mapped, so for each pixel, + * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. + * Try to keep the map from the previous pixel, to avoid too much map/unma= p. + */ +static void i915_gem_object_panic_page_set_pixel(struct drm_scanout_buffer= *sb, unsigned int x, + unsigned int y, u32 color) +{ + unsigned int new_page; + unsigned int offset; + + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + + new_page =3D offset >> PAGE_SHIFT; + offset =3D offset % PAGE_SIZE; + if (new_page !=3D i915_panic_page) { + i915_panic_kunmap(); + i915_panic_page =3D new_page; + i915_panic_vaddr =3D kmap_local_page_try_from_panic( + i915_panic_pages[i915_panic_page]); + } + if (i915_panic_vaddr) { + u32 *pix =3D i915_panic_vaddr + offset; + *pix =3D color; + } +} + +/* + * Setup the gem framebuffer for drm_panic access. + * Use current vaddr if it exists, or setup a list of pages. + * pfn is not supported yet. + */ +int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb) +{ + enum i915_map_type has_type; + void *ptr; + + ptr =3D page_unpack_bits(obj->mm.mapping, &has_type); + if (ptr) { + if (i915_gem_object_has_iomem(obj)) + iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)ptr); + else + iosys_map_set_vaddr(&sb->map[0], ptr); + + return 0; + } + if (i915_gem_object_has_struct_page(obj)) { + i915_panic_pages =3D i915_gem_object_panic_pages(obj); + sb->set_pixel =3D i915_gem_object_panic_page_set_pixel; + i915_panic_page =3D -1; + return 0; + } + return -EOPNOTSUPP; +} + +void i915_gem_object_panic_finish(struct drm_i915_gem_object *obj) +{ + i915_panic_kunmap(); + i915_panic_page =3D -1; +} + /* get, pin, and map the pages of the object into kernel space */ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, enum i915_map_type type) diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index 27437c22bd70..eb9a3400c110 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT /* Copyright =C2=A9 2024 Intel Corporation */ =20 +#include #include =20 #include "xe_bo.h" @@ -59,3 +60,57 @@ void intel_bo_describe(struct seq_file *m, struct drm_ge= m_object *obj) { /* FIXME */ } + +static int xe_panic_page =3D -1; +static void *xe_panic_vaddr; +static struct xe_bo *xe_panic_bo; + +static void xe_panic_kunmap(void) +{ + if (xe_panic_vaddr) { + drm_clflush_virt_range(xe_panic_vaddr, PAGE_SIZE); + kunmap_local(xe_panic_vaddr); + xe_panic_vaddr =3D NULL; + } +} +/* + * The scanout buffer pages are not mapped, so for each pixel, + * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. + * Try to keep the map from the previous pixel, to avoid too much map/unma= p. + */ +static void xe_panic_page_set_pixel(struct drm_scanout_buffer *sb, unsigne= d int x, + unsigned int y, u32 color) +{ + unsigned int new_page; + unsigned int offset; + + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + + new_page =3D offset >> PAGE_SHIFT; + offset =3D offset % PAGE_SIZE; + if (new_page !=3D xe_panic_page) { + xe_panic_kunmap(); + xe_panic_page =3D new_page; + xe_panic_vaddr =3D ttm_bo_kmap_try_from_panic(&xe_panic_bo->ttm, + xe_panic_page); + } + if (xe_panic_vaddr) { + u32 *pix =3D xe_panic_vaddr + offset; + *pix =3D color; + } +} + +int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb) +{ + struct xe_bo *bo =3D gem_to_xe_bo(obj); + + xe_panic_bo =3D bo; + sb->set_pixel =3D xe_panic_page_set_pixel; + return 0; +} + +void intel_bo_panic_finish(struct drm_gem_object *obj) +{ + xe_panic_kunmap(); + xe_panic_page =3D -1; +} --=20 2.49.0 From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55699288C03 for ; Fri, 6 Jun 2025 12:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749211600; cv=none; b=Sz07PSnj64QQW+qoqKkCyoBK2F5gPPh23ZEjaQrFfcbsEH3j4mp8lcCU/XtuPomLCw5Twa7Zxke1+531qo2M08d261Tu52EU+LekDsQYksa2QrTsEvufM9twj9IZ8wBrwfKt2ZYBB6HzglOTMkMZ1zF147SeLCVf0C5wamb5cnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749211600; c=relaxed/simple; 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Fri, 6 Jun 2025 12:06:31 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8240918003FD; Fri, 6 Jun 2025 12:06:26 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 6/9] drm/i915/display: Add drm_panic support Date: Fri, 6 Jun 2025 13:48:10 +0200 Message-ID: <20250606120519.753928-7-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" This adds drm_panic support for a wide range of Intel GPU. I've tested it only on 4 laptops, Haswell (with 128MB of eDRAM), Comet Lake, Raptor Lake, and Lunar Lake. For hardware using DPT, it's not possible to disable tiling, as you will need to reconfigure the way the GPU is accessing the framebuffer, so this will be handled by the following patches. Signed-off-by: Jocelyn Falempe --- v4: * Add support for Xe driver. =20 v6: * Use struct intel_display instead of drm_i915_private for intel_atomic_pl= ane.c =20 v7: * Fix mismatch {} in intel_panic_flush() (Jani Nikula) v8: * Use intel_bo_panic_setup() and intel_bo_panic_finish(). .../gpu/drm/i915/display/intel_atomic_plane.c | 82 ++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 15ede7678636..4095d69924db 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -33,19 +33,23 @@ =20 #include #include +#include =20 #include #include #include +#include #include #include #include +#include =20 #include "gem/i915_gem_object.h" #include "i915_scheduler_types.h" #include "i915_vma.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" +#include "intel_bo.h" #include "intel_cdclk.h" #include "intel_cursor.h" #include "intel_display_rps.h" @@ -53,6 +57,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_fbdev.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -1266,14 +1271,89 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 + +static void intel_panic_flush(struct drm_plane *plane) +{ + struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct intel_plane *iplane =3D to_intel_plane(plane); + struct intel_display *display =3D to_intel_display(iplane); + struct drm_framebuffer *fb =3D plane_state->hw.fb; + struct drm_gem_object *obj; + + obj =3D intel_fb_bo(fb); + + intel_bo_panic_finish(obj); + + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer= .*/ + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(display->fbde= v.fbdev)) { + struct iosys_map map; + + intel_fbdev_get_map(display->fbdev.fbdev, &map); + drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height); + return; + } + + if (fb->modifier && iplane->disable_tiling) + iplane->disable_tiling(iplane); +} + +static int intel_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct intel_plane_state *plane_state; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct intel_display *display =3D to_intel_display(plane->dev); + + if (!plane->state || !plane->state->fb || !plane->state->visible) + return -ENODEV; + + plane_state =3D to_intel_plane_state(plane->state); + fb =3D plane_state->hw.fb; + obj =3D intel_fb_bo(fb); + if (!obj) + return -ENODEV; + + if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(display->fbde= v.fbdev)) { + intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); + } else { + int ret; + /* Can't disable tiling if DPT is in use */ + if (intel_fb_uses_dpt(fb)) + return -EOPNOTSUPP; + ret =3D intel_bo_panic_setup(obj, sb); + if (ret) + return ret; + } + sb->width =3D fb->width; + sb->height =3D fb->height; + /* Use the generic linear format, because tiling, RC, CCS, CC + * will be disabled in disable_tiling() + */ + sb->format =3D drm_format_info(fb->format->format); + sb->pitch[0] =3D fb->pitches[0]; + + return 0; +} + static const struct drm_plane_helper_funcs intel_plane_helper_funcs =3D { .prepare_fb =3D intel_prepare_plane_fb, .cleanup_fb =3D intel_cleanup_plane_fb, }; =20 +static const struct drm_plane_helper_funcs intel_primary_plane_helper_func= s =3D { + .prepare_fb =3D intel_prepare_plane_fb, + .cleanup_fb =3D intel_cleanup_plane_fb, + .get_scanout_buffer =3D intel_get_scanout_buffer, + .panic_flush =3D intel_panic_flush, +}; + void intel_plane_helper_add(struct intel_plane *plane) { - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); + if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs); + else + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } =20 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_pla= ne_state, --=20 2.49.0 From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72577288C09 for ; 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Fri, 06 Jun 2025 08:06:40 -0400 X-MC-Unique: tYOC6bZiOBi7uTbL3bbC5A-1 X-Mimecast-MFC-AGG-ID: tYOC6bZiOBi7uTbL3bbC5A_1749211598 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id CF518180036E; Fri, 6 Jun 2025 12:06:37 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5F49D18002A5; Fri, 6 Jun 2025 12:06:32 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 7/9] drm/i915/display: Add drm_panic support for Y-tiling with DPT Date: Fri, 6 Jun 2025 13:48:11 +0200 Message-ID: <20250606120519.753928-8-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements Y-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- v8: * Pass the tiling function to intel_bo_panic_setup() .../gpu/drm/i915/display/intel_atomic_plane.c | 66 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_bo.c | 5 +- drivers/gpu/drm/i915/display/intel_bo.h | 3 +- .../drm/i915/display/skl_universal_plane.c | 15 +++-- drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 +++++- drivers/gpu/drm/xe/display/intel_bo.c | 10 ++- 7 files changed, 108 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 4095d69924db..ce5471bd3c43 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1271,6 +1271,31 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_plane_unpin_fb(old_plane_state); } =20 +/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is = easier) + * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32= x32 + * pixels for 32bits pixels. + */ +#define YTILE_WIDTH 32 +#define YTILE_HEIGHT 32 +#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4) + +static unsigned int intel_ytile_get_offset(unsigned int width, unsigned in= t x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); + offset +=3D swizzle * 4; + return offset; +} =20 static void intel_panic_flush(struct drm_plane *plane) { @@ -1297,6 +1322,35 @@ static void intel_panic_flush(struct drm_plane *plan= e) iplane->disable_tiling(iplane); } =20 +static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int= width, + unsigned int x, + unsigned int y) +{ + switch (fb_modifier) { + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return intel_ytile_get_offset; + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Yf_TILED_CCS: + default: + /* Not supported yet */ + return NULL; + } +} + static int intel_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) { @@ -1304,6 +1358,7 @@ static int intel_get_scanout_buffer(struct drm_plane = *plane, struct drm_gem_object *obj; struct drm_framebuffer *fb; struct intel_display *display =3D to_intel_display(plane->dev); + unsigned int (*tiling)(unsigned int width, unsigned int x, unsigned int y= ) =3D NULL; =20 if (!plane->state || !plane->state->fb || !plane->state->visible) return -ENODEV; @@ -1319,9 +1374,14 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, } else { int ret; /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) - return -EOPNOTSUPP; - ret =3D intel_bo_panic_setup(obj, sb); + if (intel_fb_uses_dpt(fb)) { + if (fb->format->cpp[0] !=3D 4) + return -EOPNOTSUPP; + tiling =3D intel_get_tiling_func(fb->modifier); + if (!tiling) + return -EOPNOTSUPP; + } + ret =3D intel_bo_panic_setup(obj, sb, tiling); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915= /display/intel_bo.c index 83dbd8ae16fe..16c4ef30133c 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -59,9 +59,10 @@ void intel_bo_describe(struct seq_file *m, struct drm_ge= m_object *obj) i915_debugfs_describe_obj(m, to_intel_bo(obj)); } =20 -int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb) +int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb, + unsigned int (*tiling)(unsigned int, unsigned int, unsigned int)) { - return i915_gem_object_panic_setup(to_intel_bo(obj), sb); + return i915_gem_object_panic_setup(to_intel_bo(obj), sb, tiling); } =20 void intel_bo_panic_finish(struct drm_gem_object *obj) diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915= /display/intel_bo.h index 9ac087ea275d..9eecc18005ae 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -24,7 +24,8 @@ struct intel_frontbuffer *intel_bo_set_frontbuffer(struct= drm_gem_object *obj, struct intel_frontbuffer *front); =20 void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj); -int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb); +int intel_bo_panic_setup(struct drm_gem_object *obj, struct drm_scanout_bu= ffer *sb, + unsigned int (*tiling)(unsigned int, unsigned int, unsigned int)); void intel_bo_panic_finish(struct drm_gem_object *obj); =20 #endif /* __INTEL_BO__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index ffcf50443c0c..e73f171988f3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2795,15 +2795,22 @@ static void skl_disable_tiling(struct intel_plane *= plane) { struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); struct intel_display *display =3D to_intel_display(plane); - u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + const struct drm_framebuffer *fb =3D state->hw.fb; u32 plane_ctl; =20 plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); - plane_ctl &=3D ~PLANE_CTL_TILED_MASK; =20 - intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), - PLANE_STRIDE_(stride)); + if (intel_fb_uses_dpt(fb)) { + /* if DPT is enabled, keep tiling, but disable compression */ + plane_ctl &=3D ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; + } else { + /* if DPT is not supported, disable tiling, and update stride */ + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; =20 + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + } intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); =20 intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i= 915/gem/i915_gem_object.h index 9a0c1019dcad..a9d4e7f93c1f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -692,7 +692,8 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object = *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_truncate(struct drm_i915_gem_object *obj); =20 -int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb); +int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb, + unsigned int (*tiling)(unsigned int, unsigned int, unsigned int)); void i915_gem_object_panic_finish(struct drm_i915_gem_object *obj); =20 /** diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i9= 15/gem/i915_gem_pages.c index 9bdbac3d9433..6a1cc0213ad0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -358,6 +358,7 @@ static void *i915_gem_object_map_pfn(struct drm_i915_ge= m_object *obj, static struct page **i915_panic_pages; static int i915_panic_page =3D -1; static void *i915_panic_vaddr; +static unsigned int (*i915_panic_tiling)(unsigned int, unsigned int, unsig= ned int); =20 static void i915_panic_kunmap(void) { @@ -385,6 +386,14 @@ static struct page **i915_gem_object_panic_pages(struc= t drm_i915_gem_object *obj return pages; } =20 +static void i915_gem_object_panic_map_set_pixel(struct drm_scanout_buffer = *sb, unsigned int x, + unsigned int y, u32 color) +{ + unsigned int offset =3D i915_panic_tiling(sb->width, x, y); + + iosys_map_wr(&sb->map[0], offset, u32, color); +} + /* * The scanout buffer pages are not mapped, so for each pixel, * use kmap_local_page_try_from_panic() to map the page, and write the pix= el. @@ -396,7 +405,10 @@ static void i915_gem_object_panic_page_set_pixel(struc= t drm_scanout_buffer *sb, unsigned int new_page; unsigned int offset; =20 - offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; + if (i915_panic_tiling) + offset =3D i915_panic_tiling(sb->width, x, y); + else + offset =3D y * sb->pitch[0] + x * sb->format->cpp[0]; =20 new_page =3D offset >> PAGE_SHIFT; offset =3D offset % PAGE_SIZE; @@ -417,11 +429,14 @@ static void i915_gem_object_panic_page_set_pixel(stru= ct drm_scanout_buffer *sb, * Use current vaddr if it exists, or setup a list of pages. * pfn is not supported yet. */ -int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb) +int i915_gem_object_panic_setup(struct drm_i915_gem_object *obj, struct dr= m_scanout_buffer *sb, + unsigned int (*tiling)(unsigned int, unsigned int, unsigned int)) { enum i915_map_type has_type; void *ptr; =20 + i915_panic_tiling =3D tiling; + ptr =3D page_unpack_bits(obj->mm.mapping, &has_type); if (ptr) { if (i915_gem_object_has_iomem(obj)) @@ -429,6 +444,8 @@ int i915_gem_object_panic_setup(struct drm_i915_gem_obj= ect *obj, struct drm_scan else iosys_map_set_vaddr(&sb->map[0], ptr); =20 + if (tiling) + sb->set_pixel =3D i915_gem_object_panic_map_set_pixel; return 0; } if (i915_gem_object_has_struct_page(obj)) { diff --git a/drivers/gpu/drm/xe/display/intel_bo.c b/drivers/gpu/drm/xe/dis= play/intel_bo.c index eb9a3400c110..af990a8cd674 100644 --- a/drivers/gpu/drm/xe/display/intel_bo.c +++ b/drivers/gpu/drm/xe/display/intel_bo.c @@ -64,6 +64,7 @@ void intel_bo_describe(struct seq_file *m, struct drm_gem= _object *obj) static int xe_panic_page =3D -1; static void *xe_panic_vaddr; static struct xe_bo *xe_panic_bo; +static unsigned int (*xe_panic_tiling)(unsigned int, unsigned int, unsigne= d int); =20 static void xe_panic_kunmap(void) { @@ -84,7 +85,10 @@ static void xe_panic_page_set_pixel(struct drm_scanout_b= uffer *sb, unsigned int unsigned int new_page; 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charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements 4-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index ce5471bd3c43..8c422c6a7186 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1297,6 +1297,25 @@ static unsigned int intel_ytile_get_offset(unsigned = int width, unsigned int x, u return offset; } =20 +static unsigned int intel_4tile_get_offset(unsigned int width, unsigned in= t x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | + ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset +=3D swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1342,6 +1361,7 @@ static unsigned int (*intel_get_tiling_func(u64 fb_mo= difier))(unsigned int width case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_get_offset; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: --=20 2.49.0 From nobody Fri Dec 19 20:34:09 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5A672874E7 for ; Fri, 6 Jun 2025 12:07:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; 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charset="utf-8" When the panic handler is called, configure the psr to send the full framebuffer to the monitor, otherwise the panic screen is only partially visible. Signed-off-by: Jocelyn Falempe --- v8: * Added in v8 .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_psr.c | 20 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 8c422c6a7186..c9a9f0770205 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -58,6 +58,7 @@ #include "intel_fb.h" #include "intel_fb_pin.h" #include "intel_fbdev.h" +#include "intel_psr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -1319,6 +1320,7 @@ static unsigned int intel_4tile_get_offset(unsigned i= nt width, unsigned int x, u static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); + struct intel_crtc_state *crtc_state =3D to_intel_crtc_state(plane->state-= >crtc->state); struct intel_plane *iplane =3D to_intel_plane(plane); struct intel_display *display =3D to_intel_display(iplane); struct drm_framebuffer *fb =3D plane_state->hw.fb; @@ -1328,6 +1330,11 @@ static void intel_panic_flush(struct drm_plane *plan= e) =20 intel_bo_panic_finish(obj); =20 + if (crtc_state->enable_psr2_sel_fetch) { + /* Force a full update for psr2 */ + intel_psr2_panic_force_full_update(display, crtc_state); + } + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer= .*/ if (to_intel_framebuffer(fb) =3D=3D intel_fbdev_framebuffer(display->fbde= v.fbdev)) { struct iosys_map map; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i91= 5/display/intel_psr.c index db7111374293..283ac2618ea5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2888,6 +2888,26 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_= state *state, return 0; } =20 +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder =3D crtc_state->cpu_transcoder; + u32 val =3D man_trk_ctl_enable_bit_get(display); + + /* SF partial frame enable has to be set even on full update */ + val |=3D man_trk_ctl_partial_frame_bit_get(display); + val |=3D man_trk_ctl_continuos_full_frame(display); + + /* Directly write the register */ + intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val= ); + + if (!crtc_state->enable_psr2_su_region_et) + return; + + intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); +} + void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i91= 5/display/intel_psr.h index 0cf53184f13f..9b061a22361f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -57,6 +57,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state= *state, struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *cr= tc_state); --=20 2.49.0