From nobody Wed Dec 17 15:33:09 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34F491C861D; Fri, 6 Jun 2025 09:39:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749202789; cv=none; b=PV4GaTKWGMgstwESmCGr0/vIC+uiSZ+6kfCrh2yhkz/784ii8fj7C5K3+wH7N/86H3hNAjomIOKL26qvR/21roA6OMrQqBYOCC2pPRaihbYhgGJKv+UvDvoUboWnbXvD6s/CV/Tg4wgY/FYVe0MFmXPYOv8+9fIp2eTH3w+3Auk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749202789; c=relaxed/simple; bh=2OFIkwcFfGxbIptsJzGXFt9IKn/aP/aohtIajXB2Jno=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wt9BoWgY4PvBFBxkhS3kesmbB99+pDpcTKkqbc4JsvESWbJFi99yZhIjTuO55Hw8gHA26kSPuQO7pugKPFp8i89fQexUwvQdYTXjFlgbInPYINQoz1UMWYxGENLIS9bR9c9byEs6HLhmDKHcDq2kdXk3kltq3tbc5Pc3rXNNAVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Lf2shYci; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Lf2shYci" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1749202787; x=1780738787; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2OFIkwcFfGxbIptsJzGXFt9IKn/aP/aohtIajXB2Jno=; b=Lf2shYciSVxArhhKE7mtyIaFOO6vDkFpU1f+HejPiVz1KasX/xaU6OiR p3XZ8Yxu/drKzfyq/wkkl7k8tsc2sYALWNuP+zFGiZc4JyLL30qfB6kOe DAs/G/3UPPYypS7uxvwO4PPAcv5lYNR71rJezqcijFwPPzm6uSXzaXMu4 TEapBqFvB/Er2CaJUV1AWtYjMExW5ImHyz8nmgmeT+G71DjWOSnM/abR7 HnQBWhQIDaKBrwqWrxsJHk0wyITQXYrv7bB++5kyfDX40Ut7508NmO5DX zZWoqzcsoZlD/Wx0lV/CIR27sqx/n/+CXeYayeTmOBw7GTwxHnyjDopBM Q==; X-CSE-ConnectionGUID: RNxw4F1gS4uefnTd7vXzbA== X-CSE-MsgGUID: y5Nj09tiRyOGdHR44TJ84A== X-IronPort-AV: E=Sophos;i="6.16,214,1744095600"; d="scan'208";a="43064047" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Jun 2025 02:39:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Fri, 6 Jun 2025 02:39:43 -0700 Received: from marius-VM.mshome.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Fri, 6 Jun 2025 02:39:40 -0700 From: To: , , , CC: , , , , , , , Subject: [PATCH v3 1/2] dt-bindings: iio: adc: adding support for PAC194X Date: Fri, 6 Jun 2025 12:39:28 +0300 Message-ID: <20250606093929.100118-2-marius.cristea@microchip.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606093929.100118-1-marius.cristea@microchip.com> References: <20250606093929.100118-1-marius.cristea@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Marius Cristea This is the device tree schema for iio driver for Microchip PAC194X and PAC195X series of Power Monitors with Accumulator. The PAC194X family supports 9V Full-Scale Range and the PAC195X supports 32V Full-Scale Range. There are two versions of the PAC194X/5X: the PAC194X/5X-1 devices are for high-side current sensing and the PAC194X/5X-2 devices are for low-side current sensing or floating VBUS applications. The PAC194X/5X-1 is named shortly PAC194X/5X. Signed-off-by: Marius Cristea --- .../bindings/iio/adc/microchip,pac1944.yaml | 204 ++++++++++++++++++ 1 file changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/microchip,pac= 1944.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,pac1944.ya= ml b/Documentation/devicetree/bindings/iio/adc/microchip,pac1944.yaml new file mode 100644 index 000000000000..4a2cf6b64055 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/microchip,pac1944.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/microchip,pac1944.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PAC1944 and PAC1954 Power Monitors with Accumulator + +maintainers: + - Marius Cristea + +description: | + This device is part of the Microchip family of Power Monitors with + Accumulator. The datasheet for PAC1941-1, PAC1941-1, PAC1942-1, PAC1942-= 2, + PAC1943-1 and PAC1944-1 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produc= tDocuments/DataSheets/PAC194X-Family-Data-Sheet-DS20006543.pdf + The datasheet for PAC1951-1, PAC1951-1, PAC1952-1, PAC1952-2, PAC1953-1 = and + PAC1954-1 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Produc= tDocuments/DataSheets/PAC195X-Family-Data-Sheet-DS20006539.pdf + +properties: + compatible: + enum: + - microchip,pac1941 + - microchip,pac19412 + - microchip,pac1942 + - microchip,pac19422 + - microchip,pac1943 + - microchip,pac1944 + - microchip,pac1951 + - microchip,pac19512 + - microchip,pac1952 + - microchip,pac19522 + - microchip,pac1953 + - microchip,pac1954 + + reg: + maxItems: 1 + + vdd-supply: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + interrupts: + maxItems: 2 + + interrupt-names: + description: + alert1 indicates a HIGH or LOW limit was exceeded. + alert2 indicates a THERM limit was exceeded. + items: + - const: alert1 + - const: alert2 + +patternProperties: + "^channel@[1-4]+$": + type: object + $ref: adc.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + reg: + items: + minimum: 1 + maximum: 4 + + shunt-resistor-micro-ohms: + description: + Value in micro Ohms of the shunt resistor connected between + the SENSE+ and SENSE- inputs, across which the current is measur= ed. + Value is needed to compute the scaling of the measured current. + + microchip,vbus-half-range: + $ref: /schemas/types.yaml#/definitions/flag + description: | + In order to increase measurement resolution and keeping the same + number the of bits the device has a configurable VBUS full range= scale + (FSR). The range should be set by hardware design and it should = not be + changed during runtime. The bipolar capability for VBUS enables + accurate offset measurement and correction. + The VBUS could be configured into the following full scale range: + - VBUS has unipolar 0V to 32V FSR (default) for PAC195X or 0V = to 9V + (default) for PAC194X. + - VBUS has bipolar -32V to 32V FSR for PAC195X or -9V to 9V for + PAC194X. The actual range is limited to about -200 mV due to= the + impact of the ESD structures. + - VBUS has bipolar -16V to 16V FSR for PAC195X or -4.5V to 4.5= V for + PAC194X. The actual range is limited to about -200 mV due to= the + impact of the ESD structures. + + microchip,vbus-bipolar: + $ref: /schemas/types.yaml#/definitions/flag + description: + If provided, the channel is to be used in bipolar mode. The + actual range is limited to about -200 mV due to the impact of th= e ESD + structures. + + microchip,vsense-half-range: + $ref: /schemas/types.yaml#/definitions/flag + description: | + In order to decrease the power dissipation on the shunt resistor= and + in the same time to increase measurement resolution by keeping t= he + same number the of bits the device has a configurable VSENSE full + range scale (FSR). The range should be set by hardware design an= d it + should not be changed during runtime. + The VSENSE could be configured into the following full scale ran= ge: + - VSENSE has unipolar 0V to 100 mV FSR (default) + - VSENSE has bipolar -100 mV to 100 mV FSR + - VSENSE has bipolar -50 mV to 50 mV FSR + + microchip,vsense-bipolar: + $ref: /schemas/types.yaml#/definitions/flag + description: + If provided, the channel is to be used in bipolar mode. + + microchip,accumulation-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The Hardware Accumulator may be used to accumulate VPOWER, VSENS= E or + VBUS values for any channel. By setting the accumulator for a ch= annel + to accumulate the VPOWER values gives a measure of accumulated p= ower + into a time period, which is equivalent to energy. Setting the + accumulator for a channel to accumulate VSENSE values gives a me= asure + of accumulated current, which is equivalent to charge. This allo= ws the + accumulator to be used as a coulomb counter. For either VSENSE or + VBUS, many samples may be accumulated on chip and the result col= lected + by the host and divided by the accumulator counter count value to + yield an average value with a very long integration time to redu= ce + noise. This feature is also very useful for system calibration, + allowing many averages to be accumulated for fast averaging/noise + reduction. + This functionality needs to be setup once and must not be changed + during the runtime, just in case the user wants to measure the c= harge + or the energy consumed from board power up till the user has con= trol + or during a reboot of the system. + The Hardware Accumulator could be configured to accumulate + VPOWER, VSENSE or VBUS + <0> - Accumulator accumulates VPOWER (default) + <1> - Accumulator accumulates VSENSE + <2> - Accumulator accumulates VBUS + maximum: 2 + default: 0 + + required: + - reg + - shunt-resistor-micro-ohms + + unevaluatedProperties: false + +required: + - compatible + - reg + - vdd-supply + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-monitor@10 { + compatible =3D "microchip,pac1954"; + reg =3D <0x10>; + vdd-supply =3D <&vdd>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@1 { + reg =3D <0x1>; + shunt-resistor-micro-ohms =3D <24900>; + label =3D "CPU"; + microchip,vsense-half-range; + microchip,vsense-bipolar; + }; + + channel@3 { + reg =3D <0x3>; + shunt-resistor-micro-ohms =3D <75000>; + label =3D "MEM"; + microchip,vbus-half-range; + microchip,vbus-bipolar; + microchip,vsense-half-range; + }; + + channel@4 { + reg =3D <0x4>; + shunt-resistor-micro-ohms =3D <100000>; + label =3D "NET"; + microchip,vbus-bipolar; + }; + }; + }; + +... --=20 2.48.1 From nobody Wed Dec 17 15:33:09 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E169286424; Fri, 6 Jun 2025 09:40:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749202835; cv=none; b=tyv4qQDk7eQvkMmtE3qzVgsrQv1XySdz/aAPwaawfXL+y6xkWC9daXjEPlYyxKHyjuIcBZZtwqUH4xyaJa/GthHAKoseqUwyWgz446ZB7/9ueZUDp0rGqOFvqBPrTYDJi963fGdFjiHCQjjdS2oOX4IDD6bWuOOHV8Au9wtNUTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749202835; c=relaxed/simple; bh=UvEzkzzdRSdLU09QVWj2cGb9t4oSZLXYFVa39D5Yx8k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cmuO5JF9CWFMIDdlsLtb504w5NiTjvMf58Mn6B91IOycy3811d0dgkcjJESJEZYxDnQyKuxakIM1YD/h5N1RvWqTbVDQM0fveV6d2WQx8GyXs5sfDn0ixD8fGe0ZUE241agw6w9cZ3FYKnCIlOcFYtys8cItxOoWX9dDordirHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=jZu8bqer; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jZu8bqer" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1749202831; x=1780738831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UvEzkzzdRSdLU09QVWj2cGb9t4oSZLXYFVa39D5Yx8k=; b=jZu8bqerHBnge5ykhKgAFRtVNoWBuM4G39JCaKGR5fUbxCotPElphMEK WkYdGY1KE7Y/C5mtPPMTra1Wu/CpUynDd4tEI4gu7Lu5rYJ5INNsw+Ki3 V/zbsWMnlLZVeoJ77TsHFVpL53l0DwFfzs2lz3USscd8gmkcQuA4oKbNJ au5/uIpS6WRFD8gx6sIztA/NMHmgnfSmE78rhDIrf7To6w98EObgiICut nZttcsD47WL2Mm4x2vW+MJAyrtZfGmPM0tAdUPQ8QDRZL8Y3NmpjBzkr9 KFneHLp1Gcax1ayKm35GyFNHIRtQsDSofNo3wbtL6bPaWmmNDQ0NH95zB Q==; X-CSE-ConnectionGUID: sMPIwhvsR82v7ZZg5p3Gug== X-CSE-MsgGUID: RuXcIohoQTO3uryuSvFXtg== X-IronPort-AV: E=Sophos;i="6.16,214,1744095600"; d="scan'208";a="47448216" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Jun 2025 02:40:29 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Fri, 6 Jun 2025 02:39:49 -0700 Received: from marius-VM.mshome.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Fri, 6 Jun 2025 02:39:46 -0700 From: To: , , , CC: , , , , , , , Subject: [PATCH v3 2/2] iio: adc: adding support for PAC194X Date: Fri, 6 Jun 2025 12:39:29 +0300 Message-ID: <20250606093929.100118-3-marius.cristea@microchip.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250606093929.100118-1-marius.cristea@microchip.com> References: <20250606093929.100118-1-marius.cristea@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Marius Cristea This is the iio driver for Microchip PAC194X and PAC195X series of Power Monitors with Accumulator. The PAC194X family supports 9V Full-Scale Range and the PAC195X supports 32V Full-Scale Range. There are two versions of the PAC194X/5X: the PAC194X/5X-1 devices are for high-side current sensing and the PAC194X/5X-2 devices are for low-side current sensing or floating VBUS applications. The PAC194X/5X-1 is named shortly PAC194X/5X. Signed-off-by: Marius Cristea --- .../ABI/testing/sysfs-bus-iio-adc-pac1944 | 17 + MAINTAINERS | 7 + drivers/iio/adc/Kconfig | 12 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/pac1944.c | 2841 +++++++++++++++++ 5 files changed, 2878 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-pac1944 create mode 100644 drivers/iio/adc/pac1944.c diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-pac1944 b/Document= ation/ABI/testing/sysfs-bus-iio-adc-pac1944 new file mode 100644 index 000000000000..ae88eac354a4 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-adc-pac1944 @@ -0,0 +1,17 @@ +What: /sys/bus/iio/devices/iio:deviceX/slow_alert1_cfg +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + A read/write property used to route, inside the PAC device, a specific A= LERT + signal to the SLOW/ALERT1 pin. The SLOW/ALERT1 pin must be configured fo= r the + ALERT function in order to control the device hardware pin (this is the = default + functionality of the device hardware pin). + +What: /sys/bus/iio/devices/iio:deviceX/gpio_alert2_cfg +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + A read/write property used to route, inside the PAC device, a specific A= LERT + signal to the GPIO/ALERT2 hardware pin. The GPIO/ALERT2 pin must be conf= igured + for ALERT function in order to control the device hardware pin (this is = the + default functionality of the device hardware pin). diff --git a/MAINTAINERS b/MAINTAINERS index 86a2045ba62e..240e84893ad9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15920,6 +15920,13 @@ S: Supported F: Documentation/devicetree/bindings/iio/adc/microchip,pac1934.yaml F: drivers/iio/adc/pac1934.c =20 +MICROCHIP PAC1944 ADC DRIVER +M: Marius Cristea +L: linux-iio@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/microchip,pac1944.yaml +F: drivers/iio/adc/pac1944.c + MICROCHIP PCI1XXXX GP DRIVER M: Vaibhaav Ram T.L M: Kumaravel Thiagarajan diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 186a453af56c..a608aa6cb9c7 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1148,6 +1148,18 @@ config PAC1934 This driver can also be built as a module. If so, the module will be called pac1934. =20 +config PAC1944 + tristate "Microchip Technology PAC1944/PAC1954 driver" + depends on I2C + help + Say yes here to build support for Microchip Technology's PAC1941, + PAC1941-2, PAC1942, PAC1942-2, PAC1943, PAC1944, PAC1951, + PAC1951-2, PAC1952, PAC1952-2, PAC1953, PAC1954 + Single/Multi-Channel Power Monitor with Accumulator. + + This driver can also be built as a module. If so, the module + will be called pac1944. + config PALMAS_GPADC tristate "TI Palmas General Purpose ADC" depends on MFD_PALMAS diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 09ae6edb2650..ee47d880babf 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_NCT7201) +=3D nct7201.o obj-$(CONFIG_NPCM_ADC) +=3D npcm_adc.o obj-$(CONFIG_PAC1921) +=3D pac1921.o obj-$(CONFIG_PAC1934) +=3D pac1934.o +obj-$(CONFIG_PAC1944) +=3D pac1944.o obj-$(CONFIG_PALMAS_GPADC) +=3D palmas_gpadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) +=3D qcom-pm8xxx-xoadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) +=3D qcom-spmi-adc5.o diff --git a/drivers/iio/adc/pac1944.c b/drivers/iio/adc/pac1944.c new file mode 100644 index 000000000000..ce09334b076a --- /dev/null +++ b/drivers/iio/adc/pac1944.c @@ -0,0 +1,2841 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IIO driver for PAC194X and PAC195X series chips + * + * Copyright (C) 2022-2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Marius Cristea marius.cristea@microchip.com + * + * Datasheet for PAC1941, PAC1942, PAC1943 and PAC1944 can be found here: + * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Product= Documents/DataSheets/PAC194X-Family-Data-Sheet-DS20006543.pdf + * Datasheet for PAC1951, PAC1952, PAC1953 and PAC1954 can be found here: + * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Product= Documents/DataSheets/PAC195X-Family-Data-Sheet-DS20006539.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Maximum (1092 * 60 * 1000), around 1092 minutes@1024 sps + * We will keep the refresh lower + */ +#define PAC1944_MAX_RFSH_LIMIT_MS 300000 + +/* 50msec is the timeout for validity of the cached registers */ +#define PAC1944_MIN_POLLING_TIME_MS 50 +/* + * 1000usec is the minimum wait time for normal conversions when sample + * rate doesn't change + */ +#define PAC1944_MIN_UPDATE_WAIT_TIME_US 1000 + +#define PAC1944_SHUNT_UOHMS_DEFAULT 100000 + +/* 32000mV */ +#define PAC195X_VOLTAGE_MILLIVOLTS_MAX 32000 +/* 9000mV */ +#define PAC194X_VOLTAGE_MILLIVOLTS_MAX 9000 + +/* + * Voltage bits resolution when set for unsigned values and + * HALF FSR signed values + */ +#define PAC1944_VOLTAGE_16B_RES 16 +/* Voltage bits resolution when set for signed values */ +#define PAC1944_VOLTAGE_15B_RES 15 + +/* 100mV maximum voltage drop over the sense resistors */ +#define PAC1944_VSENSE_MILLIVOLTS_MAX 100 + +/* + * Current bits resolution when set for unsigned values and + * HALF FSR signed values + */ +#define PAC1944_CURRENT_16B_RES 16 + +/* Current bits resolution when set for signed values */ +#define PAC1944_CURRENT_15B_RES 15 + +/* Power resolution is 30 bits when unsigned and HALF FSR signed values */ +#define PAC1944_POWER_30B_RES 30 + +/* Power resolution is 29 bits when signed */ +#define PAC1944_POWER_29B_RES 29 + +/* Accumulation register is 56 bits long for unipolar range */ +#define PAC1944_ENERGY_56B_RES 56 + +/* Accumulation register is 56 bits long for bipolar range */ +#define PAC1944_ENERGY_55B_RES 55 + +/* Maximum power-product value - 32 V * 0.1 V */ +#define PAC195X_PRODUCT_VOLTAGE_PV_FSR 3200000000000UL + +/* Maximum power-product value - 9 V * 0.1 V */ +#define PAC194X_PRODUCT_VOLTAGE_PV_FSR 900000000000UL + +#define PAC1944_MEAS_REG_SNAPSHOT_LEN 80 +#define PAC1944_CTRL_REG_SNAPSHOT_LEN 24 + +#define PAC1944_DEFAULT_CHIP_SAMP_SPEED_HZ 1024 + +/* Device register address map */ +#define PAC1944_REFRESH_REG_ADDR 0x00 +#define PAC1944_CTRL_REG_ADDR 0x01 +#define PAC1944_ACC_COUNT_REG_ADDR 0x02 +#define PAC1944_VACC_1_REG_ADDR 0x03 +#define PAC1944_VACC_2_REG_ADDR 0x04 +#define PAC1944_VACC_3_REG_ADDR 0x05 +#define PAC1944_VACC_4_REG_ADDR 0x06 +#define PAC1944_VBUS_1_ADDR 0x07 +#define PAC1944_VBUS_2_ADDR 0x08 +#define PAC1944_VBUS_3_ADDR 0x09 +#define PAC1944_VBUS_4_ADDR 0x0A +#define PAC1944_VSENSE_1_ADDR 0x0B +#define PAC1944_VSENSE_2_ADDR 0x0C +#define PAC1944_VSENSE_3_ADDR 0x0D +#define PAC1944_VSENSE_4_ADDR 0x0E +#define PAC1944_VBUS_AVG_1_ADDR 0x0F +#define PAC1944_VBUS_AVG_2_ADDR 0x10 +#define PAC1944_VBUS_AVG_3_ADDR 0x11 +#define PAC1944_VBUS_AVG_4_ADDR 0x12 +#define PAC1944_VSENSE_AVG_1_ADDR 0x13 +#define PAC1944_VSENSE_AVG_2_ADDR 0x14 +#define PAC1944_VSENSE_AVG_3_ADDR 0x15 +#define PAC1944_VSENSE_AVG_4_ADDR 0x16 +#define PAC1944_VPOWER_1_ADDR 0x17 +#define PAC1944_VPOWER_2_ADDR 0x18 +#define PAC1944_VPOWER_3_ADDR 0x19 +#define PAC1944_VPOWER_4_ADDR 0x1A + +/* Start of configurations registers */ +#define PAC1944_SMBUS_SETTINGS_REGS_ADDR 0x1C +#define PAC1944_NEG_PWR_FSR_REG_ADDR 0x1D +#define PAC1944_REFRESG_V_REG_ADDR 0x1E +#define PAC1944_REFRESH_V_REG_ADDR 0x1F +#define PAC1944_SLOW_REG_ADDR 0x20 +#define PAC1944_CTRL_ACT_REG_ADDR 0x21 +#define PAC1944_CTRL_LAT_REG_ADDR 0x23 +#define PAC1944_NEG_PWR_FSR_LAT_REG_ADDR 0x24 +#define PAC1944_ACCUM_CFG_REG_ADDR 0x25 + +/* + * Registers related to alert functionality + */ +#define PAC1944_ALERT_STATUS_REG_ADDR 0x26 +#define PAC1944_SLOW_ALERT1_REG_ADDR 0x27 +#define PAC1944_GPIO_ALERT2_REG_ADDR 0x28 +#define PAC1944_ACC_FULLNESS_LIMITS_REG_ADDR 0x29 +#define PAC1944_OC_LIMIT_REG_ADDR 0x30 +#define PAC1944_UC_LIMIT_REG_ADDR 0x34 +#define PAC1944_OP_LIMIT_REG_ADDR 0x38 +#define PAC1944_OV_LIMIT_REG_ADDR 0x3C +#define PAC1944_UV_LIMIT_REG_ADDR 0x40 +#define PAC1944_OC_LIMIT_NSAMPLES_REG_ADDR 0x44 +#define PAC1944_UC_LIMIT_NSAMPLES_REG_ADDR 0x45 +#define PAC1944_OP_LIMIT_NSAMPLES_REG_ADDR 0x46 +#define PAC1944_OV_LIMIT_NSAMPLES_REG_ADDR 0x47 +#define PAC1944_UV_LIMIT_NSAMPLES_REG_ADDR 0x48 +#define PAC1944_ALERT_ENABLE_REG_ADDR 0x49 + +#define PAC1944_ALERT_ENABLE_REG_LEN 3 +#define PAC1944_ALERTS_REG_LEN 63 + +#define PAC1944_PID_REG_ADDR 0xFD + +/* Alert Enable register */ +#define PAC1944_OC_MASK GENMASK(23, 20) +#define PAC1944_CH01OC_MASK BIT(23) +#define PAC1944_CH01OC_SET BIT(23) +#define PAC1944_CH02OC_MASK BIT(22) +#define PAC1944_CH02OC_SET BIT(22) +#define PAC1944_CH03OC_MASK BIT(21) +#define PAC1944_CH03OC_SET BIT(21) +#define PAC1944_CH04OC_MASK BIT(20) +#define PAC1944_CH04OC_SET BIT(20) + +#define PAC1944_UC_MASK GENMASK(19, 16) +#define PAC1944_CH01UC_MASK BIT(19) +#define PAC1944_CH01UC_SET BIT(19) +#define PAC1944_CH02UC_MASK BIT(18) +#define PAC1944_CH02UC_SET BIT(18) +#define PAC1944_CH03UC_MASK BIT(17) +#define PAC1944_CH03UC_SET BIT(17) +#define PAC1944_CH04UC_MASK BIT(16) +#define PAC1944_CH04UC_SET BIT(16) + +#define PAC1944_OV_MASK GENMASK(15, 12) +#define PAC1944_CH01OV_MASK BIT(15) +#define PAC1944_CH01OV_SET BIT(15) +#define PAC1944_CH02OV_MASK BIT(14) +#define PAC1944_CH02OV_SET BIT(14) +#define PAC1944_CH03OV_MASK BIT(13) +#define PAC1944_CH03OV_SET BIT(13) +#define PAC1944_CH04OV_MASK BIT(12) +#define PAC1944_CH04OV_SET BIT(12) + +#define PAC1944_UV_MASK GENMASK(11, 8) +#define PAC1944_CH01UV_MASK BIT(11) +#define PAC1944_CH01UV_SET BIT(11) +#define PAC1944_CH02UV_MASK BIT(10) +#define PAC1944_CH02UV_SET BIT(10) +#define PAC1944_CH03UV_MASK BIT(9) +#define PAC1944_CH03UV_SET BIT(9) +#define PAC1944_CH04UV_MASK BIT(8) +#define PAC1944_CH04UV_SET BIT(8) + +#define PAC1944_OP_MASK GENMASK(7, 4) +#define PAC1944_CH01OP_MASK BIT(7) +#define PAC1944_CH01OP_SET BIT(7) +#define PAC1944_CH02OP_MASK BIT(6) +#define PAC1944_CH02OP_SET BIT(6) +#define PAC1944_CH03OP_MASK BIT(5) +#define PAC1944_CH03OP_SET BIT(5) +#define PAC1944_CH04OP_MASK BIT(4) +#define PAC1944_CH04OP_SET BIT(4) + +#define PAC1944_ACC_OVF_MASK BIT(3) +#define PAC1944_ACC_OVF_SET BIT(3) + +#define PAC1944_ACC_COUNT_MASK BIT(2) +#define PAC1944_ACC_COUNT_SET BIT(2) + +#define PAC1944_ALERT_CC1_MASK BIT(1) +#define PAC1944_ALERT_CC1_SET BIT(1) + +#define PAC1944_ACC_REG_LEN 4 +#define PAC1944_VACC_REG_LEN 7 +#define PAC1944_VBUS_SENSE_REG_LEN 2 +#define PAC1944_VPOWER_REG_LEN 4 +#define PAC1944_CTRL_ACT_REG_LEN 2 +#define PAC1944_CTRL_LAT_REG_LEN 2 +#define PAC1944_MAX_REGISTER_LEN 6 + +#define PAC1944_COMMON_DEVATTR 1 +#define PAC1944_ACC_DEVATTR 3 +#define PAC1944_SHARED_DEVATTRS_COUNT 2 + +#define PAC1944_MID 0x5D +#define PAC194x54_PID 0x5B +#define PAC194x53_PID 0x5A +#define PAC194x52_PID 0x59 +#define PAC194x51_PID 0x58 + +#define PAC1944_MAX_CH 4 + +/* PAC194X family */ +#define PAC_PRODUCT_ID_1941 0x68 +#define PAC_PRODUCT_ID_1942 0x69 +#define PAC_PRODUCT_ID_1943 0x6A +#define PAC_PRODUCT_ID_1944 0x6B +#define PAC_PRODUCT_ID_1941_2 0x6C +#define PAC_PRODUCT_ID_1942_2 0x6D +/* PAC195x family */ +#define PAC_PRODUCT_ID_1951 0x78 +#define PAC_PRODUCT_ID_1952 0x79 +#define PAC_PRODUCT_ID_1953 0x7A +#define PAC_PRODUCT_ID_1954 0x7B +#define PAC_PRODUCT_ID_1951_2 0x7C +#define PAC_PRODUCT_ID_1952_2 0x7D + +#define PAC1944_ALERT 0x00 +#define PAC1944_GPIO_INPUT 0x01 +#define PAC1944_GPIO_OUTPUT 0x02 +#define PAC1944_SLOW 0x03 + +#define PAC1944_CTRL_SAMPLE_MASK GENMASK(15, 12) +#define PAC1944_CTRL_GPIO_ALERT2_MASK GENMASK(11, 10) +#define PAC1944_CTRL_SLOW_ALERT1_MASK GENMASK(9, 8) +#define PAC1944_CTRL_CH_1_OFF_MASK BIT(7) +#define PAC1944_CTRL_CH_2_OFF_MASK BIT(6) +#define PAC1944_CTRL_CH_3_OFF_MASK BIT(5) +#define PAC1944_CTRL_CH_4_OFF_MASK BIT(4) + +#define PAC1944_NEG_PWR_CFG_VS1_MASK GENMASK(15, 14) +#define PAC1944_NEG_PWR_CFG_VS2_MASK GENMASK(13, 12) +#define PAC1944_NEG_PWR_CFG_VS3_MASK GENMASK(11, 10) +#define PAC1944_NEG_PWR_CFG_VS4_MASK GENMASK(9, 8) +#define PAC1944_NEG_PWR_CFG_VB1_MASK GENMASK(7, 6) +#define PAC1944_NEG_PWR_CFG_VB2_MASK GENMASK(5, 4) +#define PAC1944_NEG_PWR_CFG_VB3_MASK GENMASK(3, 2) +#define PAC1944_NEG_PWR_CFG_VB4_MASK GENMASK(1, 0) + +#define PAC1944_CFG_ACC4_SHIFT 0 +#define PAC1944_CFG_ACC3_SHIFT 2 +#define PAC1944_CFG_ACC2_SHIFT 4 +#define PAC1944_CFG_ACC1_SHIFT 6 + +#define PAC1944_ACPI_GET_NAMES 1 +#define PAC1944_ACPI_GET_UOHMS_VALS 2 +#define PAC1944_ACPI_GET_BIPOLAR_SETTINGS 4 +#define PAC1944_ACPI_GET_SAMP 5 + +#define ACCUM_REG(acc1_cfg, acc2_cfg, acc3_cfg, acc4_cfg) \ + ((((acc1_cfg) & 0x03) << PAC1944_CFG_ACC1_SHIFT) | \ + (((acc2_cfg) & 0x03) << PAC1944_CFG_ACC2_SHIFT) | \ + (((acc3_cfg) & 0x03) << PAC1944_CFG_ACC3_SHIFT) | \ + (((acc4_cfg) & 0x03) << PAC1944_CFG_ACC4_SHIFT)) + +/* + * Accumulated power/energy formula (in mW-seconds): + * Energy =3D (Vacc/10^9)*[(10^9/2^30)*2^9]*3.2*10^3/Rsense + * Vacc - is the accumulated value per second + * Rsense - value of the shunt resistor in microOhms + * + * PAC195X_MAX_VPOWER_RSHIFTED_BY_29B =3D 3.2*((10^9)/(2^29))*10^9 + * will be used to calculate the scale for accumulated power/energy + */ +#define PAC195X_MAX_VPOWER_RSHIFTED_BY_29B 5960464478UL + +/* + * PAC194X_MAX_VPOWER_RSHIFTED_BY_29B =3D 0.9*((10^9)/(2^29))*10^9 + * will be used to calculate the scale for accumulated power/energy + */ +#define PAC194X_MAX_VPOWER_RSHIFTED_BY_29B 1676380634UL + +/* (100mV * 1000000) / (2^15) used to calculate the scale for current */ +#define PAC1944_MAX_VSENSE_RSHIFTED_BY_15B 3052 + +/* + * [(100mV * 1000000) / (2^15)]*10^9 used to calculate the scale + * for accumulated current/Coulomb counter + */ +#define PAC1944_MAX_VSENSE_NANO 3051757812500UL + +#define to_pac1944_chip_info(d) container_of(d, struct pac1944_chip_info, = work_chip_rfsh) + +/* + * these indexes are exactly describing the element order within a single + * PAC1944/54 phys channel IIO channel descriptor; see the static const st= ruct + * iio_chan_spec pac1944_single_channel[] declaration + */ +enum pac1944_ch_idx { + PAC1944_CH_POWER, + PAC1944_CH_VOLTAGE, + PAC1944_CH_CURRENT, + PAC1944_CH_VOLTAGE_AVERAGE, + PAC1944_CH_CURRENT_AVERAGE, +}; + +/* IDs ordered based on Product ID */ +enum pac1944_ids { + PAC1941, + PAC1942, + PAC1943, + PAC1944, + PAC1941_2, + PAC1942_2, + PAC1951, + PAC1952, + PAC1953, + PAC1954, + PAC1951_2, + PAC1952_2, +}; + +enum pac1944_acc_mode { + PAC1944_ACCMODE_VPOWER, + PAC1944_ACCMODE_VSENSE, + PAC1944_ACCMODE_VBUS, +}; + +enum pac1944_ { + PAC1944_UNIPOLAR_FSR_CFG, + PAC1944_BIPOLAR_FSR_CFG, + PAC1944_BIPOLAR_HALF_FSR_CFG, +}; + +enum pac1944_samps { + PAC1944_SAMP_1024SPS_ADAPT, + PAC1944_SAMP_256SPS_ADAPT, + PAC1944_SAMP_64SPS_ADAPT, + PAC1944_SAMP_8SPS_ADAPT, + + PAC1944_SAMP_1024SPS, + PAC1944_SAMP_256SPS, + PAC1944_SAMP_64SPS, + PAC1944_SAMP_8SPS, + + PAC1944_SAMP_SINGLE_SHOT, + PAC1944_SAMP_SINGLE_SHOT_8X, + PAC1944_SAMP_FAST_MODE, + PAC1944_SAMP_BURST_MODE, + + PAC1944_RESERVED1, + PAC1944_RESERVED2, + PAC1944_RESERVED3, + PAC1944_RESERVED4, +}; + +enum pac1944_number_of_active_channels { + PAC1944_1_CHANNEL_ACTIVE, + PAC1944_2_CHANNELS_ACTIVE, + PAC1944_3_CHANNELS_ACTIVE, + PAC1944_4_CHANNELS_ACTIVE, +}; + +/* + * The PAC195X has a feature called Adaptive Accumulator mode (APAPT). In = this + * mode, sampling is programmed at one of the valid sample rates and sampl= es are + * accumulated. If the SLOW pin is asserted and the device begins sampling= at + * 8 SPS, these samples are shifted by 7 bits to the left and accumulated = so as + * to simulate sampling at the maximum sampling rate, 1024 SPS, and the + * accumulator count is also incremented by 128 for each sample in Slow mo= de + * (when using the Adaptive Accumulator mode) to simulate samples being + * accumulated at the maximum sampling rate. + * This offers a big reduction in host overhead and bus traffic for system= s that + * need to use the SLOW pin for lower power operation during certain times= and + * want to have continuous accurate energy monitoring for both the maximum + * sampling rate and the SLOW sampling rate. + */ +static const unsigned int pac1944_samp_rate_map_tbl[] =3D { + [PAC1944_SAMP_1024SPS_ADAPT] =3D 1024, + [PAC1944_SAMP_256SPS_ADAPT] =3D 256, + [PAC1944_SAMP_64SPS_ADAPT] =3D 64, + [PAC1944_SAMP_8SPS_ADAPT] =3D 8, + [PAC1944_SAMP_1024SPS] =3D 1024, + [PAC1944_SAMP_256SPS] =3D 256, + [PAC1944_SAMP_64SPS] =3D 64, + [PAC1944_SAMP_8SPS] =3D 8, + [PAC1944_SAMP_SINGLE_SHOT] =3D 1, + [PAC1944_SAMP_SINGLE_SHOT_8X] =3D 8, + [PAC1944_SAMP_FAST_MODE] =3D 0xff, + [PAC1944_SAMP_BURST_MODE] =3D 0xff, + [PAC1944_RESERVED1] =3D 0xff, + [PAC1944_RESERVED2] =3D 0xff, + [PAC1944_RESERVED3] =3D 0xff, + [PAC1944_RESERVED4] =3D 0xff, +}; + +static const unsigned int shift_map_tbl[] =3D { + [PAC1944_SAMP_1024SPS_ADAPT] =3D 10, + [PAC1944_SAMP_256SPS_ADAPT] =3D 10, + [PAC1944_SAMP_64SPS_ADAPT] =3D 10, + [PAC1944_SAMP_8SPS_ADAPT] =3D 10, + [PAC1944_SAMP_1024SPS] =3D 10, + [PAC1944_SAMP_256SPS] =3D 8, + [PAC1944_SAMP_64SPS] =3D 6, + [PAC1944_SAMP_8SPS] =3D 3, + [PAC1944_SAMP_SINGLE_SHOT] =3D 10, + [PAC1944_SAMP_SINGLE_SHOT_8X] =3D 8, + [PAC1944_SAMP_FAST_MODE] =3D 0xff, + [PAC1944_SAMP_BURST_MODE] =3D 0xff, + [PAC1944_RESERVED1] =3D 0xff, + [PAC1944_RESERVED2] =3D 0xff, + [PAC1944_RESERVED3] =3D 0xff, + [PAC1944_RESERVED4] =3D 0xff, +}; + +static const unsigned int samp_rate_burst_mode_tbl[] =3D { + [PAC1944_1_CHANNEL_ACTIVE] =3D 5120, + [PAC1944_2_CHANNELS_ACTIVE] =3D 2560, + [PAC1944_3_CHANNELS_ACTIVE] =3D 1706, + [PAC1944_4_CHANNELS_ACTIVE] =3D 1280, +}; + +static const unsigned int samp_rate_fast_mode_tbl[] =3D { + [PAC1944_1_CHANNEL_ACTIVE] =3D 2560, + [PAC1944_2_CHANNELS_ACTIVE] =3D 1707, + [PAC1944_3_CHANNELS_ACTIVE] =3D 1280, + [PAC1944_4_CHANNELS_ACTIVE] =3D 1024, +}; + +/* Available Sample Modes */ +static const char * const pac1944_frequency_avail[] =3D { + "1024_ADAP", + "256_ADAP", + "64_ADAP", + "8_ADAP", + "1024", + "256", + "64", + "8", + "single_shot_1x", + "single_shot_8x", + "fast", + "burst", +}; + +static const unsigned int pac1944_overvoltage_mask_tbl[] =3D { + PAC1944_CH01OV_MASK, + PAC1944_CH02OV_MASK, + PAC1944_CH03OV_MASK, + PAC1944_CH04OV_MASK, +}; + +static const unsigned int pac1944_undervoltage_mask_tbl[] =3D { + PAC1944_CH01UV_MASK, + PAC1944_CH02UV_MASK, + PAC1944_CH03UV_MASK, + PAC1944_CH04UV_MASK, +}; + +static const unsigned int pac1944_overcurrent_mask_tbl[] =3D { + PAC1944_CH01OC_MASK, + PAC1944_CH02OC_MASK, + PAC1944_CH03OC_MASK, + PAC1944_CH04OC_MASK, +}; + +static const unsigned int pac1944_undercurrent_mask_tbl[] =3D { + PAC1944_CH01UC_MASK, + PAC1944_CH02OC_MASK, + PAC1944_CH03OC_MASK, + PAC1944_CH04OC_MASK, +}; + +static const unsigned int pac1944_overpower_mask_tbl[] =3D { + PAC1944_CH01OP_MASK, + PAC1944_CH02OP_MASK, + PAC1944_CH03OP_MASK, + PAC1944_CH04OP_MASK, +}; + +/** + * struct reg_data - data from the registers + * @vsense_mode:array of values, Full Scale Range (FSR) mode for V Sense + * @vbus_mode: array of values, Full Scale Range (FSR) mode for V Bus + * @accumulation_mode: array of values, accumulation mode for hardware acc= umulator + * @meas_regs: snapshot of raw measurements registers + * @ctrl_act_reg: snapshot of the ctrl_act register + * @ctrl_lat_reg: snapshot of the ctrl_lat register + * @acc_count: snapshot of the acc_count register + * @total_samples_nr: accumulated values for acc_count (total number of sa= mples) + * @acc_val: accumulated values per second + * @vacc: accumulated vpower values + * @vpower: snapshot of vpower registers + * @vbus: snapshot of vbus registers + * @vbus_avg: averages of vbus registers + * @vsense: snapshot of vsense registers + * @vsense_avg: averages of vsense registers + * @jiffies_tstamp: chip's uptime + */ +struct reg_data { + u8 vbus_mode[PAC1944_MAX_CH]; + u8 vsense_mode[PAC1944_MAX_CH]; + u8 accumulation_mode[PAC1944_MAX_CH]; + u8 meas_regs[PAC1944_MEAS_REG_SNAPSHOT_LEN]; + u16 ctrl_act_reg; + u16 ctrl_lat_reg; + u32 acc_count; + u32 total_samples_nr[PAC1944_MAX_CH]; + s64 acc_val[PAC1944_MAX_CH]; + s64 vacc[PAC1944_MAX_CH]; + s32 vpower[PAC1944_MAX_CH]; + s32 vbus[PAC1944_MAX_CH]; + s32 vbus_avg[PAC1944_MAX_CH]; + s32 vsense[PAC1944_MAX_CH]; + s32 vsense_avg[PAC1944_MAX_CH]; + unsigned long jiffies_tstamp; +}; + +/** + * struct pac1944_chip_info - chip configuration + * @channels: array of values, true means that channel is active + * @iio_info: pointer to iio_info structure + * @client: a pointer to the i2c client associated with the device + * @lock: lock to prevent concurrent reads/writes + * @work_chip_rfsh: chip refresh workqueue implementation + * @active_channels_mask: active channels + * @phys_channels: number of physical channels for the device + * @chip_variant: stores the type of the device + * @chip_revision: store the silicon revision version of the device + * @shunts: array of values, shunt resistor values + * @chip_reg_data: pointer to structure, containing data from the device r= egisters + * @sample_rate_value: sampling frequency + * @labels: array of string, name of each channel + * @is_pac195x_family: true if device is part of the PAC195x family + * @sampling_mode: sampling mode used by the device + * @num_enabled_channels: count of how many chip channels are currently en= abled + * @slow_alert1: snapshot of slow/alert register + * @gpio_alert2: snapshot of gpio/alert register + * @acc_fullness: snapshot of accumulator fullness limit register + * @overcurrent: array of values, overcurrent limit + * @undercurrent: array of values, undercurrent limit + * @overpower: array of values, overpower limit + * @overvoltage: array of values, overvoltage limit + * @undervoltage: array of values, undervoltage limit + * @oc_limit_nsamples: number of consecutive samples exceeding the overcur= rent limit + * @uc_limit_nsamples: number of consecutive samples exceeding the undercu= rrent limit + * @op_limit_nsamples: number of consecutive samples exceeding the overpow= er limit + * @ov_limit_nsamples: number of consecutive samples exceeding the overvol= tage limit + * @uv_limit_nsamples: number of consecutive samples exceeding the undervo= ltage limit + * @alert_enable: snapshot of alert enable register + * @enable_acc: array of values, true means that accumulation channel is m= easured + */ +struct pac1944_chip_info { + const struct iio_chan_spec *channels; + struct iio_info iio_info; + struct i2c_client *client; + struct mutex lock; /* lock to prevent concurrent reads/writes */ + struct delayed_work work_chip_rfsh; + unsigned long active_channels_mask; + u8 phys_channels; + u8 chip_variant; + u8 chip_revision; + u32 shunts[PAC1944_MAX_CH]; + struct reg_data chip_reg_data; + s32 sample_rate_value; + char *labels[PAC1944_MAX_CH]; + bool is_pac195x_family; + u8 sampling_mode; + u8 num_enabled_channels; + u32 slow_alert1; + u32 gpio_alert2; + u16 acc_fullness; + u16 overcurrent[PAC1944_MAX_CH]; + u16 undercurrent[PAC1944_MAX_CH]; + u32 overpower[PAC1944_MAX_CH]; + u16 overvoltage[PAC1944_MAX_CH]; + u16 undervoltage[PAC1944_MAX_CH]; + u8 oc_limit_nsamples[PAC1944_MAX_CH]; + u8 uc_limit_nsamples[PAC1944_MAX_CH]; + u8 op_limit_nsamples[PAC1944_MAX_CH]; + u8 ov_limit_nsamples[PAC1944_MAX_CH]; + u8 uv_limit_nsamples[PAC1944_MAX_CH]; + u32 alert_enable; + bool enable_acc[PAC1944_MAX_CH]; +}; + +/** + * struct pac1944_features - features of a pac194x instance + * @phys_channels: number of physical channels supported by the chip + * @prod_id: hardware ID + * @name: chip's name + */ +struct pac1944_features { + u8 phys_channels; + u8 prod_id; + const char *name; +}; + +static const struct pac1944_features pac1944_chip_config[] =3D { + /* PAC194X Family */ + [PAC1941] =3D { + .phys_channels =3D 1, + .prod_id =3D PAC_PRODUCT_ID_1941, + .name =3D "pac1941", + }, + [PAC1942] =3D { + .phys_channels =3D 2, + .prod_id =3D PAC_PRODUCT_ID_1942, + .name =3D "pac1942", + }, + [PAC1943] =3D { + .phys_channels =3D 3, + .prod_id =3D PAC_PRODUCT_ID_1943, + .name =3D "pac1943", + }, + [PAC1944] =3D { + .phys_channels =3D 4, + .prod_id =3D PAC_PRODUCT_ID_1944, + .name =3D "pac1944", + }, + [PAC1941_2] =3D { + .phys_channels =3D 1, + .prod_id =3D PAC_PRODUCT_ID_1941_2, + .name =3D "pac1941_2", + }, + [PAC1942_2] =3D { + .phys_channels =3D 2, + .prod_id =3D PAC_PRODUCT_ID_1942_2, + .name =3D "pac1942_2", + }, + /* PAC195X Family */ + [PAC1951] =3D { + .phys_channels =3D 1, + .prod_id =3D PAC_PRODUCT_ID_1951, + .name =3D "pac1951", + }, + [PAC1952] =3D { + .phys_channels =3D 2, + .prod_id =3D PAC_PRODUCT_ID_1952, + .name =3D "pac1952_1", + }, + [PAC1953] =3D { + .phys_channels =3D 3, + .prod_id =3D PAC_PRODUCT_ID_1953, + .name =3D "pac1953", + }, + [PAC1954] =3D { + .phys_channels =3D 4, + .prod_id =3D PAC_PRODUCT_ID_1954, + .name =3D "pac1954", + }, + [PAC1951_2] =3D { + .phys_channels =3D 1, + .prod_id =3D PAC_PRODUCT_ID_1951_2, + .name =3D "pac1951_2", + }, + [PAC1952_2] =3D { + .phys_channels =3D 2, + .prod_id =3D PAC_PRODUCT_ID_1952_2, + .name =3D "pac1952_2", + }, +}; + +static inline u64 pac1944_get_unaligned_be56(const u8 *p) +{ + return (u64)p[0] << 48 | (u64)p[1] << 40 | (u64)p[2] << 32 | + (u64)p[3] << 24 | p[4] << 16 | p[5] << 8 | p[6]; +} + +/* Low-level I2c functions used to transfer more then 32 bytes at once */ +static int pac1944_i2c_read(struct i2c_client *client, u8 reg_addr, + void *databuf, u8 len) +{ + struct i2c_msg msgs[2] =3D { + { .addr =3D client->addr, + .len =3D 1, + .buf =3D (u8 *)®_addr, + .flags =3D 0 + }, + { .addr =3D client->addr, + .len =3D len, + .buf =3D databuf, + .flags =3D I2C_M_RD + } + }; + + return i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); +} + +static int pac1944_disable_alert_reg(struct device *dev, u32 mask, u8 *sta= tus) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + u32 val; + u8 buf[PAC1944_ALERT_ENABLE_REG_LEN]; + + ret =3D i2c_smbus_read_i2c_block_data(client, + PAC1944_ALERT_ENABLE_REG_ADDR, + PAC1944_ALERT_ENABLE_REG_LEN, + status); + if (ret < 0) { + dev_err(dev, "failing to disable allert reg\n"); + return ret; + } + + val =3D get_unaligned_be24(status); + val =3D val & (~mask); + put_unaligned_be24(val, &buf[0]); + + /* disable appropriate bit from the Alert enable register */ + return i2c_smbus_write_block_data(client, PAC1944_ALERT_ENABLE_REG_ADDR, + PAC1944_ALERT_ENABLE_REG_LEN, + (u8 *)&buf[0]); +} + +static int pac1944_restore_alert_reg(struct iio_dev *indio_dev, u8 *status) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + + /* restoring the Alert enable register */ + ret =3D i2c_smbus_write_block_data(client, PAC1944_ALERT_ENABLE_REG_ADDR, + PAC1944_ALERT_ENABLE_REG_LEN, status); + if (ret) { + dev_err(&client->dev, "failing to write %s\n", __func__); + return ret; + } + + /* Sending a REFRESH_V to the chip, so the new settings take place */ + ret =3D i2c_smbus_write_byte(info->client, PAC1944_REFRESH_V_REG_ADDR); + if (ret) + dev_err(&client->dev, "cannot send REFRESH_V\n"); + + return ret; +} + +static int pac1944_update_alert_16b(struct device *dev, u8 addr, u32 mask, + u16 value) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + __be16 tmp_be16; + u8 status[PAC1944_ALERT_ENABLE_REG_LEN]; + + ret =3D pac1944_disable_alert_reg(dev, mask, &status[0]); + if (ret) { + dev_err(dev, "failed to disable alert reg\n"); + return ret; + } + + tmp_be16 =3D cpu_to_be16(value); + + ret =3D i2c_smbus_write_word_data(client, addr, tmp_be16); + if (ret) { + dev_err(dev, "failing to write at 0x%x\n", addr); + return ret; + } + + return pac1944_restore_alert_reg(indio_dev, &status[0]); +} + +static int pac1944_update_alert_24b(struct device *dev, u8 addr, u32 mask, + u32 value) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + u8 status[PAC1944_ALERT_ENABLE_REG_LEN], tmp[3]; + + ret =3D pac1944_disable_alert_reg(dev, mask, &status[0]); + if (ret) { + dev_err(dev, "failed to disable alert reg\n"); + return ret; + } + + put_unaligned_be24(value, &tmp[0]); + + ret =3D i2c_smbus_write_block_data(client, addr, ARRAY_SIZE(tmp), (u8 *)&= tmp[0]); + if (ret) { + dev_err(dev, "failing to write at 0x%x\n", addr); + return ret; + } + + return pac1944_restore_alert_reg(indio_dev, &status[0]); +} + +/* Custom IIO Device Attributes */ +static ssize_t pac1944_shunt_value_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + + return sysfs_emit(buf, "%u\n", info->shunts[this_attr->address]); +} + +static ssize_t pac1944_shunt_value_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int sh_val; + + if (kstrtouint(buf, 10, &sh_val)) { + dev_err(dev, "Shunt value is not valid\n"); + return -EINVAL; + } + + scoped_guard(mutex, &info->lock) + info->shunts[this_attr->address] =3D sh_val; + + return count; +} + +static ssize_t pac1944_slow_alert1_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + u32 val; + u8 tmp[3]; + + if (kstrtoint(buf, 10, &val)) + return -EINVAL; + + put_unaligned_be24(val, &tmp[0]); + + scoped_guard(mutex, &info->lock) { + ret =3D i2c_smbus_write_block_data(client, PAC1944_SLOW_ALERT1_REG_ADDR, + ARRAY_SIZE(tmp), (u8 *)&tmp[0]); + if (ret) { + dev_err(dev, "failing to write %s\n", __func__); + return ret; + } + + info->slow_alert1 =3D val; + } + + return count; +} + +#define PAC1944_SLOW_ALERT_SHOW(alert_name) \ +static ssize_t pac1944_##alert_name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); \ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); \ + \ + return sysfs_emit(buf, "%u\n", info->alert_name); \ + } + +PAC1944_SLOW_ALERT_SHOW(slow_alert1) +PAC1944_SLOW_ALERT_SHOW(gpio_alert2) + +static ssize_t pac1944_gpio_alert2_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + u32 val; + u8 tmp[3]; + + if (kstrtoint(buf, 10, &val)) + return -EINVAL; + + put_unaligned_be24(val, &tmp[0]); + + scoped_guard(mutex, &info->lock) { + ret =3D i2c_smbus_write_block_data(client, PAC1944_GPIO_ALERT2_REG_ADDR, + ARRAY_SIZE(tmp), (u8 *)&tmp[0]); + if (ret) { + dev_err(dev, "failing to write %s\n", __func__); + return ret; + } + + info->gpio_alert2 =3D val; + } + + return count; +} + +static IIO_DEVICE_ATTR(in_current1_shunt_resistor, 0644, + pac1944_shunt_value_show, pac1944_shunt_value_store, 0); +static IIO_DEVICE_ATTR(in_current2_shunt_resistor, 0644, + pac1944_shunt_value_show, pac1944_shunt_value_store, 1); +static IIO_DEVICE_ATTR(in_current3_shunt_resistor, 0644, + pac1944_shunt_value_show, pac1944_shunt_value_store, 2); +static IIO_DEVICE_ATTR(in_current4_shunt_resistor, 0644, + pac1944_shunt_value_show, pac1944_shunt_value_store, 3); + +static IIO_DEVICE_ATTR(slow_alert1_cfg, 0644, pac1944_slow_alert1_show, + pac1944_slow_alert1_store, 0); +static IIO_DEVICE_ATTR(gpio_alert2_cfg, 0644, pac1944_gpio_alert2_show, + pac1944_gpio_alert2_store, 0); + +static struct attribute *pac1944_all_attrs[] =3D { + &iio_dev_attr_in_current1_shunt_resistor.dev_attr.attr, + &iio_dev_attr_in_current2_shunt_resistor.dev_attr.attr, + &iio_dev_attr_in_current3_shunt_resistor.dev_attr.attr, + &iio_dev_attr_in_current4_shunt_resistor.dev_attr.attr, + &iio_dev_attr_slow_alert1_cfg.dev_attr.attr, + &iio_dev_attr_gpio_alert2_cfg.dev_attr.attr, + NULL +}; + +static const struct iio_event_spec pac1944_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +static const struct iio_event_spec pac1944_single_event[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_separate =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +#define PAC1944_VBUS_CHANNEL(_index, _address, _ev_spec, _num_ev_spec) {\ + .type =3D IIO_VOLTAGE, \ + .address =3D (_address), \ + .indexed =3D 1, \ + .channel =3D (_index) + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .event_spec =3D (_ev_spec), \ + .num_event_specs =3D (_num_ev_spec), \ + .ext_info =3D pac1944_ext_info \ +} + +#define PAC1944_VBUS_AVG_CHANNEL(_index, _address) {\ + .type =3D IIO_VOLTAGE, \ + .address =3D (_address), \ + .indexed =3D 1, \ + .channel =3D (_index) + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info =3D pac1944_ext_info \ +} + +#define PAC1944_VSENSE_CHANNEL(_index, _address, _ev_spec, _num_ev_spec) {\ + .type =3D IIO_CURRENT, \ + .address =3D (_address), \ + .indexed =3D 1, \ + .channel =3D (_index) + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .event_spec =3D (_ev_spec), \ + .num_event_specs =3D (_num_ev_spec), \ + .ext_info =3D pac1944_ext_info \ +} + +#define PAC1944_VSENSE_AVG_CHANNEL(_index, _address) { \ + .type =3D IIO_CURRENT, \ + .address =3D (_address), \ + .indexed =3D 1, \ + .channel =3D (_index) + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info =3D pac1944_ext_info \ +} + +#define PAC1944_VPOWER_CHANNEL(_index, _address, _ev_spec, _num_ev_spec) {\ + .type =3D IIO_POWER, \ + .address =3D (_address), \ + .indexed =3D 1, \ + .channel =3D (_index) + 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .event_spec =3D (_ev_spec), \ + .num_event_specs =3D (_num_ev_spec), \ + .ext_info =3D pac1944_ext_info \ +} + +static int pac1944_send_refresh(struct pac1944_chip_info *info, u8 refresh= _cmd, + u32 wait_time) +{ + struct i2c_client *client =3D info->client; + int ret; + + /* Writing a REFRESH or a REFRESH_V command */ + ret =3D i2c_smbus_write_byte(client, refresh_cmd); + if (ret) { + dev_err(&client->dev, "%s - cannot send Refresh cmd (0x%02X) to PAC1944\= n", + __func__, refresh_cmd); + return ret; + } + + /* Register data retrieval timestamp */ + info->chip_reg_data.jiffies_tstamp =3D jiffies; + /* Wait till the data is available */ + usleep_range(wait_time, wait_time + 100); + + return 0; +} + +static int pac1944_reg_snapshot(struct pac1944_chip_info *info, bool do_re= fresh, + u8 refresh_cmd, u32 wait_time) +{ + struct i2c_client *client =3D info->client; + struct device *dev =3D &client->dev; + u8 shift, idx; + u8 *offset_reg_data_p; + int cnt, ret; + u32 count, inc_count; + u32 fs =3D 0; + s64 stored_value, tmp_s64; + s64 inc =3D 0; + __be16 tmp_be16; + u16 smpl_mode; + bool is_unipolar; + + guard(mutex)(&info->lock); + + if (do_refresh) { + ret =3D pac1944_send_refresh(info, refresh_cmd, wait_time); + if (ret < 0) { + dev_err(dev, "cannot send refresh towards PAC1944\n"); + return ret; + } + } + + /* Read the ctrl/status registers for this snapshot */ + ret =3D i2c_smbus_read_i2c_block_data(client, PAC1944_CTRL_ACT_REG_ADDR, + sizeof(tmp_be16), (u8 *)&tmp_be16); + if (ret < 0) { + dev_err(dev, "cannot read PAC1944 regs from 0x%02X\n", PAC1944_CTRL_ACT_= REG_ADDR); + return ret; + } + + info->chip_reg_data.ctrl_act_reg =3D be16_to_cpu(tmp_be16); + + ret =3D i2c_smbus_read_i2c_block_data(client, PAC1944_CTRL_LAT_REG_ADDR, + sizeof(tmp_be16), (u8 *)&tmp_be16); + if (ret < 0) { + dev_err(dev, "cannot read PAC1944 regs from 0x%02X\n", PAC1944_CTRL_LAT_= REG_ADDR); + return ret; + } + + info->chip_reg_data.ctrl_lat_reg =3D be16_to_cpu(tmp_be16); + + /* Read the data registers */ + ret =3D pac1944_i2c_read(client, PAC1944_ACC_COUNT_REG_ADDR, + (u8 *)info->chip_reg_data.meas_regs, + PAC1944_MEAS_REG_SNAPSHOT_LEN); + if (ret < 0) { + dev_err(dev, "cannot read PAC1944 regs from 0x%02X\n", PAC1944_ACC_COUNT= _REG_ADDR); + return ret; + } + + offset_reg_data_p =3D &info->chip_reg_data.meas_regs[0]; + + info->chip_reg_data.acc_count =3D get_unaligned_be32(offset_reg_data_p); + + offset_reg_data_p +=3D PAC1944_ACC_REG_LEN; + + /* + * Check if the channel is active (within the data read from + * the chip), skip all fields if disabled + */ + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + /* skip if the energy accumulation is disabled */ + if (!info->enable_acc[cnt]) { + offset_reg_data_p +=3D PAC1944_VACC_REG_LEN; + continue; + } + + stored_value =3D info->chip_reg_data.acc_val[cnt]; + + info->chip_reg_data.vacc[cnt] =3D pac1944_get_unaligned_be56(offset_reg_= data_p); + + is_unipolar =3D true; + switch (info->chip_reg_data.accumulation_mode[cnt]) { + case PAC1944_ACCMODE_VPOWER: + if (info->chip_reg_data.vbus_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG || + info->chip_reg_data.vsense_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + is_unipolar =3D false; + break; + case PAC1944_ACCMODE_VBUS: + if (info->chip_reg_data.vbus_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + is_unipolar =3D false; + break; + case PAC1944_ACCMODE_VSENSE: + if (info->chip_reg_data.vsense_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + is_unipolar =3D false; + break; + } + + if (!is_unipolar) + info->chip_reg_data.vacc[cnt] =3D + sign_extend64(info->chip_reg_data.vacc[cnt], 55); + + if (info->chip_reg_data.accumulation_mode[cnt] !=3D PAC1944_ACCMODE_VBUS= ) { + /* + * Integrate the accumulated power or current over + * the elapsed interval. + */ + smpl_mode =3D info->chip_reg_data.ctrl_lat_reg >> 12; + + tmp_s64 =3D info->chip_reg_data.vacc[cnt]; + if (smpl_mode < PAC1944_SAMP_FAST_MODE) { + /* + * Find how much shift is required by the sample rate + * The chip's sampling rate is 2^shift samples/sec + */ + shift =3D shift_map_tbl[smpl_mode]; + inc =3D tmp_s64 >> shift; + } else if (smpl_mode <=3D PAC1944_SAMP_BURST_MODE) { + idx =3D info->num_enabled_channels - 1; + + if (smpl_mode =3D=3D PAC1944_SAMP_FAST_MODE) + fs =3D samp_rate_fast_mode_tbl[idx]; + else + /* smpl_mode =3D=3D PAC1944_SAMP_BURST_MODE) */ + fs =3D samp_rate_burst_mode_tbl[idx]; + + inc =3D div_u64(abs(tmp_s64), fs); + if (tmp_s64 < 0) + inc =3D -inc; + } else { + dev_err(dev, "Invalid sample rate index: %d!\n", smpl_mode); + return -EIO; + } + } else { + count =3D info->chip_reg_data.total_samples_nr[cnt]; + inc_count =3D info->chip_reg_data.acc_count; + + /* Check if total number of samples will overflow */ + if (check_add_overflow(count, inc_count, &count)) { + dev_err(dev, "Number of samples on channel [%d] overflow!\n", + cnt + 1); + info->chip_reg_data.total_samples_nr[cnt] =3D 0; + info->chip_reg_data.acc_val[cnt] =3D 0; + } + + info->chip_reg_data.total_samples_nr[cnt] +=3D inc_count; + + inc =3D info->chip_reg_data.vacc[cnt]; + } + + if (check_add_overflow(stored_value, inc, &stored_value)) { + if (is_negative(stored_value)) + info->chip_reg_data.acc_val[cnt] =3D S64_MIN; + else + info->chip_reg_data.acc_val[cnt] =3D S64_MAX; + + dev_err(dev, "Overflow detected on channel [%d]!\n", cnt + 1); + } else { + info->chip_reg_data.acc_val[cnt] +=3D inc; + } + + offset_reg_data_p +=3D PAC1944_VACC_REG_LEN; + } + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + info->chip_reg_data.vbus[cnt] =3D get_unaligned_be16(offset_reg_data_p); + + if (info->chip_reg_data.vbus_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + info->chip_reg_data.vbus[cnt] =3D + sign_extend32(info->chip_reg_data.vbus[cnt], 15); + + offset_reg_data_p +=3D PAC1944_VBUS_SENSE_REG_LEN; + } + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + info->chip_reg_data.vsense[cnt] =3D get_unaligned_be16(offset_reg_data_p= ); + + if (info->chip_reg_data.vsense_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + info->chip_reg_data.vsense[cnt] =3D + sign_extend32(info->chip_reg_data.vsense[cnt], 15); + + offset_reg_data_p +=3D PAC1944_VBUS_SENSE_REG_LEN; + } + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + info->chip_reg_data.vbus_avg[cnt] =3D get_unaligned_be16(offset_reg_data= _p); + + if (info->chip_reg_data.vbus_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + info->chip_reg_data.vbus_avg[cnt] =3D + sign_extend32(info->chip_reg_data.vbus_avg[cnt], 15); + + offset_reg_data_p +=3D PAC1944_VBUS_SENSE_REG_LEN; + } + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + info->chip_reg_data.vsense_avg[cnt] =3D get_unaligned_be16(offset_reg_da= ta_p); + + if (info->chip_reg_data.vsense_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + info->chip_reg_data.vsense_avg[cnt] =3D + sign_extend32(info->chip_reg_data.vsense_avg[cnt], 15); + + offset_reg_data_p +=3D PAC1944_VBUS_SENSE_REG_LEN; + } + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + info->chip_reg_data.vpower[cnt] =3D get_unaligned_be32(offset_reg_data_p= ) >> 2; + + if (info->chip_reg_data.vbus_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG || + info->chip_reg_data.vsense_mode[cnt] !=3D PAC1944_UNIPOLAR_FSR_CFG) + info->chip_reg_data.vpower[cnt] =3D + sign_extend32(info->chip_reg_data.vpower[cnt], 29); + + offset_reg_data_p +=3D PAC1944_VPOWER_REG_LEN; + } + + return 0; +} + +static int pac1944_retrieve_data(struct pac1944_chip_info *info, u32 wait_= time) +{ + int ret =3D 0; + + /* + * Check if the minimal elapsed time has passed and if so, + * re-read the chip, otherwise the cached info is just fine + */ + if (time_after(jiffies, info->chip_reg_data.jiffies_tstamp + + msecs_to_jiffies(PAC1944_MIN_POLLING_TIME_MS))) { + /* + * We need to re-read the chip values + * call the pac1944_reg_snapshot + */ + ret =3D pac1944_reg_snapshot(info, true, PAC1944_REFRESH_REG_ADDR, + wait_time); + /* + * Re-schedule the work for the read registers timeout + * (to prevent chip regs saturation) + */ + cancel_delayed_work_sync(&info->work_chip_rfsh); + schedule_delayed_work(&info->work_chip_rfsh, + msecs_to_jiffies(PAC1944_MAX_RFSH_LIMIT_MS)); + } + + return ret; +} + +static ssize_t pac1944_in_power_acc_raw_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int ret; + s64 curr_energy, int_part; + int rem; + + ret =3D pac1944_retrieve_data(info, PAC1944_MIN_UPDATE_WAIT_TIME_US); + if (ret < 0) + return 0; + + /* + * Expresses the 64 bit energy value as a + * 64 bit integer and a 32 bit nano value + */ + curr_energy =3D info->chip_reg_data.acc_val[this_attr->address]; + int_part =3D div_s64_rem(curr_energy, 1000000000, &rem); + + if (rem < 0) + return sysfs_emit(buf, "-%lld.%09u\n", abs(int_part), -rem); + else + return sysfs_emit(buf, "%lld.%09u\n", int_part, abs(rem)); +} + +static ssize_t pac1944_in_power_acc_scale_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + unsigned int shunt, rem; + u64 tmp, ref; + + if (info->is_pac195x_family) + ref =3D PAC195X_MAX_VPOWER_RSHIFTED_BY_29B; + else + ref =3D PAC194X_MAX_VPOWER_RSHIFTED_BY_29B; + + if ((info->chip_reg_data.vbus_mode[this_attr->address] =3D=3D PAC1944_UNI= POLAR_FSR_CFG && + info->chip_reg_data.vsense_mode[this_attr->address] =3D=3D PAC1944_U= NIPOLAR_FSR_CFG) || + info->chip_reg_data.vbus_mode[this_attr->address] =3D=3D PAC1944_BIPO= LAR_HALF_FSR_CFG || + info->chip_reg_data.vsense_mode[this_attr->address] =3D=3D PAC1944_BI= POLAR_HALF_FSR_CFG) + ref =3D ref >> 1; + + shunt =3D info->shunts[this_attr->address]; + + tmp =3D div_u64(ref * 1000000000LL, shunt); + rem =3D do_div(tmp, 1000000000LL); + + return sysfs_emit(buf, "%lld.%09u\n", tmp, rem); +} + +static ssize_t pac1944_in_enable_acc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + + return sysfs_emit(buf, "%d\n", info->enable_acc[this_attr->address]); +} + +static ssize_t pac1944_in_enable_acc_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int val; + + if (kstrtouint(buf, 10, &val)) { + dev_err(dev, "Value is not valid\n"); + return -EINVAL; + } + + scoped_guard(mutex, &info->lock) { + info->enable_acc[this_attr->address] =3D val ? true : false; + if (val) { + info->chip_reg_data.acc_val[this_attr->address] =3D 0; + info->chip_reg_data.total_samples_nr[this_attr->address] =3D 0; + } + } + + return count; +} + +static ssize_t pac1944_in_current_acc_raw_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int ret; + + ret =3D pac1944_retrieve_data(info, PAC1944_MIN_UPDATE_WAIT_TIME_US); + if (ret < 0) + return ret; + + return sysfs_emit(buf, "%lld\n", info->chip_reg_data.acc_val[this_attr->a= ddress]); +} + +static ssize_t pac1944_in_current_acc_scale_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int shunt, rem; + u64 tmp_u64, ref; + + /* + * Currents - scale for mA - depends on the channel's shunt value + * (100mV * 1000000) / (2^16 * shunt(uOhm)) + */ + ref =3D PAC1944_MAX_VSENSE_NANO; + + switch (info->chip_reg_data.vsense_mode[this_attr->address]) { + case PAC1944_UNIPOLAR_FSR_CFG: + case PAC1944_BIPOLAR_HALF_FSR_CFG: + shunt =3D info->shunts[this_attr->address]; + break; + case PAC1944_BIPOLAR_FSR_CFG: + ref =3D ref << 1; + shunt =3D info->shunts[this_attr->address]; + break; + default: + return -EINVAL; + } + + /* + * Increasing precision + * (100mV * 1000000 * 1000000000) / 2^16 ) + */ + tmp_u64 =3D div_u64(ref, shunt); + rem =3D do_div(tmp_u64, 1000000000LL); + + return sysfs_emit(buf, "%lld.%09u\n", tmp_u64, rem); +} + +static ssize_t pac1944_in_voltage_acc_raw_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int ret; + s64 acc_voltage; + u32 samples_count; + u64 tmp_u64; + + ret =3D pac1944_retrieve_data(info, PAC1944_MIN_UPDATE_WAIT_TIME_US); + if (ret < 0) + return ret; + + acc_voltage =3D info->chip_reg_data.acc_val[this_attr->address]; + samples_count =3D info->chip_reg_data.total_samples_nr[this_attr->address= ]; + + tmp_u64 =3D div_u64(abs(acc_voltage), samples_count); + + if (is_negative(acc_voltage)) + return sysfs_emit(buf, "-%lld\n", tmp_u64); + else + return sysfs_emit(buf, "%lld\n", tmp_u64); +} + +static ssize_t pac1944_in_voltage_acc_scale_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); + int vals[2]; + unsigned long long tmp; + + if (info->is_pac195x_family) + vals[0] =3D PAC195X_VOLTAGE_MILLIVOLTS_MAX; + else + vals[0] =3D PAC194X_VOLTAGE_MILLIVOLTS_MAX; + + if (info->chip_reg_data.vbus_mode[this_attr->address] !=3D PAC1944_BIPOLA= R_FSR_CFG) + /* PAC1944_UNIPOLAR_FSR_CFG or PAC1944_BIPOLAR_HALF_FSR_CFG */ + vals[1] =3D PAC1944_VOLTAGE_16B_RES; + else + vals[1] =3D PAC1944_VOLTAGE_15B_RES; + + tmp =3D (s64)vals[0] * 1000000000LL >> vals[1]; + vals[1] =3D do_div(tmp, 1000000000LL); + vals[0] =3D tmp; + + return sysfs_emit(buf, "%d.%09u\n", vals[0], vals[1]); +} + +static IIO_DEVICE_ATTR(in_energy1_raw, 0444, pac1944_in_power_acc_raw_show= , NULL, 0); +static IIO_DEVICE_ATTR(in_energy2_raw, 0444, pac1944_in_power_acc_raw_show= , NULL, 1); +static IIO_DEVICE_ATTR(in_energy3_raw, 0444, pac1944_in_power_acc_raw_show= , NULL, 2); +static IIO_DEVICE_ATTR(in_energy4_raw, 0444, pac1944_in_power_acc_raw_show= , NULL, 3); + +static IIO_DEVICE_ATTR(in_energy1_scale, 0444, pac1944_in_power_acc_scale_= show, NULL, 0); +static IIO_DEVICE_ATTR(in_energy2_scale, 0444, pac1944_in_power_acc_scale_= show, NULL, 1); +static IIO_DEVICE_ATTR(in_energy3_scale, 0444, pac1944_in_power_acc_scale_= show, NULL, 2); +static IIO_DEVICE_ATTR(in_energy4_scale, 0444, pac1944_in_power_acc_scale_= show, NULL, 3); + +static IIO_DEVICE_ATTR(in_energy1_en, 0644, pac1944_in_enable_acc_show, + pac1944_in_enable_acc_store, 0); +static IIO_DEVICE_ATTR(in_energy2_en, 0644, pac1944_in_enable_acc_show, + pac1944_in_enable_acc_store, 1); +static IIO_DEVICE_ATTR(in_energy3_en, 0644, pac1944_in_enable_acc_show, + pac1944_in_enable_acc_store, 2); +static IIO_DEVICE_ATTR(in_energy4_en, 0644, pac1944_in_enable_acc_show, + pac1944_in_enable_acc_store, 3); + +static IIO_DEVICE_ATTR(in_current_acc1_raw, 0444, pac1944_in_current_acc_r= aw_show, NULL, 0); +static IIO_DEVICE_ATTR(in_current_acc2_raw, 0444, pac1944_in_current_acc_r= aw_show, NULL, 1); +static IIO_DEVICE_ATTR(in_current_acc3_raw, 0444, pac1944_in_current_acc_r= aw_show, NULL, 2); +static IIO_DEVICE_ATTR(in_current_acc4_raw, 0444, pac1944_in_current_acc_r= aw_show, NULL, 3); + +static IIO_DEVICE_ATTR(in_current_acc1_scale, 0444, pac1944_in_current_acc= _scale_show, NULL, 0); +static IIO_DEVICE_ATTR(in_current_acc2_scale, 0444, pac1944_in_current_acc= _scale_show, NULL, 1); +static IIO_DEVICE_ATTR(in_current_acc3_scale, 0444, pac1944_in_current_acc= _scale_show, NULL, 2); +static IIO_DEVICE_ATTR(in_current_acc4_scale, 0444, pac1944_in_current_acc= _scale_show, NULL, 3); + +static IIO_DEVICE_ATTR(in_current_acc1_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 0); +static IIO_DEVICE_ATTR(in_current_acc2_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 1); +static IIO_DEVICE_ATTR(in_current_acc3_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 2); +static IIO_DEVICE_ATTR(in_current_acc4_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 3); + +static IIO_DEVICE_ATTR(in_voltage_acc1_raw, 0444, pac1944_in_voltage_acc_r= aw_show, NULL, 0); +static IIO_DEVICE_ATTR(in_voltage_acc2_raw, 0444, pac1944_in_voltage_acc_r= aw_show, NULL, 1); +static IIO_DEVICE_ATTR(in_voltage_acc3_raw, 0444, pac1944_in_voltage_acc_r= aw_show, NULL, 2); +static IIO_DEVICE_ATTR(in_voltage_acc4_raw, 0444, pac1944_in_voltage_acc_r= aw_show, NULL, 3); + +static IIO_DEVICE_ATTR(in_voltage_acc1_scale, 0444, pac1944_in_voltage_acc= _scale_show, NULL, 0); +static IIO_DEVICE_ATTR(in_voltage_acc2_scale, 0444, pac1944_in_voltage_acc= _scale_show, NULL, 1); +static IIO_DEVICE_ATTR(in_voltage_acc3_scale, 0444, pac1944_in_voltage_acc= _scale_show, NULL, 2); +static IIO_DEVICE_ATTR(in_voltage_acc4_scale, 0444, pac1944_in_voltage_acc= _scale_show, NULL, 3); + +static IIO_DEVICE_ATTR(in_voltage_acc1_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 0); +static IIO_DEVICE_ATTR(in_voltage_acc2_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 1); +static IIO_DEVICE_ATTR(in_voltage_acc3_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 2); +static IIO_DEVICE_ATTR(in_voltage_acc4_en, 0644, pac1944_in_enable_acc_sho= w, + pac1944_in_enable_acc_store, 3); + +static struct attribute *pac1944_power_acc_attr[] =3D { + &iio_dev_attr_in_energy1_raw.dev_attr.attr, + &iio_dev_attr_in_energy2_raw.dev_attr.attr, + &iio_dev_attr_in_energy3_raw.dev_attr.attr, + &iio_dev_attr_in_energy4_raw.dev_attr.attr, + &iio_dev_attr_in_energy1_scale.dev_attr.attr, + &iio_dev_attr_in_energy2_scale.dev_attr.attr, + &iio_dev_attr_in_energy3_scale.dev_attr.attr, + &iio_dev_attr_in_energy4_scale.dev_attr.attr, + &iio_dev_attr_in_energy1_en.dev_attr.attr, + &iio_dev_attr_in_energy2_en.dev_attr.attr, + &iio_dev_attr_in_energy3_en.dev_attr.attr, + &iio_dev_attr_in_energy4_en.dev_attr.attr, + NULL +}; + +static struct attribute *pac1944_current_acc_attr[] =3D { + &iio_dev_attr_in_current_acc1_raw.dev_attr.attr, + &iio_dev_attr_in_current_acc2_raw.dev_attr.attr, + &iio_dev_attr_in_current_acc3_raw.dev_attr.attr, + &iio_dev_attr_in_current_acc4_raw.dev_attr.attr, + &iio_dev_attr_in_current_acc1_scale.dev_attr.attr, + &iio_dev_attr_in_current_acc2_scale.dev_attr.attr, + &iio_dev_attr_in_current_acc3_scale.dev_attr.attr, + &iio_dev_attr_in_current_acc4_scale.dev_attr.attr, + &iio_dev_attr_in_current_acc1_en.dev_attr.attr, + &iio_dev_attr_in_current_acc2_en.dev_attr.attr, + &iio_dev_attr_in_current_acc3_en.dev_attr.attr, + &iio_dev_attr_in_current_acc4_en.dev_attr.attr, + NULL +}; + +static struct attribute *pac1944_voltage_acc_attr[] =3D { + &iio_dev_attr_in_voltage_acc1_raw.dev_attr.attr, + &iio_dev_attr_in_voltage_acc2_raw.dev_attr.attr, + &iio_dev_attr_in_voltage_acc3_raw.dev_attr.attr, + &iio_dev_attr_in_voltage_acc4_raw.dev_attr.attr, + &iio_dev_attr_in_voltage_acc1_scale.dev_attr.attr, + &iio_dev_attr_in_voltage_acc2_scale.dev_attr.attr, + &iio_dev_attr_in_voltage_acc3_scale.dev_attr.attr, + &iio_dev_attr_in_voltage_acc4_scale.dev_attr.attr, + &iio_dev_attr_in_voltage_acc1_en.dev_attr.attr, + &iio_dev_attr_in_voltage_acc2_en.dev_attr.attr, + &iio_dev_attr_in_voltage_acc3_en.dev_attr.attr, + &iio_dev_attr_in_voltage_acc4_en.dev_attr.attr, + NULL +}; + +static int pac1944_prep_custom_attributes(struct pac1944_chip_info *info, + struct iio_dev *indio_dev) +{ + int ch, i, j; + int active_channels_count =3D 0; + struct attribute **pac1944_custom_attrs, **tmp_attr; + struct attribute_group *pac1944_group; + int custom_attr_cnt; + struct i2c_client *client =3D info->client; + + active_channels_count =3D info->num_enabled_channels; + + pac1944_group =3D devm_kzalloc(&client->dev, sizeof(*pac1944_group), GFP_= KERNEL); + if (!pac1944_group) + return -ENOMEM; + + /* + * Attributes for channel X: + * - in_shunt_value_X + * - one of pair attributes: + * - in_power_accX_raw and in_power_accX_scale + * - in_current_accX_raw and in_current_accX_scale + * - in_voltage_accX_raw and in_voltage_accX_scale + * Shared attributes: + * - slow_alert1_cfg + * - gpio_alert2_cfg + * NULL + */ + custom_attr_cnt =3D PAC1944_COMMON_DEVATTR * active_channels_count; + custom_attr_cnt +=3D PAC1944_ACC_DEVATTR * active_channels_count; + custom_attr_cnt +=3D PAC1944_SHARED_DEVATTRS_COUNT; + + pac1944_custom_attrs =3D devm_kzalloc(&client->dev, custom_attr_cnt * + sizeof(*pac1944_group) + 1, GFP_KERNEL); + if (!pac1944_custom_attrs) + return -ENOMEM; + + j =3D 0; + + for_each_set_bit(ch, &info->active_channels_mask, info->phys_channels) { + for (i =3D 0; i < PAC1944_COMMON_DEVATTR; i++) + pac1944_custom_attrs[j++] =3D + pac1944_all_attrs[PAC1944_COMMON_DEVATTR * ch + i]; + + switch (info->chip_reg_data.accumulation_mode[ch]) { + case PAC1944_ACCMODE_VPOWER: + tmp_attr =3D pac1944_power_acc_attr; + break; + case PAC1944_ACCMODE_VSENSE: + tmp_attr =3D pac1944_current_acc_attr; + break; + case PAC1944_ACCMODE_VBUS: + tmp_attr =3D pac1944_voltage_acc_attr; + break; + default: + return -EINVAL; + } + + pac1944_custom_attrs[j++] =3D tmp_attr[ch]; + pac1944_custom_attrs[j++] =3D pac1944_power_acc_attr[PAC1944_MAX_CH + ch= ]; + pac1944_custom_attrs[j++] =3D pac1944_power_acc_attr[2 * PAC1944_MAX_CH = + ch]; + } + + for (i =3D 0; i < PAC1944_SHARED_DEVATTRS_COUNT; i++) + pac1944_custom_attrs[j++] =3D + pac1944_all_attrs[PAC1944_COMMON_DEVATTR * PAC1944_MAX_CH + i]; + + pac1944_group->attrs =3D pac1944_custom_attrs; + info->iio_info.attrs =3D pac1944_group; + + return 0; +} + +static int pac1944_frequency_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int ret; + u16 tmp_u16; + __be16 tmp_be16; + + ret =3D i2c_smbus_read_i2c_block_data(client, PAC1944_CTRL_ACT_REG_ADDR, + sizeof(tmp_u16), (u8 *)&tmp_be16); + if (ret < 0) { + dev_err(&client->dev, "cannot read PAC1944 regs from 0x%02X\n", + PAC1944_CTRL_ACT_REG_ADDR); + return ret; + } + + tmp_u16 =3D be16_to_cpu(tmp_be16); + tmp_u16 &=3D ~PAC1944_CTRL_SAMPLE_MASK; + tmp_u16 |=3D FIELD_PREP(PAC1944_CTRL_SAMPLE_MASK, mode); + tmp_be16 =3D cpu_to_be16(tmp_u16); + + scoped_guard(mutex, &info->lock) { + ret =3D i2c_smbus_write_word_data(client, PAC1944_CTRL_REG_ADDR, tmp_be1= 6); + if (ret < 0) { + dev_err(&client->dev, "Failed to configure sampling mode\n"); + return ret; + } + + info->sampling_mode =3D mode; + info->chip_reg_data.ctrl_act_reg =3D tmp_u16; + } + + return pac1944_retrieve_data(info, PAC1944_MIN_UPDATE_WAIT_TIME_US); +} + +static int pac1944_frequency_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + + return info->sampling_mode; +} + +static const struct iio_enum sampling_mode_enum =3D { + .items =3D pac1944_frequency_avail, + .num_items =3D ARRAY_SIZE(pac1944_frequency_avail), + .set =3D pac1944_frequency_set, + .get =3D pac1944_frequency_get, +}; + +static const struct iio_chan_spec_ext_info pac1944_ext_info[] =3D { + IIO_ENUM("sampling_frequency", IIO_SHARED_BY_ALL, &sampling_mode_enum), + { + .name =3D "sampling_frequency_available", + .shared =3D IIO_SHARED_BY_ALL, + .read =3D iio_enum_available_read, + .private =3D (uintptr_t)&sampling_mode_enum, + }, + { } +}; + +static int pac1944_read_raw(struct iio_dev *indio_dev, struct iio_chan_spe= c const *chan, + int *val, int *val2, long mask) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + int ret, idx; + u64 tmp; + + ret =3D pac1944_retrieve_data(info, PAC1944_MIN_UPDATE_WAIT_TIME_US); + if (ret < 0) + return ret; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + /* + * For AVG the index should be between 5 to 8. To calculate + * PAC1944_CH_VOLTAGE_AVERAGE and PAC1944_CH_CURRENT_AVERAGE real index, + * we need to remove the added offset (PAC1944_MAX_CH). + */ + if (idx >=3D PAC1944_MAX_CH) + idx =3D idx - PAC1944_MAX_CH; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + switch (chan->type) { + case IIO_VOLTAGE: + *val =3D info->chip_reg_data.vbus[idx]; + return IIO_VAL_INT; + case IIO_CURRENT: + *val =3D info->chip_reg_data.vsense[idx]; + return IIO_VAL_INT; + case IIO_POWER: + *val =3D info->chip_reg_data.vpower[idx]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_AVERAGE_RAW: + switch (chan->type) { + case IIO_VOLTAGE: + *val =3D info->chip_reg_data.vbus_avg[idx]; + return IIO_VAL_INT; + case IIO_CURRENT: + *val =3D info->chip_reg_data.vsense_avg[idx]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SCALE: + switch (chan->address) { + case PAC1944_VBUS_1_ADDR: + case PAC1944_VBUS_2_ADDR: + case PAC1944_VBUS_3_ADDR: + case PAC1944_VBUS_4_ADDR: + case PAC1944_VBUS_AVG_1_ADDR: + case PAC1944_VBUS_AVG_2_ADDR: + case PAC1944_VBUS_AVG_3_ADDR: + case PAC1944_VBUS_AVG_4_ADDR: + if (info->is_pac195x_family) + *val =3D PAC195X_VOLTAGE_MILLIVOLTS_MAX; + else + *val =3D PAC194X_VOLTAGE_MILLIVOLTS_MAX; + + switch (info->chip_reg_data.vbus_mode[idx]) { + case PAC1944_UNIPOLAR_FSR_CFG: + case PAC1944_BIPOLAR_HALF_FSR_CFG: + *val2 =3D PAC1944_VOLTAGE_16B_RES; + break; + case PAC1944_BIPOLAR_FSR_CFG: + *val2 =3D PAC1944_VOLTAGE_15B_RES; + break; + default: + return -EINVAL; + } + return IIO_VAL_FRACTIONAL_LOG2; + /* + * Currents - scale for mA - depends on the + * channel's shunt value + * (100mV * 1000000) / (2^16 * shunt(microOhm)) + */ + case PAC1944_VSENSE_1_ADDR: + case PAC1944_VSENSE_2_ADDR: + case PAC1944_VSENSE_3_ADDR: + case PAC1944_VSENSE_4_ADDR: + case PAC1944_VSENSE_AVG_1_ADDR: + case PAC1944_VSENSE_AVG_2_ADDR: + case PAC1944_VSENSE_AVG_3_ADDR: + case PAC1944_VSENSE_AVG_4_ADDR: + *val =3D PAC1944_MAX_VSENSE_RSHIFTED_BY_15B; + switch (info->chip_reg_data.vsense_mode[idx]) { + case PAC1944_UNIPOLAR_FSR_CFG: + case PAC1944_BIPOLAR_HALF_FSR_CFG: + *val =3D *val >> 1; + *val2 =3D info->shunts[idx]; + break; + case PAC1944_BIPOLAR_FSR_CFG: + *val2 =3D info->shunts[idx]; + break; + default: + return -EINVAL; + } + return IIO_VAL_FRACTIONAL; + /* + * Power - mW - it will use the combined scale + * for current and voltage + * current(mA) * voltage(mV) =3D power (uW) + */ + case PAC1944_VPOWER_1_ADDR: + case PAC1944_VPOWER_2_ADDR: + case PAC1944_VPOWER_3_ADDR: + case PAC1944_VPOWER_4_ADDR: + if (info->is_pac195x_family) + tmp =3D PAC195X_PRODUCT_VOLTAGE_PV_FSR; + else + tmp =3D PAC194X_PRODUCT_VOLTAGE_PV_FSR; + + do_div(tmp, info->shunts[idx]); + *val =3D (int)tmp; + if ((info->chip_reg_data.vbus_mode[idx] =3D=3D PAC1944_UNIPOLAR_FSR_CFG= && + info->chip_reg_data.vsense_mode[idx] =3D=3D PAC1944_UNIPOLAR_FSR_C= FG) || + info->chip_reg_data.vbus_mode[idx] =3D=3D PAC1944_BIPOLAR_HALF_FSR_= CFG || + info->chip_reg_data.vsense_mode[idx] =3D=3D PAC1944_BIPOLAR_HALF_FS= R_CFG) + *val2 =3D PAC1944_POWER_30B_RES; + else + *val2 =3D PAC1944_POWER_29B_RES; + + return IIO_VAL_FRACTIONAL_LOG2; + } + } + + return -EINVAL; +} + +static int pac1944_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + int idx; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + /* + * For AVG the index should be between 5 to 8. + * To calculate PAC1944_CH_VOLTAGE_AVERAGE and + * PAC1944_CH_CURRENT_AVERAGE real index, we need + * to remove the added offset (PAC1944_MAX_CH). + */ + if (idx >=3D PAC1944_MAX_CH) + idx =3D idx - PAC1944_MAX_CH; + + switch (chan->address) { + case PAC1944_VBUS_1_ADDR: + case PAC1944_VBUS_2_ADDR: + case PAC1944_VBUS_3_ADDR: + case PAC1944_VBUS_4_ADDR: + if (info->labels[idx]) + return sysfs_emit(label, "%s_VBUS_%d\n", info->labels[idx], idx + 1); + else + return sysfs_emit(label, "VBUS_%d\n", idx + 1); + case PAC1944_VBUS_AVG_1_ADDR: + case PAC1944_VBUS_AVG_2_ADDR: + case PAC1944_VBUS_AVG_3_ADDR: + case PAC1944_VBUS_AVG_4_ADDR: + if (info->labels[idx]) + return sysfs_emit(label, "%s_VBUS_AVG_%d\n", info->labels[idx], idx + 1= ); + else + return sysfs_emit(label, "VBUS_AVG_%d\n", idx + 1); + case PAC1944_VSENSE_1_ADDR: + case PAC1944_VSENSE_2_ADDR: + case PAC1944_VSENSE_3_ADDR: + case PAC1944_VSENSE_4_ADDR: + if (info->labels[idx]) + return sysfs_emit(label, "%s_IBUS_%d\n", info->labels[idx], idx + 1); + else + return sysfs_emit(label, "IBUS_%d\n", idx + 1); + case PAC1944_VSENSE_AVG_1_ADDR: + case PAC1944_VSENSE_AVG_2_ADDR: + case PAC1944_VSENSE_AVG_3_ADDR: + case PAC1944_VSENSE_AVG_4_ADDR: + if (info->labels[idx]) + return sysfs_emit(label, "%s_IBUS_AVG_%d\n", info->labels[idx], idx + 1= ); + else + return sysfs_emit(label, "IBUS_AVG_%d\n", idx + 1); + case PAC1944_VPOWER_1_ADDR: + case PAC1944_VPOWER_2_ADDR: + case PAC1944_VPOWER_3_ADDR: + case PAC1944_VPOWER_4_ADDR: + if (info->labels[idx]) + return sysfs_emit(label, "%s_POWER_%d\n", info->labels[idx], idx + 1); + else + return sysfs_emit(label, "POWER_%d\n", idx + 1); + } + + return 0; +} + +static int pac1944_read_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir, enum iio_event_info info, + int *val, int *val2) +{ + struct pac1944_chip_info *chip_info =3D iio_priv(indio_dev); + int idx; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + guard(mutex)(&chip_info->lock); + + switch (chan->type) { + case IIO_VOLTAGE: + switch (dir) { + case IIO_EV_DIR_RISING: + *val =3D chip_info->overvoltage[idx]; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + *val =3D chip_info->undervoltage[idx]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CURRENT: + switch (dir) { + case IIO_EV_DIR_RISING: + *val =3D chip_info->overcurrent[idx]; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + *val =3D chip_info->undercurrent[idx]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_POWER: + switch (dir) { + case IIO_EV_DIR_RISING: + *val =3D chip_info->overpower[idx]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int pac1944_write_thresh(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, enum iio_event_type type, + enum iio_event_direction dir, enum iio_event_info info, + int val, int val2) +{ + struct pac1944_chip_info *chip_info =3D iio_priv(indio_dev); + int idx, ret; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + guard(mutex)(&chip_info->lock); + + switch (chan->type) { + case IIO_VOLTAGE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret =3D pac1944_update_alert_16b(&indio_dev->dev, + PAC1944_OV_LIMIT_REG_ADDR + idx, + pac1944_overvoltage_mask_tbl[idx], val); + if (ret) + return ret; + + chip_info->overvoltage[idx] =3D val; + return 0; + case IIO_EV_DIR_FALLING: + ret =3D pac1944_update_alert_16b(&indio_dev->dev, + PAC1944_UV_LIMIT_REG_ADDR + idx, + pac1944_undervoltage_mask_tbl[idx], val); + if (ret) + return ret; + + chip_info->undervoltage[idx] =3D val; + return 0; + default: + return -EINVAL; + } + case IIO_CURRENT: + switch (dir) { + case IIO_EV_DIR_RISING: + ret =3D pac1944_update_alert_16b(&indio_dev->dev, + PAC1944_OC_LIMIT_REG_ADDR + idx, + pac1944_overcurrent_mask_tbl[idx], val); + if (ret) + return ret; + + chip_info->overcurrent[idx] =3D val; + return ret; + case IIO_EV_DIR_FALLING: + ret =3D pac1944_update_alert_16b(&indio_dev->dev, + PAC1944_UC_LIMIT_REG_ADDR + idx, + pac1944_undercurrent_mask_tbl[idx], val); + if (ret) + return ret; + + chip_info->undercurrent[idx] =3D val; + return 0; + default: + return -EINVAL; + } + case IIO_POWER: + switch (dir) { + case IIO_EV_DIR_RISING: + ret =3D pac1944_update_alert_24b(&indio_dev->dev, + PAC1944_OP_LIMIT_REG_ADDR + idx, + pac1944_overpower_mask_tbl[idx], + val); + if (ret) + return ret; + + chip_info->overpower[idx] =3D val; + return 0; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int pac1944_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + int idx; + u32 tmp; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + scoped_guard(mutex, &info->lock) { + switch (chan->type) { + case IIO_VOLTAGE: + switch (dir) { + case IIO_EV_DIR_RISING: + tmp =3D FIELD_GET(PAC1944_OV_MASK, info->alert_enable); + break; + case IIO_EV_DIR_FALLING: + tmp =3D FIELD_GET(PAC1944_UV_MASK, info->alert_enable); + break; + default: + return -EINVAL; + } + return -EINVAL; + case IIO_CURRENT: + switch (dir) { + case IIO_EV_DIR_RISING: + tmp =3D FIELD_GET(PAC1944_OC_MASK, info->alert_enable); + break; + case IIO_EV_DIR_FALLING: + tmp =3D FIELD_GET(PAC1944_UC_MASK, info->alert_enable); + break; + default: + return -EINVAL; + } + return -EINVAL; + case IIO_POWER: + if (dir =3D=3D IIO_EV_DIR_RISING) + tmp =3D FIELD_GET(PAC1944_OP_MASK, info->alert_enable); + else + return -EINVAL; + break; + default: + return -EINVAL; + } + } + + tmp =3D tmp >> (3 - idx); + + return tmp & 0x01; +} + +static int pac1944_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct pac1944_chip_info *info =3D iio_priv(indio_dev); + struct i2c_client *client =3D info->client; + int idx, val, mask, ret; + bool update =3D false; + u8 tmp[PAC1944_ALERT_ENABLE_REG_LEN]; + + /* into the datasheet channels are noted from 1 to 4 */ + idx =3D chan->channel - 1; + + switch (chan->type) { + case IIO_VOLTAGE: + switch (dir) { + case IIO_EV_DIR_RISING: + mask =3D pac1944_overvoltage_mask_tbl[idx]; + break; + case IIO_EV_DIR_FALLING: + mask =3D pac1944_undervoltage_mask_tbl[idx]; + break; + default: + return -EINVAL; + } + break; + case IIO_CURRENT: + switch (dir) { + case IIO_EV_DIR_RISING: + mask =3D pac1944_overcurrent_mask_tbl[idx]; + break; + case IIO_EV_DIR_FALLING: + mask =3D pac1944_undercurrent_mask_tbl[idx]; + break; + default: + return -EINVAL; + } + break; + case IIO_POWER: + if (dir !=3D IIO_EV_DIR_RISING) + return -EINVAL; + + mask =3D pac1944_overpower_mask_tbl[idx]; + break; + default: + return -EINVAL; + } + + guard(mutex)(&info->lock); + + val =3D info->alert_enable & mask; + if (state && !val) { + /* enable the event in hardware */ + info->alert_enable |=3D mask; + update =3D true; + } else if (!state && val) { + /* disable the event in hardware */ + info->alert_enable &=3D ~mask; + update =3D true; + } + + /* do not update if not needed */ + if (update) { + put_unaligned_be24(info->alert_enable, &tmp[0]); + + /* update the Alert enable register */ + ret =3D pac1944_restore_alert_reg(indio_dev, &tmp[0]); + if (ret) { + dev_err(&client->dev, "failing to restore alert reg\n"); + return ret; + } + } + + return 0; +} + +static void pac1944_work_periodic_rfsh(struct work_struct *work) +{ + struct pac1944_chip_info *info =3D to_pac1944_chip_info(to_delayed_work(w= ork)); + struct i2c_client *client =3D info->client; + + dev_dbg(&client->dev, "Periodic refresh\n"); + + pac1944_reg_snapshot(info, true, PAC1944_REFRESH_REG_ADDR, + PAC1944_MIN_UPDATE_WAIT_TIME_US); + + schedule_delayed_work(&info->work_chip_rfsh, + msecs_to_jiffies(PAC1944_MAX_RFSH_LIMIT_MS)); +} + +/* + * Universal Unique Identifier (UUID), + * 721F1534-5D27-4B60-9DF4-41A3C4B7DA3A, + * is reserved to Microchip for the PAC194x and PAC195x. + */ +#define PAC1944_DSM_UUID "721F1534-5D27-4B60-9DF4-41A3C4B7DA3A" + +/* + * documentation related to the ACPI device definition + * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/Product= Documents/UserGuides/PAC194X_5X-UEFI-BIOS-Integration-and-Microsoft-Windows= -10-and-Windows-11-Energy-Meter-Interface-Device-Driver-Users-Guide-DS50003= 155.pdf + */ +static int pac1944_acpi_parse_channel_config(struct i2c_client *client, + struct pac1944_chip_info *info) +{ + acpi_handle handle; + union acpi_object *rez; + struct device *dev =3D &client->dev; + unsigned short bi_dir_mask; + int i; + guid_t guid; + const struct acpi_device_id *id; + + handle =3D ACPI_HANDLE(dev); + + id =3D acpi_match_device(dev->driver->acpi_match_table, dev); + if (!id) + return -ENODEV; + + guid_parse(PAC1944_DSM_UUID, &guid); + + rez =3D acpi_evaluate_dsm(handle, &guid, 0, PAC1944_ACPI_GET_NAMES, NULL); + if (!rez) + return -EINVAL; + + for (i =3D 0; i < rez->package.count; i++) { + info->labels[i] =3D devm_kmemdup(dev, rez->package.elements[i].string.po= inter, + (size_t)rez->package.elements[i].string.length + 1, + GFP_KERNEL); + info->labels[i][rez->package.elements[i].string.length] =3D '\0'; + } + + ACPI_FREE(rez); + + rez =3D acpi_evaluate_dsm(handle, &guid, 1, PAC1944_ACPI_GET_UOHMS_VALS, = NULL); + if (!rez) + return -EINVAL; + + for (i =3D 0; i < rez->package.count; i++) { + info->shunts[i] =3D rez->package.elements[i].integer.value; + if (info->shunts[i]) + set_bit(i, &info->active_channels_mask); + } + + ACPI_FREE(rez); + + rez =3D acpi_evaluate_dsm(handle, &guid, 1, PAC1944_ACPI_GET_BIPOLAR_SETT= INGS, NULL); + if (!rez) + return -EINVAL; + + for_each_set_bit(i, &info->active_channels_mask, info->phys_channels) { + bi_dir_mask =3D rez->package.elements[i].integer.value; + + if (bi_dir_mask =3D=3D PAC1944_UNIPOLAR_FSR_CFG || + bi_dir_mask =3D=3D PAC1944_BIPOLAR_FSR_CFG || + bi_dir_mask =3D=3D PAC1944_BIPOLAR_HALF_FSR_CFG) { + dev_dbg(dev, "VBUS{%d} mode set to: %d\n", i, bi_dir_mask); + info->chip_reg_data.vbus_mode[i] =3D bi_dir_mask; + } else { + return dev_err_probe(dev, -EINVAL, "invalid vbus-mode value on %i\n", i= ); + } + + bi_dir_mask =3D rez->package.elements[i + PAC1944_MAX_CH].integer.value; + + if (bi_dir_mask =3D=3D PAC1944_UNIPOLAR_FSR_CFG || + bi_dir_mask =3D=3D PAC1944_BIPOLAR_FSR_CFG || + bi_dir_mask =3D=3D PAC1944_BIPOLAR_HALF_FSR_CFG) { + dev_dbg(dev, "VSENSE{%d} mode set to: %d\n", i, bi_dir_mask); + info->chip_reg_data.vsense_mode[i] =3D bi_dir_mask; + } else { + return dev_err_probe(dev, -EINVAL, "invalid vsense-mode value on %i\n",= i); + } + } + + ACPI_FREE(rez); + + rez =3D acpi_evaluate_dsm(handle, &guid, 1, PAC1944_ACPI_GET_SAMP, NULL); + if (!rez) + return -EINVAL; + + info->sample_rate_value =3D rez->package.elements[0].integer.value; + + ACPI_FREE(rez); + + return 0; +} + +static int pac1944_of_parse_channel_config(struct i2c_client *client, + struct pac1944_chip_info *info) +{ + unsigned int current_channel; + struct device *dev =3D &client->dev; + int idx, ret, temp; + bool is_bipolar, is_half_fsr; + + current_channel =3D 1; + + device_for_each_child_node_scoped(dev, child) { + ret =3D fwnode_property_read_u32(child, "reg", &idx); + if (ret) + return dev_err_probe(dev, ret, "reading invalid channel index\n"); + + /* adjust idx to match channel index (1 to 4) from the datasheet */ + idx--; + + if (current_channel >=3D (info->phys_channels + 1) || + idx >=3D info->phys_channels || idx < 0) + return dev_err_probe(dev, -EINVAL, "invalid channel index %d value\n", + idx + 1); + + /* enable channel */ + set_bit(idx, &info->active_channels_mask); + + ret =3D fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", + &info->shunts[idx]); + if (ret) + return dev_err_probe(dev, ret, "%s: invalid shunt-resistor value: %d\n", + fwnode_get_name(child), info->shunts[idx]); + + if (fwnode_property_present(child, "label")) + fwnode_property_read_string(child, "label", + (const char **)&info->labels[idx]); + + is_bipolar =3D false; + if (fwnode_property_present(child, "microchip,vbus-bipolar")) + is_bipolar =3D true; + + is_half_fsr =3D false; + if (fwnode_property_present(child, "microchip,vbus-half-range")) + is_half_fsr =3D true; + + /* default value is unipolar and Full Scale Range */ + info->chip_reg_data.vbus_mode[idx] =3D PAC1944_UNIPOLAR_FSR_CFG; + if (is_half_fsr) + info->chip_reg_data.vbus_mode[idx] =3D PAC1944_BIPOLAR_HALF_FSR_CFG; + else if (is_bipolar) + info->chip_reg_data.vbus_mode[idx] =3D PAC1944_BIPOLAR_FSR_CFG; + + is_bipolar =3D false; + if (fwnode_property_present(child, "microchip,vsense-bipolar")) + is_bipolar =3D true; + + is_half_fsr =3D false; + if (fwnode_property_present(child, "microchip,vsense-half-range")) + is_half_fsr =3D true; + + /* default value is unipolar and Full Scale Range */ + info->chip_reg_data.vsense_mode[idx] =3D PAC1944_UNIPOLAR_FSR_CFG; + if (is_half_fsr) + info->chip_reg_data.vsense_mode[idx] =3D PAC1944_BIPOLAR_HALF_FSR_CFG; + else if (is_bipolar) + info->chip_reg_data.vsense_mode[idx] =3D PAC1944_BIPOLAR_FSR_CFG; + + ret =3D fwnode_property_read_u32(child, "microchip,accumulation-mode", &= temp); + if (ret) + return dev_err_probe(dev, ret, "invalid accumulation-mode value on %s\n= ", + fwnode_get_name(child)); + if (temp =3D=3D PAC1944_ACCMODE_VPOWER || + temp =3D=3D PAC1944_ACCMODE_VSENSE || + temp =3D=3D PAC1944_ACCMODE_VBUS) { + dev_dbg(dev, "Accumulation{%d} mode set to: %d\n", idx, temp); + info->chip_reg_data.accumulation_mode[idx] =3D temp; + } else { + return dev_err_probe(dev, -EINVAL, + "invalid mode for accumulator value on %s\n", + fwnode_get_name(child)); + } + current_channel++; + } + + return 0; +} + +static void pac1944_cancel_delayed_work(void *dwork) +{ + cancel_delayed_work_sync(dwork); +} + +static int pac1944_chip_identify(struct pac1944_chip_info *info) +{ + int ret =3D 0; + struct i2c_client *client =3D info->client; + u8 chip_rev_info[3]; + + ret =3D i2c_smbus_read_i2c_block_data(client, PAC1944_PID_REG_ADDR, + sizeof(chip_rev_info), + chip_rev_info); + if (ret < 0) + return dev_err_probe(&client->dev, ret, "cannot read revision\n"); + + dev_info(&client->dev, "Chip revision: 0x%02X\n", chip_rev_info[2]); + info->chip_revision =3D chip_rev_info[2]; + info->chip_variant =3D chip_rev_info[0]; + + switch (chip_rev_info[0]) { + case PAC_PRODUCT_ID_1941: + case PAC_PRODUCT_ID_1942: + case PAC_PRODUCT_ID_1943: + case PAC_PRODUCT_ID_1944: + case PAC_PRODUCT_ID_1941_2: + case PAC_PRODUCT_ID_1942_2: + info->is_pac195x_family =3D false; + return chip_rev_info[0] - PAC_PRODUCT_ID_1941; + case PAC_PRODUCT_ID_1951: + case PAC_PRODUCT_ID_1952: + case PAC_PRODUCT_ID_1953: + case PAC_PRODUCT_ID_1954: + case PAC_PRODUCT_ID_1951_2: + case PAC_PRODUCT_ID_1952_2: + info->is_pac195x_family =3D true; + return (chip_rev_info[0] - PAC_PRODUCT_ID_1951) + + (PAC_PRODUCT_ID_1942_2 - PAC_PRODUCT_ID_1941) + 1; + default: + dev_err(&client->dev, + "product ID (0x%02X, 0x%02X, 0x%02X) for this part doesn't match\n", + chip_rev_info[0], chip_rev_info[1], chip_rev_info[2]); + return -EINVAL; + } +} + +static int pac1944_chip_configure(struct pac1944_chip_info *info) +{ + int cnt, ret; + struct i2c_client *client =3D info->client; + u8 regs[PAC1944_ALERTS_REG_LEN]; + u8 *offset_p; + u32 wait_time; + u8 tmp_u8; + __be16 tmp_be16; + u16 cfg; + + /* + * Counting how many channels are enabled and store + * this information within the driver data + */ + info->num_enabled_channels =3D hweight_long(info->active_channels_mask); + + /* get sampling rate from PAC */ + ret =3D i2c_smbus_read_i2c_block_data(client, PAC1944_CTRL_REG_ADDR, + sizeof(tmp_be16), (u8 *)&tmp_be16); + if (ret < 0) + return dev_err_probe(&client->dev, ret, "cannot read CTRL reg\n"); + + info->sampling_mode =3D FIELD_GET(PAC1944_CTRL_SAMPLE_MASK, be16_to_cpu(t= mp_be16)); + + /* + * The current/voltage can be measured unidirectional, bidirectional or h= alf FSR + * no SLOW triggered REFRESH, clear POR + */ + cfg =3D FIELD_PREP(PAC1944_NEG_PWR_CFG_VS1_MASK, info->chip_reg_data.vsen= se_mode[0]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VS2_MASK, info->chip_reg_data.vsense_mode= [1]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VS3_MASK, info->chip_reg_data.vsense_mode= [2]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VS4_MASK, info->chip_reg_data.vsense_mode= [3]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VB1_MASK, info->chip_reg_data.vbus_mode[0= ]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VB2_MASK, info->chip_reg_data.vbus_mode[1= ]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VB3_MASK, info->chip_reg_data.vbus_mode[2= ]) | + FIELD_PREP(PAC1944_NEG_PWR_CFG_VB4_MASK, info->chip_reg_data.vbus_mode[3= ]); + + ret =3D i2c_smbus_write_word_data(client, PAC1944_NEG_PWR_FSR_REG_ADDR, c= pu_to_be16(cfg)); + if (ret) + return dev_err_probe(&client->dev, ret, "cannot write NEG_PWR_FSR reg\n"= ); + + ret =3D i2c_smbus_write_word_data(client, PAC1944_SLOW_REG_ADDR, 0); + if (ret) + return dev_err_probe(&client->dev, ret, "cannot write SLOW reg\n"); + + /* Write the CHANNEL_N_OFF from CTRL REGISTER */ + cfg =3D FIELD_PREP(PAC1944_CTRL_SAMPLE_MASK, info->sampling_mode) | + FIELD_PREP(PAC1944_CTRL_GPIO_ALERT2_MASK, 0) | + FIELD_PREP(PAC1944_CTRL_SLOW_ALERT1_MASK, 0) | + FIELD_PREP(PAC1944_CTRL_CH_1_OFF_MASK, !test_bit(0, &info->active_channe= ls_mask)) | + FIELD_PREP(PAC1944_CTRL_CH_2_OFF_MASK, !test_bit(1, &info->active_channe= ls_mask)) | + FIELD_PREP(PAC1944_CTRL_CH_3_OFF_MASK, !test_bit(2, &info->active_channe= ls_mask)) | + FIELD_PREP(PAC1944_CTRL_CH_4_OFF_MASK, !test_bit(3, &info->active_channe= ls_mask)); + + ret =3D i2c_smbus_write_word_data(client, PAC1944_CTRL_REG_ADDR, cpu_to_b= e16(cfg)); + if (ret) + return dev_err_probe(&client->dev, ret, "cannot write CTRL reg\n"); + + tmp_u8 =3D ACCUM_REG(info->chip_reg_data.accumulation_mode[0], + info->chip_reg_data.accumulation_mode[1], + info->chip_reg_data.accumulation_mode[2], + info->chip_reg_data.accumulation_mode[3]); + + ret =3D i2c_smbus_write_byte_data(client, PAC1944_ACCUM_CFG_REG_ADDR, tmp= _u8); + if (ret) + return dev_err_probe(&client->dev, ret, "cannot write ACCUM_CFG reg\n"); + + /* reading all alerts, status and limits related registers */ + ret =3D pac1944_i2c_read(client, PAC1944_ALERT_STATUS_REG_ADDR, regs, siz= eof(regs)); + if (ret < 0) + return dev_err_probe(&client->dev, ret, "cannot read ALERT_STATUS reg\n"= ); + + offset_p =3D ®s[0]; + + /* skip alert_status register*/ + offset_p +=3D 3; + + info->slow_alert1 =3D get_unaligned_be24(offset_p); + offset_p +=3D 3; + + info->gpio_alert2 =3D get_unaligned_be24(offset_p); + offset_p +=3D 3; + + info->acc_fullness =3D get_unaligned_be16(offset_p); + offset_p +=3D 2; + + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) { + info->overcurrent[cnt] =3D get_unaligned_be16(offset_p); + offset_p +=3D 2; + } + + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) { + info->undercurrent[cnt] =3D get_unaligned_be16(offset_p); + offset_p +=3D 2; + } + + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) { + info->overpower[cnt] =3D get_unaligned_be24(offset_p); + offset_p +=3D 3; + } + + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) { + info->overvoltage[cnt] =3D get_unaligned_be16(offset_p); + offset_p +=3D 2; + } + + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) { + info->undervoltage[cnt] =3D get_unaligned_be16(offset_p); + offset_p +=3D 2; + } + + offset_p +=3D 1; + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) + info->oc_limit_nsamples[cnt] =3D (*offset_p >> (2 * cnt)) & 0x03; + + offset_p +=3D 1; + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) + info->uc_limit_nsamples[cnt] =3D (*offset_p >> (2 * cnt)) & 0x03; + + offset_p +=3D 1; + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) + info->op_limit_nsamples[cnt] =3D (*offset_p >> (2 * cnt)) & 0x03; + + offset_p +=3D 1; + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) + info->ov_limit_nsamples[cnt] =3D (*offset_p >> (2 * cnt)) & 0x03; + + offset_p +=3D 1; + for (cnt =3D 0; cnt < PAC1944_MAX_CH; cnt++) + info->uv_limit_nsamples[cnt] =3D (*offset_p >> (2 * cnt)) & 0x03; + + offset_p +=3D 1; + info->alert_enable =3D get_unaligned_be24(offset_p); + + /* + * Sending a REFRESH to the chip, so the new settings take place + * as well as resetting the accumulators + */ + ret =3D i2c_smbus_write_byte(client, PAC1944_REFRESH_REG_ADDR); + if (ret) + return dev_err_probe(&client->dev, ret, "cannot write REFRESH reg\n"); + + /* + * Get the current (in the chip) sampling speed and compute the + * required timeout based on its value the timeout is 1/sampling_speed + * wait the maximum amount of time to be on the safe side - the + * maximum wait time is for 8sps + */ + wait_time =3D (1024 / pac1944_samp_rate_map_tbl[info->sampling_mode]) * 1= 000; + usleep_range(wait_time, wait_time + 100); + + INIT_DELAYED_WORK(&info->work_chip_rfsh, pac1944_work_periodic_rfsh); + /* Setup the latest moment for reading the regs before saturation */ + schedule_delayed_work(&info->work_chip_rfsh, + msecs_to_jiffies(PAC1944_MAX_RFSH_LIMIT_MS)); + + return devm_add_action_or_reset(&client->dev, pac1944_cancel_delayed_work, + &info->work_chip_rfsh); +} + +static const struct iio_chan_spec pac1944_single_channel[] =3D { + PAC1944_VPOWER_CHANNEL(0, PAC1944_VPOWER_1_ADDR, pac1944_single_event, + ARRAY_SIZE(pac1944_single_event)), + PAC1944_VBUS_CHANNEL(0, PAC1944_VBUS_1_ADDR, pac1944_events, + ARRAY_SIZE(pac1944_events)), + PAC1944_VSENSE_CHANNEL(0, PAC1944_VSENSE_1_ADDR, pac1944_events, + ARRAY_SIZE(pac1944_events)), + PAC1944_VBUS_AVG_CHANNEL(0, PAC1944_VBUS_AVG_1_ADDR), + PAC1944_VSENSE_AVG_CHANNEL(0, PAC1944_VSENSE_AVG_1_ADDR), +}; + +static int pac1944_prep_iio_channels(struct pac1944_chip_info *info, + struct iio_dev *indio_dev) +{ + struct device *dev =3D &info->client->dev; + struct iio_chan_spec *ch_sp; + int channel_size, attribute_count, cnt; + + /* Finding out dynamically how many IIO channels we need */ + attribute_count =3D 0; + channel_size =3D 0; + + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + /* add the size of the properties of one chip physical channel */ + channel_size +=3D sizeof(pac1944_single_channel); + /* count how many enabled channels we have */ + attribute_count +=3D ARRAY_SIZE(pac1944_single_channel); + dev_dbg(dev, ":%s: Channel %d active\n", __func__, cnt + 1); + } + + ch_sp =3D devm_kzalloc(dev, channel_size, GFP_KERNEL); + if (!ch_sp) + return -ENOMEM; + + /* + * Send the updated dynamic channel structure information towards IIO + * prepare the required field for IIO class registration + */ + indio_dev->num_channels =3D attribute_count; + indio_dev->channels =3D ch_sp; + + /* Populate the dynamic channels and make all the adjustments */ + for_each_set_bit(cnt, &info->active_channels_mask, info->phys_channels) { + memcpy(ch_sp, pac1944_single_channel, sizeof(pac1944_single_channel)); + /* + * Into the datasheet channels are noted from 1 to 4 so we will adjust + * the channel to match channel index (1 to 4) from the datasheet + */ + ch_sp[PAC1944_CH_POWER].channel =3D cnt + 1; + ch_sp[PAC1944_CH_POWER].address =3D cnt + PAC1944_VPOWER_1_ADDR; + ch_sp[PAC1944_CH_VOLTAGE].channel =3D cnt + 1; + ch_sp[PAC1944_CH_VOLTAGE].address =3D cnt + PAC1944_VBUS_1_ADDR; + ch_sp[PAC1944_CH_CURRENT].channel =3D cnt + 1; + ch_sp[PAC1944_CH_CURRENT].address =3D cnt + PAC1944_VSENSE_1_ADDR; + /* + * In order to be able to use labels for PAC1944_CH_VOLTAGE and + * PAC1944_CH_VOLTAGE_AVERAGE, respectively PAC1944_CH_CURRENT + * and PAC1944_CH_CURRENT_AVERAGE we need to use different channel numbe= rs. + * We will add +5 (+1 to maximum PAC channels). + */ + ch_sp[PAC1944_CH_VOLTAGE_AVERAGE].channel =3D cnt + PAC1944_MAX_CH + 1; + ch_sp[PAC1944_CH_VOLTAGE_AVERAGE].address =3D cnt + PAC1944_VBUS_AVG_1_A= DDR; + ch_sp[PAC1944_CH_CURRENT_AVERAGE].channel =3D cnt + PAC1944_MAX_CH + 1; + ch_sp[PAC1944_CH_CURRENT_AVERAGE].address =3D cnt + PAC1944_VSENSE_AVG_1= _ADDR; + + /* advance the pointer */ + ch_sp +=3D ARRAY_SIZE(pac1944_single_channel); + } + + return 0; +} + +static const struct iio_info pac1944_info =3D { + .read_raw =3D pac1944_read_raw, + .read_label =3D pac1944_read_label, + .read_event_value =3D pac1944_read_thresh, + .write_event_value =3D pac1944_write_thresh, + .read_event_config =3D pac1944_read_event_config, + .write_event_config =3D pac1944_write_event_config, +}; + +static int pac1944_probe(struct i2c_client *client) +{ + struct pac1944_chip_info *info; + struct iio_dev *indio_dev; + const struct pac1944_features *chip; + int cnt, ret; + struct device *dev =3D &client->dev; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info =3D iio_priv(indio_dev); + info->client =3D client; + + ret =3D pac1944_chip_identify(info); + if (ret < 0) { + dev_dbg(dev, "Failed to identify the device based on HW ID\n"); + /* + * If failed to identify the hardware based on internal registers, + * try using fallback compatible in device tree to deal with + * some newer part number. + */ + chip =3D i2c_get_match_data(client); + if (!chip) + return -EINVAL; + + info->chip_variant =3D chip->prod_id; + info->phys_channels =3D chip->phys_channels; + indio_dev->name =3D chip->name; + } else { + info->phys_channels =3D pac1944_chip_config[ret].phys_channels; + indio_dev->name =3D pac1944_chip_config[ret].name; + } + + for (cnt =3D 0; cnt < info->phys_channels; cnt++) { + /* always start with accumulation channels enabled */ + info->enable_acc[cnt] =3D true; + } + + if (ACPI_HANDLE(dev)) + ret =3D pac1944_acpi_parse_channel_config(client, info); + else + ret =3D pac1944_of_parse_channel_config(client, info); + + if (ret) + return dev_err_probe(dev, ret, "parameter parsing returned an error\n"); + + ret =3D devm_mutex_init(dev, &info->lock); + if (ret < 0) + return ret; + + ret =3D pac1944_chip_configure(info); + if (ret < 0) + return ret; + + ret =3D pac1944_prep_iio_channels(info, indio_dev); + if (ret < 0) + return ret; + + info->iio_info =3D pac1944_info; + indio_dev->info =3D &info->iio_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + ret =3D pac1944_prep_custom_attributes(info, indio_dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Can't configure custom attributes for de= vice\n"); + + ret =3D pac1944_reg_snapshot(info, true, false, + PAC1944_MIN_UPDATE_WAIT_TIME_US); + if (ret < 0) + return ret; + + ret =3D devm_iio_device_register(dev, indio_dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Can't register IIO device\n"); + + return 0; +} + +static const struct i2c_device_id pac1944_id[] =3D { + { .name =3D "pac1941", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1941] }, + { .name =3D "pac19412", .driver_data =3D (kernel_ulong_t)&pac1944_chip_co= nfig[PAC1941_2] }, + { .name =3D "pac1942", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1942] }, + { .name =3D "pac19422", .driver_data =3D (kernel_ulong_t)&pac1944_chip_co= nfig[PAC1942_2] }, + { .name =3D "pac1943", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1943] }, + { .name =3D "pac1944", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1944] }, + { .name =3D "pac1951", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1951] }, + { .name =3D "pac19512", .driver_data =3D (kernel_ulong_t)&pac1944_chip_co= nfig[PAC1951_2] }, + { .name =3D "pac1952", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1952] }, + { .name =3D "pac19522", .driver_data =3D (kernel_ulong_t)&pac1944_chip_co= nfig[PAC1952_2] }, + { .name =3D "pac1953", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1953] }, + { .name =3D "pac1954", .driver_data =3D (kernel_ulong_t)&pac1944_chip_con= fig[PAC1954] }, + { } +}; +MODULE_DEVICE_TABLE(i2c, pac1944_id); + +static const struct of_device_id pac1944_of_match[] =3D { + { + .compatible =3D "microchip,pac1941", + .data =3D (void *)&pac1944_chip_config[PAC1941] + }, + { + .compatible =3D "microchip,pac19412", + .data =3D (void *)&pac1944_chip_config[PAC1941_2] + }, + { + .compatible =3D "microchip,pac1942", + .data =3D (void *)&pac1944_chip_config[PAC1942] + }, + { + .compatible =3D "microchip,pac19422", + .data =3D (void *)&pac1944_chip_config[PAC1942_2] + }, + { + .compatible =3D "microchip,pac1943", + .data =3D (void *)&pac1944_chip_config[PAC1943] + }, + { + .compatible =3D "microchip,pac1944", + .data =3D (void *)&pac1944_chip_config[PAC1944] + }, + { + .compatible =3D "microchip,pac1951", + .data =3D (void *)&pac1944_chip_config[PAC1951] + }, + { + .compatible =3D "microchip,pac19512", + .data =3D (void *)&pac1944_chip_config[PAC1951_2] + }, + { + .compatible =3D "microchip,pac1952", + .data =3D (void *)&pac1944_chip_config[PAC1952] + }, + { + .compatible =3D "microchip,pac19522", + .data =3D (void *)&pac1944_chip_config[PAC1952_2] + }, + { + .compatible =3D "microchip,pac1953", + .data =3D (void *)&pac1944_chip_config[PAC1953] + }, + { + .compatible =3D "microchip,pac1954", + .data =3D (void *)&pac1944_chip_config[PAC1954] + }, + { } +}; +MODULE_DEVICE_TABLE(of, pac1944_of_match); + +static const struct acpi_device_id pac1944_acpi_match[] =3D { + { "MCHP1940", .driver_data =3D (kernel_ulong_t)&pac1944_chip_config[PAC19= 44] }, + { } +}; +MODULE_DEVICE_TABLE(acpi, pac1944_acpi_match); + +static struct i2c_driver pac1944_driver =3D { + .driver =3D { + .name =3D "pac1944", + .of_match_table =3D pac1944_of_match, + .acpi_match_table =3D pac1944_acpi_match + }, + .probe =3D pac1944_probe, + .id_table =3D pac1944_id, +}; +module_i2c_driver(pac1944_driver); + +MODULE_AUTHOR("Marius Cristea "); +MODULE_DESCRIPTION("Microchip PAC194X and PAC195X Power Monitor"); +MODULE_LICENSE("GPL"); --=20 2.48.1